JPS59135752A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59135752A JPS59135752A JP58011162A JP1116283A JPS59135752A JP S59135752 A JPS59135752 A JP S59135752A JP 58011162 A JP58011162 A JP 58011162A JP 1116283 A JP1116283 A JP 1116283A JP S59135752 A JPS59135752 A JP S59135752A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- emitter
- collector
- insulating substrate
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48111—Disposition the wire connector extending above another semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
との発明は半導体装置に関し、特に絶縁基板上に複数の
半導体素子を配設した樹脂封止形半導体モジュールから
なる半導体装置に係わるものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The invention relates to a semiconductor device, and particularly to a semiconductor device comprising a resin-sealed semiconductor module in which a plurality of semiconductor elements are disposed on an insulating substrate.
近年、電子機器の発達は著るしく、機器の高集鞘化、小
形軽知化が急速に進んでおり、その基本的なものは半導
体装置の小形化である。そしてなかでも中容量の電力用
半導体素子として、以前はサイリスタが主力に使用され
てきたが、トランジスタの大容量化に伴ない、周辺回路
の簡略化、スイッチングタイムの短縮化などの特性上の
り１１点から、このトランジスタがサイリスタに換えら
れるようになってきでおり、またパワー素子を複数個組
み合わせて単一パッケージ化した７いわゆるパワーモジ
ュールの分野においてもこのトランジスタの進出が活発
になっている。BACKGROUND ART In recent years, electronic devices have made remarkable progress, and devices are rapidly becoming more highly integrated, smaller, and more intelligent, and the basic element of this is the miniaturization of semiconductor devices. In the past, thyristors were mainly used as medium-capacity power semiconductor devices, but with the increase in transistor capacity, improvements in characteristics such as simplification of peripheral circuits and shortening of switching time11 As a result, this transistor has come to be replaced by a thyristor, and this transistor is also actively used in the field of so-called power modules, in which a plurality of power devices are combined into a single package.
こ＼でこのようなパワーモジ、コーールにあっては、機
器への糺み込みを容易にするために、半導体装置内で電
極を絶縁した。いわゆる絶縁タイプのモジュールが多く
なっており、この絶縁タイプのパワーモジュールの大容
量化については、複数のチップをバラ接続することによ
る電流分相の問題もさること乍ら、電極下面の絶縁基板
の大形化に伴う種々の問題がある。In these power modules and calls, the electrodes were insulated within the semiconductor device to facilitate integration into equipment. There are many so-called insulated type modules, and in order to increase the capacity of these insulated type power modules, there is the problem of current phase splitting caused by connecting multiple chips separately, as well as the problem of current phase separation due to the insulating substrate on the bottom surface of the electrode. There are various problems associated with increasing the size.
従来のこの種の半導体装置の植装構成を第１図および第
２図に示しである。これらの各図において、放熱板（１
）に固着された絶縁基板（２）上には、それぞれにエミ
ッタ電極（３）、コレクタ拓′極（４）、およ０：ヘ−
スミ極（５）が接着され、かつコレクタ電極ｆ極（１４
上にこの場合、４個のトランジスタチップ（６）が設ケ
ラれており、各トランジスタチップ（６）の上面のエミ
ッタパットおよびベースパッドと、それぞれ対応するエ
ミッタを極（３〕、ベース電極（５）とをアルミ配ｆＩ
Ｍ（７）によりワイヤボンド接続して、各トランジスタ
ナツプ（６）のパラ接続をなしている。そし′（この構
成にあって、前記エミッタ電極（３）とコレクタ電極（
４）とからは、それぞれに外部箱棒が立ち上っているが
、拌・１図には立ち上る以前の状態が水爆れている。芒
らにこのように構成はｔＬる半樽体モジュール刊み立て
体は、別のし１示しない外装容器に納められ、前記各外
部′ｉ′極の上端部を残し、これを樹脂封止して完成畑
れる。The conventional implantation configuration of this type of semiconductor device is shown in FIGS. 1 and 2. In each of these figures, the heat sink (1
), on which are respectively an emitter electrode (3), a collector electrode (4), and a 0:H-
A sumi pole (5) is glued, and a collector electrode f pole (14
In this case, four transistor chips (6) are installed on the top, and the emitter pad and base pad on the top surface of each transistor chip (6) and the corresponding emitter are connected to the pole (3) and the base electrode (5). ) and the aluminum
A wire bond connection is made through M(7) to form a parallel connection between each transistor nap (6). (In this configuration, the emitter electrode (3) and the collector electrode (
4) External box rods are rising from each of them, but in Figure 1, the state before they rise is a water bomb. The half-barrel module assembly having the above configuration is housed in a separate outer container (not shown), and the upper end of each external 'i' pole is left, and this is sealed with resin. Then the field will be completed.
従ってこの従来装置の場合にあっては、各トランジスタ
チップ（６）のサイズが大きくなっｆＣ妙、あるいはそ
の個数が多くなると、これに比例してコレクタ電極（４
）の面私が大きくｌす、かつ下面の絶縁基板Ｃ）も大形
化せさるを得ず、これによって絶縁基板（２）自体に反
りを生ずることになる。例えば絶縁基板（２）が４０Ｘ
４０朋程度の大きさになると、０．３〜０４朋桿度の反
りを生じて、下面放熱板（１）との間の固着が困難にな
り、捷た放熱板（１）への固着の際の熱歪が大きくなっ
て、絶縁基板（２）に割れを生ずることすらある。そし
てまた同時に各トランジスタチップ（６）をエミッタＮ
極（３）とベースＮ極（５）にアルミ配線（７）で接続
するのす、配線相互が接触し易くて配線作業が困難にな
るほか、各アルミ配線（７）の長さがチップ毎に異なり
（例えば第１図にあって左側のチップは右側のチップに
比較１〜でエミッタ配線長が２倍近くなる）、各トラン
ジスタチップ（６）の電流バランスが悪くなるという問
題を生ずる。Therefore, in the case of this conventional device, as the size of each transistor chip (6) increases and the number of transistor chips (6) increases, the collector electrode (4) increases in proportion to this.
) is made large, and the insulating substrate (C) on the bottom side is also unavoidably enlarged, which causes warping of the insulating substrate (2) itself. For example, the insulating substrate (2) is 40X
When the size is about 40 mm, a warpage of 0.3 to 0.4 mm will occur, making it difficult to adhere to the lower heat sink (1), making it difficult to adhere to the broken heat sink (1). The resulting thermal strain may even increase, causing cracks in the insulating substrate (2). And at the same time, each transistor chip (6) is connected to the emitter N
When connecting the pole (3) and the base N-pole (5) with the aluminum wire (7), the wires tend to come into contact with each other, making wiring work difficult, and the length of each aluminum wire (7) is different for each chip. (For example, in FIG. 1, the chip on the left side has nearly twice the emitter wiring length as compared to the chip on the right side.) This causes a problem that the current balance of each transistor chip (6) becomes poor.
このように従沫の半導体装置にあっては、大容量化のた
めにＰ縁基板が大形化して（ｌ’性を損なうと共に、チ
ップとｉｆｆ間の配線作業の困難さ。In such a semiconductor device, the P-edge substrate becomes large in order to increase the capacity (l' property is lost and wiring work between the chip and the IF becomes difficult).
並びに％作土の問題があり、かつこれを解消するために
、卑純に絶縁基板を分割したので目、名指。In addition, there was a problem of % cropping, and in order to solve this problem, the insulating board was divided into parts.
極を倍近く必要とし、これに伴ないイの間の接続も心裏
″となって、徒らに部品点数が増し、絹み立て作業も複
雑になるものであった。Nearly twice the number of poles was required, and the connection between the two wires was also complicated, which unnecessarily increased the number of parts and made the silk-making process more complicated.
この発明は従来のこのような欠点に鑑み、分割した絶縁
基板上にあって、各ベース電極と共に、各基板に共通の
コレクタ、およびエミッタ各電極を配した構成とし、こ
れによって組み立て並びに配線作業の簡易化を図り、併
せて信頼性２特性を向上させるようにしたものである。In view of these conventional drawbacks, the present invention has a structure in which a common collector and emitter electrodes are arranged on each divided insulating substrate in addition to each base electrode, thereby simplifying assembly and wiring work. This is intended to simplify the structure and improve two reliability characteristics.
以下、この発明に係わる半導体装置の一実施例につき、
第３図および第４図を参照して詳細に欽明する。Hereinafter, one embodiment of the semiconductor device according to the present invention will be described.
The details will be explained with reference to FIGS. 3 and 4.
第３図および第４図実施例は前記第１図および第２図従
来例にそれぞれ対応している。これらの第３図および第
４図において、放熱板（８）には１対の絶縁基板（９）
が固着されており、各絶縁基板（９）上に各１個づ＼の
ベース５極（２）と、双方に共通のエミッタ市、極（１
０） 、およびコレクタ電極０υが接着されている。そ
してこの第３図でも前記第１図と同様に各電極（１０）
、 （ＩＩ）の立ち上り以前の状態を〉トシている。The embodiments shown in FIGS. 3 and 4 correspond to the conventional examples shown in FIGS. 1 and 2, respectively. In these figures 3 and 4, the heat sink (8) has a pair of insulating substrates (9).
are fixed on each insulating substrate (9), and one base 5 pole (2) and an emitter city and pole (1) common to both.
0) and the collector electrode 0υ are bonded. In this figure, each electrode (10) is similar to the figure 1 above.
, the state before the rise of (II) is maintained.
甘たこ＼で双方のコレクタ電極ｏｖ上には、各々２個づ
＼のトランジスタチップα東が接着されていて、前記ベ
ース電極亜とエミッタ電極００）とは、絶縁基板（９）
上にあってこのトランジスタチップＱ３１ 。On both collector electrodes ov, two transistor chips α east are glued, and the base electrode and emitter electrode 00) are connected to an insulating substrate (9).
This transistor chip Q31 is on the top.
ひいてはコレクタ電極αυを挾むように配置されると共
に、名トランジスタチップ（１３の上面のエミッタパッ
ドおよびベースパッドと、それぞれに対応するエミッタ
電極ＧＯ）およびベース電極（２）とをアルミ配線（１
４）によ勺ワイヤボンド接続して、各トランジスタ（至
）のバラ接続をなし、同様に樹脂封止（図示せず）して
完成するものである。Furthermore, the transistor chip (the emitter pad and base pad on the upper surface of 13 and the corresponding emitter electrode GO) and the base electrode (2) are connected to the aluminum wiring (1) so as to sandwich the collector electrode αυ.
4) Connect each transistor (to each other) separately by wire bonding, and complete the process by sealing with resin (not shown) in the same manner.
従ってこの実施例の構成の場合には、分割した２個の絶
縁基板上に、共通のエミッタおよびコレクタ電＠Ｉを配
置するから、大容量化のためにチップ面私が増加したと
しても、絶縁基板の面８ｉを特に大きくシナくてすみ、
これによって絶に基板の反りによる放熱板との固着の困
難さ、並びに熱歪忙よる割れを防止できると共に、各ト
ランジスタチップと配線対象電極とが対応しているため
に、配線作業が容易となるばかりか複雑に絡み合うよう
な惧れがなく、各配線長をも同一にできて電流バランス
がよく、特性を向上し得るのである。Therefore, in the case of the configuration of this embodiment, since the common emitter and collector voltage @I are arranged on two divided insulating substrates, even if the chip surface I increases to increase the capacity, the insulation It is unnecessary to make the surface 8i of the board particularly large,
This absolutely prevents the difficulty of adhering the board to the heat sink due to warpage, as well as cracking due to thermal distortion, and also simplifies wiring work because each transistor chip corresponds to the electrode to be wired. Not only that, there is no risk of complicated intertwining, and each wiring length can be made the same, resulting in good current balance and improved characteristics.
なお前記実施例は絶縁基板を２個に分割した場合である
がより以上の複数個に分割する場合にも適用できること
は勿論である。Although the above embodiment deals with the case where the insulating substrate is divided into two pieces, it is of course applicable to the case where the insulating substrate is divided into a larger number of pieces.
以上詳述したようにこの発明によれは、複数個に分割さ
れた絶縁基板上に、それぞれベース電極と共に、各基板
に共辿のエミッタおよびコレクタ電極を設け、かつトラ
ンジスタチップ′ｆ！：接着するコレクタ電極を挾むよ
うにしてベース電極とエミッタ正極とを配するようにし
たから、従来構成に比較して、部品数を僅かに増すだけ
で、装置の信頼性、紹み立て作業性、ならびに特性な向
上させ利るものである。As described in detail above, according to the present invention, a base electrode and co-tracing emitter and collector electrodes are provided on each substrate on a plurality of divided insulating substrates, and a transistor chip 'f! :Since the base electrode and emitter positive electrode are arranged to sandwich the collector electrode to be bonded, the reliability of the device, ease of installation, and It is useful for improving characteristics.
第１図および第２図は従来例による半導体装置の平面図
および側面図、第３図および第４図はこの発明の一実施
例による半導体装置の平面図および１則面図である。
（８）・・・・放熱板、（９）・・・・絶縁基！、（１
０）・・・・エミッタ和積、０東）・・・・コレクタ電
極、（２）Φ・・・べ−ｘｌｉ、（ハ）・＠φ・トラン
ジスタチップ、α４）φ・・−アルミ配線。
代理人 葛 野 伯 −
第１図
第２図
第３図
第４図FIGS. 1 and 2 are a plan view and a side view of a conventional semiconductor device, and FIGS. 3 and 4 are a plan view and a one-dimensional plan view of a semiconductor device according to an embodiment of the present invention. (8)... Heat sink, (9)... Insulating base! , (1
0)... Emitter sum product, 0 East)... Collector electrode, (2) Φ... Be-xli, (c) @φ transistor chip, α4) φ...-aluminum wiring. Agent Haku Kuzuno - Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
縁基板上には個々のベース電極と共に、各基板共通のエ
ミッタ箱棒、およびコレクタ電極のそれぞれを、トラン
ジスタチップな設けるコレクタ電極対応にベース電極、
エミッタ電極があるように配したととを特徴とする半導
体装置。Multiple insulating substrates are fixed on the heat sink, and on each insulating substrate, an individual base electrode, an emitter box rod common to each substrate, and a collector electrode are installed to correspond to the collector electrode provided on the transistor chip. base electrode,
A semiconductor device characterized by dots arranged so as to have an emitter electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58011162A JPS59135752A (en) | 1983-01-24 | 1983-01-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58011162A JPS59135752A (en) | 1983-01-24 | 1983-01-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59135752A true JPS59135752A (en) | 1984-08-04 |
| JPH0318344B2 JPH0318344B2 (en) | 1991-03-12 |
Family
ID=11770338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58011162A Granted JPS59135752A (en) | 1983-01-24 | 1983-01-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59135752A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4825279A (en) * | 1986-10-08 | 1989-04-25 | Fuji Electric Col, Ltd. | Semiconductor device |
| JPH03145755A (en) * | 1989-10-31 | 1991-06-20 | Fuji Electric Co Ltd | Power conversion device transistor module |
| US6455925B1 (en) * | 2001-03-27 | 2002-09-24 | Ericsson Inc. | Power transistor package with integrated flange for surface mount heat removal |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5021456U (en) * | 1973-06-20 | 1975-03-11 | ||
| JPS56104145U (en) * | 1979-11-20 | 1981-08-14 |
-
1983
- 1983-01-24 JP JP58011162A patent/JPS59135752A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5021456U (en) * | 1973-06-20 | 1975-03-11 | ||
| JPS56104145U (en) * | 1979-11-20 | 1981-08-14 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4825279A (en) * | 1986-10-08 | 1989-04-25 | Fuji Electric Col, Ltd. | Semiconductor device |
| JPH03145755A (en) * | 1989-10-31 | 1991-06-20 | Fuji Electric Co Ltd | Power conversion device transistor module |
| US6455925B1 (en) * | 2001-03-27 | 2002-09-24 | Ericsson Inc. | Power transistor package with integrated flange for surface mount heat removal |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0318344B2 (en) | 1991-03-12 |
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