JPS59135749A - Formation of interlayer insulating film - Google Patents

Abstract

PURPOSE:To eliminate the surface stepping of an interlayer insulating film by a method wherein the stepping on the surface of a substrate is filled up and flattened before formation of the interlayer insulating film. CONSTITUTION:An interlayer insulating film 13a is formed on the semiconductor substrate 11, whereon the first layer of metal wiring 12 is formed, is provided by performing a plasma CVD or a vapor-deposition or the like, and a resist 14 is formed in the recessed part of the interlayer insulating film 13a. The interlayer insulating film 13a is removed using the resist 14 as a mask, and the resist 14 is then removed, thereby enabling to fill up the recessed part of the substrate 11 formed by the metal wiring 12 and the surface is flattened. Subsequently, an interlayer insulating film 13b is formed, and the interlayer insulating film having no stepping is obtained.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for forming an interlayer insulating film during the manufacture of semiconductor devices. [Prior Art] A process for forming an interlayer insulating film of this type according to a conventional example The different forms are shown in Figures 1 and 2. In these figures, (1) is a semiconductor substrate such as silicon, and (2) is a semiconductor substrate such as aluminum formed on this substrate. 1st layer metal wiring,
(3) is an interlayer insulating film such as a silicon oxide film or silicon nitride film necessary to form a multilayer wiring of the second layer or higher on this first M metal wiring (2), and (4) is an adjacent metal wiring. This is a resist layer used to selectively open the interlayer insulating film (3) in order to connect between the layers. It shows the case. .

However, when the metal wiring (2) is formed on the semiconductor substrate (1) as in the conventional example, a step is created on the surface due to the thickness of the metal wiring, and the metal It is well known that when an interlayer insulating film (3) is formed on the wiring (2) by CVD or vapor deposition, this level difference is not particularly alleviated, and sometimes even a larger level difference occurs. There is. Therefore, in order to conduct metal wiring in the soil layer on the interlayer insulating film (3) soil, when a resist (4) is applied by photolithography on the fourth layer (3), the resist layer (4) is applied as shown in FIG. ) is thin, a 5-minute corner of the interlayer insulating film (3) may be exposed at the stepped portion (5), causing problems when etching is performed using the resist pattern as a mask. When the resist layer (4) is thick as shown in the figure, the resolution of the pattern becomes poor, and a fine pattern cannot be obtained, resulting in fTJ degradation in high integration.

[Summary of the invention]

In order to improve these drawbacks of the conventional method, this invention forms the interlayer insulating film in two steps.In the first step, the already formed step is filled and flattened, and then in the next step, the interlayer insulating film is formed in two steps. An interlayer insulating film is formed again, and an interlayer insulating film without surface steps is obtained by combing.

[Embodiments of the invention]

Hereinafter, one embodiment of the method of the present invention will be described in detail with reference to FIGS.

FIG. 3 (5) or Takumi describes this embodiment method in step 111.
TF+m is shown. In each of these figures, in this embodiment method, a semiconductor substrate (11) such as silicon, etc.
For a single layer including a first layer metal wiring (12) made of aluminum or the like, first, a first layer interlayer (mW) (13g) made of, for example, a silicon nitride film is formed by plasma CVD or vapor deposition (as shown in the figure). A)). Next, a positive type EB L such as PMMA is applied to this interlayer insulating film (13a).
/Resist 4) was applied with electron beam (EB).
Alternatively, the ion beam (IB) K, l) is irradiated to expose the ion beam, but at this time, the penetration depth of the beam is 12, which sufficiently reaches the convex portion of the interlayer insulating film (13a), and the same layer (13a) is exposed. control so that it does not reach the recess (see the same figure).

Subsequently, by developing this resist (14), only the four parts of the previous jL interlayer insulation 1 (13a) were developed.
is left behind ((0) in the same figure. Then, using this remaining P resist (14) as a mask, the same interlayer insulating film (13a) is formed.
- Remove by etching using pyroplasmic plasma or wet chemical method. In the case of plasma etching, it is sufficient to remove the mixed residue such as CF4 + H2 (see the same figure). Furthermore, the resist used for the mask (14
), the four parts of the soil of the semiconductor substrate (11) produced by the gold 17.4 arrangement M1 (12), that is, the stepped portions, are removed from the first stage of interlayers covered by the resist (14). The insulating film (13PL) is filled with K and V by -1lJ'L (FIG. 1). Therefore, the second layer of interlayer insulation [4 (13b
), this interlayer insulating film (13b) takes on a form with no surface step ((6) in the same figure).
).

Here, we will specifically examine the relationship between the resist film thickness and the beam penetration depth in the above embodiment.

As mentioned above, when a positive EB resist such as PMMA is coated to a thickness of about 15 μm, even if it is 1.5 μm on the substrate surface, the thickness of the four parts is approximately 2.5 μm depending on the depth and width.
It becomes about 0 to 2.5 μm. Therefore, for example, an electron beam (
EB) at 10 KV about 5×l Q-5c/cm
If 2 irradiations are made, the depth reached will be approximately 15 μm, so
The resist other than the area becomes soluble in the developer. In addition, a hydrogen ion beam was applied at 100KV to approximately 5Xl.
If Oe/cm2 is irradiated fL, the depth reached is approximately 1
．． Since it is 0 μm'11', the thickness of the resist at this time needs to be approximately 1.0/jm. When using PMMA in this way, the developer contains MIBK and I
A mixed solution of PA may be used.

〔Effect of the invention〕

As detailed above, according to the method of the present invention, the semiconductor device t
The formation of the interlayer insulating film during the manufacturing of the semiconductor device is a two-step process, and the first step is to cover the surface of the semiconductor substrate, which has already been formed, by utilizing the control of the exposure penetration depth into the positive resist using photolithography technology. After filling the four-part step with the first stage interlayer insulating film and flattening the -IJ, we formed the interlayer insulating film again in the next step, so we could create a flattened interlayer with no surface steps. An insulating film can be easily obtained, and furthermore, the next process pattern formation in this interlayer separation process can be made finer by GJ, and higher integration of the device can be achieved.

[Brief explanation of the drawing]

FIGS. 1 and 2 show the entire state of resist application in the conventional example, and the resist coating state shown in FIG.
Figure 3 (A) shows an example of the method for forming an interlayer insulating film according to the present invention.
Shizofl-Town [This is a plan. (11)...Semiconductor substrate, (12)...Metal wiring, (13a)...First stage interlayer insulation ij
,,,(13b)...Second stage interlayer resuscitation film, (1
4)・Dispute・Resist. Agent Makoto Kuzuno - Figure 1, 5,4 7″ Figure 2

Claims (1)

[Claims] A first layer of silicon oxide film, silicon nitride film, etc.
A step of forming the interlayer insulating film in the first step by plasma CVD or vapor deposition, a step of applying a positive EI3 resist on the first step interlayer insulating film, and a step of applying an electron beam (EBB) to this resist. ) or by irradiating the resist with an ion beam (IB) to expose the resist except the inside of the recessed portions, and developing the parentheses n, and using the resist on the four parts left by this development as a mask, the first step A step of etching and removing the interlayer insulating film using plasma or a wet chemical method, and filling the inside of the recess with a first stage interlayer insulating film, followed by a step of etching a second stage interlayer insulating film thereon in the same manner as above. 1. A method for forming an interlayer insulating film, the method comprising the step of forming an interlayer insulating film.