JPS59134818A - Semiconductor chip assembled body - Google Patents

Semiconductor chip assembled body

Info

Publication number
JPS59134818A
JPS59134818A JP845383A JP845383A JPS59134818A JP S59134818 A JPS59134818 A JP S59134818A JP 845383 A JP845383 A JP 845383A JP 845383 A JP845383 A JP 845383A JP S59134818 A JPS59134818 A JP S59134818A
Authority
JP
Japan
Prior art keywords
tape
chips
semiconductor chip
holes
strip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP845383A
Other languages
Japanese (ja)
Inventor
Kurahei Tanaka
田中 倉平
Kazuhiro Mori
和弘 森
Eiji Ichitenmanya
一天満谷 英二
Kanji Hata
寛二 秦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP845383A priority Critical patent/JPS59134818A/en
Publication of JPS59134818A publication Critical patent/JPS59134818A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68313Auxiliary support including a cavity for storing a finished device, e.g. IC package, or a partly finished device, e.g. die, during manufacturing or mounting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To perform the continuous stable supply of chips by a method wherein a semiconductor chip is placed in the recess of a band form continuous strip material having a plurality of recesses, apertures are covered with the band form continuous strip material, thus sealing reducing gas in the recesses, and mechanical feeding holes are provided in the continuous strip material. CONSTITUTION:The holes 1a for containing chips 3 are arranged in a tape 1 at equal intervals, tapes 2 and 2a are fixed with an adhesive material 6 by sandwiching the tape 1 on both sides so as to cover the hole 1a, and the reducing gas 5 is introduced to the hole 1a. The chip 3 is contained to the holes 1a by one. The feeding holes 4 corresponding to loading the chips 3 are provided in the tapes 1, 2 and 2a. This constitution makes a containing area small by rolling up the tape and enables to securely carry the chips 3 by utilizing the feeding holes 4. When the tape 2 or 2a is stripped off from the tape 1, one of the chips can be securely taken out and then can be supplied continuously and stably, and besides there is no possibility of oxidation.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体チップの供給、特にダイスボンダ等への
供給に適した半導体チップ集合体に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor chip assembly suitable for supplying semiconductor chips, particularly to a die bonder or the like.

従来例の構成とその問題点 従来、半導体チップは電子回路を構成する基板上に装着
する装置において、装置具への供給方法として第1図に
示す半導体ウニ/・による方法がある。ところがウェー
・の状態で長時間放置していると半導体チップの酸化が
進むとともに、大気中のゴミが付着して不良を発生して
いた。又、ウニ・・状態でマガジンにつめ搬送している
ために大きな容積を必要とする。設備面においてもウニ
・・から1個づつ半導体チップを取り出さなければなら
ず複雑で大きなスペースを必要とした。
2. Description of the Related Art Conventional Structure and Problems Conventionally, in an apparatus in which semiconductor chips are mounted on a substrate constituting an electronic circuit, there is a method of supplying semiconductor chips to the apparatus using a semiconductor urchin shown in FIG. However, if semiconductor chips were left in a wafer state for a long time, oxidation of the semiconductor chips progressed, and dust from the atmosphere adhered to them, causing defects. In addition, since the sea urchins are transported in a magazine, a large capacity is required. In terms of equipment, the semiconductor chips had to be extracted one by one from the sea urchins, making it complicated and requiring a large amount of space.

発明の目的 本発明は、テープ等の帯状長尺材料に半導体チップを等
間隔に積載し一連続安定供給をねらったもので、従来の
欠点を取り除き、理想的な半導体チップの供給を可能に
する半導体チップ集合体を提供しようとするものである
Purpose of the Invention The present invention aims at continuous and stable supply of semiconductor chips by stacking them on a long strip material such as a tape at equal intervals, thereby eliminating the drawbacks of the conventional method and making it possible to supply ideal semiconductor chips. The aim is to provide a semiconductor chip assembly.

発明の構成 本発明は、痺数個の凹みを有する第1の帯状長尺材料と
、この第1の帯状長尺材料の一方の側にあって前記凹み
の開口部を被覆可能な第2の帯状長尺材料とからなり一
前記凹みに半導体チップを載置し、凹み部に還元性ガス
を密封し一帯状長尺材料に機械送り可能力送り案内手段
を設けている。
Structure of the Invention The present invention comprises a first strip-shaped elongated material having several dents, and a second strip-shaped elongated material on one side of the first strip-shaped elongated material that can cover the openings of the dents. A semiconductor chip is placed in one of the recesses, a reducing gas is sealed in the recess, and the belt-like elongate material is provided with force-feeding guide means that can be mechanically fed.

以上の内容から構成されており、半導体チップの連続安
定供給という特有の効果を有する。
Consisting of the above contents, it has the unique effect of providing a continuous and stable supply of semiconductor chips.

実施例の説明 以下1本発明を実施例にもとづき、図面とともに説明す
る。
DESCRIPTION OF EMBODIMENTS The present invention will be described below based on embodiments and with reference to drawings.

第2図および第3図は本発明の一実施例に係る半導体チ
ップ(以下チップという)の集合体であり、図において
1は帯状長尺材料(以下テープという)で、このテープ
1にはチップ3を案内収納できる収納穴1aが等間隔に
配されており、かつテープ1の収納穴1aを被覆するよ
うに両側に−はテープ2および2aが該テープ1を挾み
込み熱圧着あるいは接着剤6又は機械的結合により固定
すると共に、収納穴1aを密封している。収納穴1aを
密封する際収納穴1aには還元性ガス5を注入しである
。チップ3は上記収納穴1aに1個づつ案内収納される
状態にて、テープ1とテープ゛2.2aに治って等間隔
に積載されている。−また、テープ1および2,2aに
はチック゛3の積載に対応して送り穴4が設けられてい
る。
2 and 3 show an assembly of semiconductor chips (hereinafter referred to as chips) according to an embodiment of the present invention. In the figures, 1 is a strip-like long material (hereinafter referred to as tape), and this tape Storage holes 1a for guiding and storing the tape 1 are arranged at equal intervals, and tapes 2 and 2a sandwich the tape 1 on both sides so as to cover the storage hole 1a of the tape 1, and are bonded by thermocompression or adhesive. 6 or mechanically coupled, and the storage hole 1a is sealed. When the storage hole 1a is sealed, a reducing gas 5 is injected into the storage hole 1a. The chips 3 are stacked on the tape 1 and the tape 2.2a at equal intervals, with the chips 3 being guided and stored one by one in the storage holes 1a. -Furthermore, the tapes 1, 2, and 2a are provided with feed holes 4 corresponding to the stacking of ticks 3.

この構造によると−テープ1および2,2aを巻き取れ
ば部品収納面積を大きく必要とせず、また等間隔に設け
た送り穴4を利用してチップ3を多数個連続して確実に
送ることが可能であり、かつチップ3の外部への装着に
際してはテープ2もしくは2aのいずれかをテープ1か
ら離し、テープ1の収納穴1aからチップ3を1個づつ
確実に取り出すことができる等効果が大きい。
According to this structure, if the tapes 1, 2, and 2a are wound up, a large component storage area is not required, and a large number of chips 3 can be reliably fed in succession by using the feed holes 4 provided at equal intervals. This is possible, and has great effects, such as being able to separate either the tape 2 or 2a from the tape 1 and reliably take out the chips 3 one by one from the storage hole 1a of the tape 1 when mounting the chip 3 externally. .

発明の効果 以上のように一本発明によれば半導体チップの酸化を防
止しつつ連続安定供給が可能となるものである。
Effects of the Invention As described above, according to the present invention, it is possible to continuously and stably supply semiconductor chips while preventing their oxidation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例である半導体ウニ・・の斜視図、第2図
は本発明の一実施例の半導体チツ7°集合体の上面図、
第3図は同断面図である。 1・・・・・・(第2の)帯状長尺材料、2・・・・・
・(第1の)帯状長尺材料、2a・・・・・・凹み、3
・・・・・・半導体チップ24・・・・・・送り案内手
段(送り穴)、6・・・・・還元性ガス、6・・・・:
・接着剤。 代理人の氏名 弁理士 中 尾 敏 勇 ほか1名第1
図 第2図 第3図 L
Fig. 1 is a perspective view of a conventional semiconductor chip, and Fig. 2 is a top view of a 7° semiconductor chip assembly according to an embodiment of the present invention.
FIG. 3 is a sectional view of the same. 1... (second) strip-like long material, 2...
・(First) long strip material, 2a... recess, 3
...Semiconductor chip 24...Feeding guide means (feeding hole), 6...Reducing gas, 6...:
·glue. Name of agent: Patent attorney Toshi Isamu Nakao and 1 other person 1st
Figure 2 Figure 3 Figure L

Claims (3)

【特許請求の範囲】[Claims] (1)複数個の凹みを一有する第1の帯状長尺材料と。 この第1の帯状長尺材料の一方の側にあって前記凹みの
開口部を被覆可能な第2の帯状長尺材料とからなり、前
記凹みに半導体チップを載置すると共に、前記凹み内に
還元性ガスを密封した半導体チップ集合体。
(1) A first strip-shaped elongated material having a plurality of depressions. a second strip-shaped elongated material that is on one side of the first strip-shaped elongated material and capable of covering the opening of the recess; A semiconductor chip assembly sealed with reducing gas.
(2)第1.第2の帯状長尺材料のいずれか一方に機械
送り可能な送り案内手段を設けてなる特許請求の範囲第
1項に記載の半導体チップ集合体。
(2) First. 2. The semiconductor chip assembly according to claim 1, wherein either one of the second strip-shaped elongated materials is provided with a feed guide means that can be mechanically fed.
(3)第1の帯状長尺材料と第2の帯状長尺材料とを接
着材料にて固定してなる特許請求の範囲第1項または第
2項に記載の半導体チップ集合体。
(3) The semiconductor chip assembly according to claim 1 or 2, which is formed by fixing a first strip-shaped elongated material and a second strip-shaped elongated material with an adhesive material.
JP845383A 1983-01-20 1983-01-20 Semiconductor chip assembled body Pending JPS59134818A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP845383A JPS59134818A (en) 1983-01-20 1983-01-20 Semiconductor chip assembled body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP845383A JPS59134818A (en) 1983-01-20 1983-01-20 Semiconductor chip assembled body

Publications (1)

Publication Number Publication Date
JPS59134818A true JPS59134818A (en) 1984-08-02

Family

ID=11693542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP845383A Pending JPS59134818A (en) 1983-01-20 1983-01-20 Semiconductor chip assembled body

Country Status (1)

Country Link
JP (1) JPS59134818A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100359718B1 (en) * 1997-11-07 2003-01-15 오리엔트 세미컨덕터 일렉트로닉스 리미티드 Improved supporting device for semi-conductor chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100359718B1 (en) * 1997-11-07 2003-01-15 오리엔트 세미컨덕터 일렉트로닉스 리미티드 Improved supporting device for semi-conductor chip

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