JPS5913419A - Priority encoder circuit - Google Patents

Abstract

PURPOSE:To obtain a priority encoder circuit of which delay time is shortened by connecting an individual logic circuit without cascading in multi-stages and determining the upper bit output of the priority encoder circuit. CONSTITUTION:In the figure, the numbers 43, 45, 47, 49 show signal lines to connect an enabling signal input EI of respective PE-B with the outputs D1, E2, E3, E4 of an enabling input signal determining circuit 35, and the numbers 44, 46, 48, 50 show signal lines to connect an enabling signal output EO of each priority encoder with the inputs G1, G2, G3, G4 of the enabling input signal determining circuit 35. In the circuit, an enabling signal is determined by the enabling input signal determining circuit 35 without transmitting like cascade between respective PE-Bs, so that the delay time until the output logic of Q0-Q4 is determined can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention provides a priority encoder (pri-o
The present invention relates to an m-bit input priority encoder circuit, and particularly to a circuit that uses n m-bit input priority encoder circuits to configure an nm-bit priority encoder.

A conventional device of this type is shown in FIG. The example shown in FIG. 1 shows a case where a 32-pit priority encoder circuit is constructed using four encoders with an 8-bit input priority, and fil, +21
, +31, +41 are 8-bit input priority encoders (hereinafter referred to as T) with the same internal connections, respectively.
8 Tcy3 PE-A or UPE-A). The truth table for 8TG-3PE-A is shown in FIG. That is, the enable signal is rH
J means that there is a higher priority than the PE-A, and therefore the enable signal output E0 becomes rHJ and the next stage 8Tα3 PE
- becomes the EI of A. When EI is rLJ and input signals 0 to 7 are all rLJ, it means that neither the PE-A nor the higher priority exists, and there is no priority request in the input of the PE-A. , so the enable signal output Eαt-1rl,J becomes the next stage 8
T(EI of 9-3PE-A), and the priority can be determined from among the inputs of the next stage.

Inputs 0 to 7 (hereinafter referred to as DOO to DO7, BT
() When 3PE-A is cascaded, the next stage number 0 is DO8
(the priority order is expressed by increasing the number sequentially), the input child number 0 has the highest priority order, and the priority order decreases as the order number increases. Therefore, among the inputs of 1 to 1, a digital number representing the order of the first rHJ is output from the output terminal ABC. A is MSB and C is LS
It is B. For example, when 1 is rHJ, ABC is “LL
When O-5 is all rLJ and τ is rHJ, ABC becomes rHHLJ. The output GS is “L” when a priority request input exists in the PE-A input;
Otherwise, it becomes rHJ.

Next, returning to FIG.
-A (4-pit input type). +61
, +71 and 181 are wired ORs (wir
ed OR). As shown in Figure 1, 8Te3PE
If -A are connected in cascade, only one of the 8TeaPE-A's output ABC becomes rHJ, so a wired OR can be used here. 32 pit input is D0
The priority order decreases in the order of 0→D31. (
t31s (t4 tα→ is [11, +21, (3
This is a signal line that connects 1 in cascade. The enable signal output EO of P E -A (41 is specifically indicated by QZ, DOO~031
When all 0 inputs are rLJ, it becomes rLJ.

Since there is no input with a higher priority than D00, the enable signal EI of Pg-All+ is always set to "L". Ql, Qsece H, IA
is PE −At1l , +21 , +31 , +
Each GS output of 41 is P E”-A + 0.1,2 of 51
゜It is a signal line that connects to each of the three human power sources.

In the circuit shown in FIG. 1, four stages of cascaded 8Tcy3P
E-A tll, f2+, +31, +41
The order in which the input of PE-A should be given priority depends on the BC output of PE-A (5), that is, QO.
, Ql, and the order of which inputs within that PE-A should be given priority is wired-or (6).

+71, +81 outputs, ie, Q21Q3. Since it is indicated by Ql, inputs given priority among DOO to D31 can be indicated by the bit pattern of QOIQllQ21Q31Q4 in the order in which QO is MSB and Ql is LSB. For example, if DOO is rHJ, ABC of P E-At1l becomes “LLLJ” and G
The S output becomes rLJ and 1 of PE-A (5) becomes rHJ, so the BC of PE-At51 becomes rLLJ, and QO to Q4 become rooooooJ pattern and DO
O is selected and DOO~D17 are all r L J Te D1
8 Kar HJ Teare ld'PE-A (3) ABC becomes rLHLJ, GS output becomes rLJ and PE
-A +51 i becomes rHJ, so PF:, -A(
51 BC is r)ILJ, QO~Q4 is rlooo
D18 is selected as a pattern of lOJ.

Since the conventional priority encoder circuit is configured as described above, the lower input, for example, PE-A +
41 input is selected, the signal is sent to the signal line (13
, a4. acJ) Each PE-A +11 via input/output
, +21.

After propagating within +31 and +41, the signal line (2(
Qo
*Q Since the logic of the t bit is determined, there is a drawback that the delay time is long.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional one.In order to avoid cascading 8Tel)3PE-A in multiple stages, a separate logic circuit is provided to control the priority and upper bit output of the encoder circuit. The purpose is to provide a shifter circuit with short delay time by determining .

Hereinafter, the present invention will be described in detail with reference to the drawings. Third
The figure is a block diagram showing one embodiment of the present invention, and DOO~
p31 and QO to Q4 indicate the same input/output signals as the same reference numerals in FIG. 1, (3S, C32), (33).

(34) are +11, +31, and +31 in Figure 1, respectively.
8-bit input priority encoder (hereinafter referred to as BT(!) 3PE-B or 1' corresponding to +31 and +41)
1PE-B). (35) it is an enable input signal determination circuit; (36) and (37
) and (38) are +61 and +7 in Figure 1, respectively.
1, wired or similar to +81, (43), (4
5) t(47), (49) are the enable signal EI of each PE-B and the output El', E2. E3. Signal lines (44), (46), (48), and (50) connecting the enable signal output EO of each PE-B and the input Gl, G2 . G3. These are signal lines that respectively connect G4.

Figure 4 shows the truth table of 8Tc)3PE-B and E
When I is rHJ, EO can be rHJ or rLJ, and when all inputs from θ to 7 are rLJ, E
Regardless of the logic of I, ABC is rLLLJ and Eα is rLJ, but it is the same as in FIG.

Therefore, wired or (36), (37),
(38) output Q2゜Q3. Q4 is determined similarly to conventional circuits.

FIG. 5 shows the truth table of the enable signal input determination circuit (35), and Ey r Exp Es r E4 is either rLJ or all "H" (all r
If HJ, it means that none of the inputs from DOO to D31 requires priority), the logic of -G, , G; G, , G, becomes E! The pit pattern of ~E4 can be determined and therefore the logic of FO~Fl can be determined. For example, the 7 stones in PE-B (31) are PE-B (irrespective of the 3 koma (see Figure 4)).
At any time, rHJ becomes rHJ, which is the signal m (44
), the stone becomes rHJ, 100~■ becomes rL)IHHJ, FO becomes rLLJ, and Fl becomes rLLJ.

However, even if Er ~ E4 is rHHHHJ, rLLJ is output as FO and Fl, so the distinction between the two can be made using the output signal Q.
What is done according to the logic of G is as shown in FIG.

As shown in FIG. 3, in the circuit of the present invention, the enable signal is determined within the enable input signal determining circuit (35) without cascadingly propagating between each PE-B.
The delay time until the output logic of O to Q4 is determined can be shortened.

Figure 6 is a connection diagram showing a connection example to realize the logic expressed in the truth table in Figure 4, and the off diagram is a connection diagram showing a connection example to realize the logic expressed in the truth table in Figure 5. However, since these connection diagrams can be easily designed from the corresponding truth tables, their explanation will be omitted.

In the above embodiment, an example of configuring a priority encoder circuit with 32 human power and 5 outputs has been described, but it is clear that the present invention is not limited to the above numerical example.

As described above, according to the present invention, it is possible to eliminate the cascading propagation of signals in the priority encoder circuit, thereby reducing the delay time for determining the priority.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional circuit, Figure 2 is a truth table of the 8-bit input encoder shown in Figure 1, and Figure 3 is a diagram showing the truth table of the 8-bit input encoder in Figure 1.
FIG. 4 is a block diagram showing an embodiment of the present invention; FIG. 4 is a truth table of the 8-bit input encoder shown in FIG. 3;
Fig. 5 is a diagram showing a truth table of the enable input signal determination circuit shown in Fig. 3, and Fig. 6 is a connection diagram showing a connection example to realize the logic expressed in the truth table shown in Fig. 4, and an off-line diagram. 5 is a connection diagram showing a connection example for realizing the logic expressed in the truth table shown in FIG. 5. FIG. (31), (32), (33), (34)
...Priority encoder (sT()3PE-B) for each 8-bit input. (35)...Enable signal input determination circuit. Agent Shin Kuzuno −

Claims (1)

[Claims] It is a priority encoder for m-pit input, and when all input m bits are logic rLJ, the logic of the enable signal output is determined to be rLJ regardless of the logic of the enable signal input, and the logic of the enable signal input is " When "H", the logic of the enable signal output is determined regardless of the logic of the enable signal input.
means for connecting the priority input signals of mn pits to the signal input terminals of the n encoders in order of priority; an enable input signal determining circuit for determining the logic of the enable signal input of the encoder; and means for determining a pit pattern of an upper set of priority signal outputs according to a pit pattern of an enable signal input output from the enable input signal determining circuit. priority encoder circuit.