JPH0383124A - Serial input/output circuit - Google Patents

Abstract

PURPOSE:To reduce the number of shift registers to one to narrow the pattern area by switching registers to the function of an MSB first serial input/output circuit or the function of an LSB first serial input/output circuit in accordance with the signal line group set to the conductive state out of signal line groups. CONSTITUTION:Switching means 20 and 30 set one of first and second signal line groups 17 and 15 to the conductive state in accordance with a given control signal to switch (n+1)-bit registers S0 to Sn to the function of an LSB first serial input/output circuit or the function of an MSB first serial input/output circuit. Thus, the pattern area is narrowed at the time of integration in comparison with the case in which two shift registers are used to perform switching between LSB first and MSB first.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to serial input/output circuits, and particularly to LSB
(least significant bit) first and MSB (most significant bit)
This relates to a serial input/output circuit that can switch between first and second modes.

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of a shift register, which is an example of a conventional serial input/output circuit.

There are (n+1) registers S in shift register 1.
S S to'11'12''', SIn are connected in series.Registers 5S to'u'..., SIn are respectively 0th bit data bus DB0, 1st bit data bus DB1.・
..., connected to the n-th bit data bus DBn. In the initial state, each data bus DBO, DBI, .
..., DBn to each register "'Io, Sl□, ...
, sn, and when the input data DR is input to the n-th bit register Slo, each bit of data is shifted to the upper bit, and the n-th bit, which is the most significant bit, is Output data D from register Sln
T is output. Each time the input data DR is input, each bit of data is shifted to the upper bit, and output data DT is outputted from the n-th bit register S2.

In home appliances such as VTRs, for example, when transmitting a control signal from a timer to another system, whether to transmit it MSB first or LSB first differs depending on the manufacturer and is not standardized. Therefore, it is necessary to select a transmission method for each manufacturer of home appliances used. FIG. 3 is a block diagram showing a conventional serial input/output circuit that can support these two types of transmission methods. Shift registers la and lb are 8-bit shift registers having the same configuration as shift register 1 shown in FIG. The shift register 1a is for MSB first, and the shift register 1b is for LSB first. Each bit of shift registers a and lb is connected to a corresponding data bus DBO to DB7 and DB, respectively.
It is connected to Ob-DB7a b. 2a, 2a,'; lbl.

22b2 is a transmission gate, and these transmission gates are controlled by control signals B and B. LSB first and MSB first are switched by 0N10FF of transmission gates 2a to 2b2.

In the initial state, register S in shift register a
Oa to S7a are connected to data bus DBOa-DB7,
Desired data is input to registers Sob to S in shift register b from data buses DBOb to DB7b, respectively.

When control signal B is “H#”, transmission gates 2a and 2a2 are ONL, and transmission gate 2
b, 2b2 is turned off. In this case, shift register a is selected. In this state, input data D
When R is input, the data in register 9 s Oa of the least significant bit (0th bit) is transferred to register S of its upper bit.
1a, the data in each register is shifted to its respective upper bit register. Then, the data of the most significant bit (7th bit) is the transmission data D
Output as r. In other words, it functions as an MSB first serial input/output circuit.

On the other hand, when the control signal B is "L", the transmission gates 2a and 2a2 are set to 0FFL, and the transmission gates 2b and 2b2 are turned on.

In this case, shift register b is selected. In this state, when the input data DR is input, the data of each register is shifted to the register S6b of the lower bit, and so on. Shift into register. And the least significant bit (nth bit)
data is output as transmission data DT. In other words,
It functions as an LSB first serial input/output circuit.

[Problem to be solved by the invention]

The conventional serial input/output circuit is configured as described above, and uses two shift registers la and lb to switch between LSB first and MSB first, so when integrated, the pattern area becomes large. was there.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a serial input/output circuit that does not require a large pattern area when integrated.

[Means to solve the problem]

The serial input/output circuit according to the present invention has an input terminal to which data is input, an output terminal to which data is output, and a total (n) of bits from 0th bit to nth bit (n is a natural number).
+ 1) bit register, the input terminal and the input of the n-th bit register are connected, and the i-th bit (1lIIIO
11r ``'+ '-1) register output and (i
+1) A first signal line group that connects the input of the bit-th register and connects the output of the n-th bit register and the output terminal, and connects the input terminal and the input of the n-th register, A second circuit connects the output of the j-th register (jm1,..., 1) to the input of the (j-1)-th register, and connects the output of the n-th register to the output terminal. a signal line group; connected to the second signal line group,
Depending on the applied control signal, the first . and switching means for making one of the second signal line groups conductive.

[Effect]

The switching means in this invention is configured to switch between first and second switches according to the applied control signal. Either make one of the second signal line groups conductive and make the (n + 1) bit register function as an LSB first serial input/output circuit, or
Switch whether to function as an SB first serial input/output circuit.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a serial input/output circuit according to the present invention. This serial input/output circuit includes a shift register 10 and is configured to output data from a data output terminal 100 when data is input to a data input terminal 50. Shift register 0 has registers So to S with a total of (n+1) bits from 0th bit to nth bit, and data buses DBO to DBn of corresponding bits are connected to these registers 5o to Sn.

Register S-8 is connected to the first signal line group 17. R.

n 17 17 ... 178n and second signal line group s
Data input/output terminals 50 and 100 are connected as follows using o'st' 15.15 15 . . . 15 sn. That is, in connection by the first signal line group,
The data input terminal 50 is connected to the signal line 17. R.

The 0th bit register S via the transmission gate 20. is connected to the input of the 0th bit register S
The output is signal line 17 transmi o
transmission gate 20, and the output of the (n-1)th bit register 5(n-1) is connected to the signal line 17S(n-1)' transmission gate. 20 to the input of the n-th bit register S.
The output of signal line 17, transmi n
It is connected to the data output terminal 100 via the connection gate 20. On the other hand, in the connection using the second signal line group, the data input terminal 50 is connected to the input of the n-th bit R register S via the signal line 15 and the transmission gate 30, and the output of the n-th pit register S is Signal line 15, tiger n
Sn is connected to the input of the n-1)th bit register S via the transmission gate 30, and the output of the 1st bit register S is connected to the signal line 15.
SP is connected to the input of the 0th bit register So via the transmission gate 30, and the output of the 0th bit register S is connected to the data output terminal 100 via the signal line 15 transmission gate 30.

Transmission gate 20 receives control signal A.

0N10FFL according to A, first signal line group 1717
...178n is made conductive/non-conductive.

DR' 31' Transmission gate 30 receives control signal A.

0N10FFL according to A, second signal line group 15DR”
5 15Sr """Sn conductive/non-conductive SO.

state.

Next, the operation will be explained. In the initial state, desired data is input to registers So to Sn from data buses DBO to DBn. When the control signal A is "H", the transmission gate 30 is OFFFL and the transmission gate 20 is turned ON. Therefore, the first signal line group becomes conductive, and the second signal line group becomes non-conductive. In this case, when the input data DR is input from the data input terminal 50, the data in each register is shifted such that the data in the register So of the least significant bit (0th bit) is shifted to the register Sl of the upper bit. Shift to the upper bits of . Then, the data of the most significant bit (n-th bit) is sent to data output terminal 1 as transmission data D□.
It is output from 00. In other words, it functions as an MSB first serial input/output circuit.

On the other hand, when the control signal A is "L", the transmission gate 30 is turned on and the transmission gate 20 is turned off. Therefore, the first signal line group becomes non-conductive, and the second signal line group becomes conductive. In this case, when input data DR is input from the data input terminal 50,
Input data DR is sent to the most significant bit (
nth bit) is given to the register S. Then, the data in the register S is shifted to the lower bit ((n-1)th bit) of the register 5 (n-1) via the signal line 158n. In this way, each bit of data is shifted into its respective lower bit register. And register S of the least significant bit (0th bit).

The data is sent to the data output terminal 100 via the signal line 158o.
is output as transmission data Dr. In other words, LSB
It will function as a first serial input/output circuit.

In the above embodiment, one shift register 0 constitutes a serial input/output circuit that can function in either MSB first or LSB first. The pattern area is smaller than that of a serial input/output circuit.

In addition, in the above embodiment, the transmission gate 20
, 3(1) ONloFFl,: Although the conduction/non-conduction of each signal line is controlled by other switching means, the conduction/non-conduction of each signal line may be controlled by other switching means.

〔Effect of the invention〕

As described above, according to the present invention, the input terminal and the input of the 0th bit register are connected, and the 1st bit (i 0,
1. ..., n-1), and a first signal line group connecting the output of the (i+l)-th register to the input of the (i+l)-th register, and connecting the output of the n-th register to the output terminal;
Connect the input terminal and the input of the n-th register, and
Connect the output of the bit (j-n, n i, ..., 1) register to the input of the (j-1) bit register, and connect the output of the 0-bit register to the output terminal. a second signal line group, and a first signal line group. A switching means is connected to the second signal line group and makes either one of the first signal line group and the second signal line group conductive in accordance with a control signal applied thereto. Depending on which of the second signal line group becomes conductive, it is possible to switch between functioning as an MSB-first serial input/output circuit or as an LSB-first serial input/output circuit. There is no need to provide two shift registers. As a result, when integrated, the pattern area is reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the serial input/output circuit according to the present invention, FIG. 2 is a block diagram showing the configuration of a conventional shift register, and FIG. 3 is a block diagram showing the configuration of a conventional serial input/output circuit. It is a block diagram. In the figure, 20 and 30 are transmission gates, 17, 17 . ..., 17s, is the first DI?
80 signal line group, 15.15..., 158n is the second DRSO. A signal line group, 50 is a data input terminal, 100 is a data output terminal, s, s. ot'..., S are registers. Note that the same symbols in each figure indicate the same or equivalent parts.

Claims (1)

[Claims] (1) The input terminal where data is input, the output terminal where data is output, and the total from bit 0 to bit n (n is a natural number) (
n+1) bit register, the input terminal and the input of the 0th bit register are connected, and the output of the i-th bit (i=0, 1, ..., n-1) register and the (i+1) bit are connected. a first signal line group connecting the input of the n-th register and connecting the output of the n-th register with the output terminal, and connecting the input terminal and the input of the n-th register; jth bit (j=n
, n-1, ..., 1) and (j-1)
a second signal line group that connects the input of the bit-th register and the output of the zero-bit register and the output terminal; A serial input/output circuit comprising: switching means for making one of the first and second signal line groups conductive in accordance with a control signal.