KR930006746B1 - One by one comparise a/d converter capable of addresable latch - Google Patents

Abstract

The system utilizes latches in constituting the successive approximation A/D converter to reduce the number of the components such as photo-couplers, etc. the circuit comprises: addressable latches (3) to select the external analog input in a successive mode; a D/A converter (DA1) for generating a reference data with the successive comparison method; a comparator (CP1) for comparing the analog input data with the generated reference data.

Description

Sequentially Comparative A / D Converter Using Addressable Latch

1 is a block diagram of a conventional A / D converter.

2 is a graph of the difference comparison register function of the conventional A / D converter.

3 is a block diagram of the present invention A / D conversion apparatus.

* Explanation of symbols for main parts of the drawings

1: Central processing unit (CPU) 2: Photocoupler end

3: Addressable latch part 4: Input part

5: D / A converter AS ₁ : Analog switch

DA ₁ : D / A Converter CP ₁ : Comparator

LA ₁ to LA ₃ : addressable latch MUX ₁ , MUX ₂ : multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peripheral circuit of an analog (A) / digital (D) converter for converting an analog signal of voltage or current, which has been electrically converted from a physical quantity in nature, into a digital signal that can be used in a computer. The present invention relates to a sequential comparison type A / D converter using an addresser latch that can be applied to a sequential type A / D converter using an addressable latch.

With the development of computers, the signals used in most fields are digital signals, and the physical quantities of nature, such as temperature, pressure, humidity, flow rate, and mass, are analog signals, and in order to use them, it is necessary to convert analog signals into digital signals. .

Here, there are various A / D conversion methods for converting to digital signals, such as integral type, double integration type, and V / F (Voltage to Frequency) conversion. Among them, the most frequently used is the sequential comparison method in consideration of speed and precision, and the one-chip component is very expensive, making it difficult to apply to actual products.

Therefore, A / D conversion mechanism and most products are installed by combining D / A converter, sequential comparison type register and comparator, and they are used as modules of PLC (Programmable Logic Controller) or they are A / D conversion by themselves. In most cases, the central processing unit (CPU) is mounted on the A / D converter so that the peripheral device can send and receive the converted value.

In this way, FIG. 1 is a block diagram of a conventional A / D conversion apparatus. As shown in FIG. 1, the central processing unit 101 and the analog unit read out the value after the A / D conversion is completed through the port. A photo coupler stage 102 for passing a signal while insulating the digital portion, a D / A converter 103 for converting a digital value of the sequential comparison register 105 into an analog value with a reference voltage of the reference voltage generator 107, and A comparator 104 which compares the output of the D / A converter 103 with the value of the analog input to give the comparison comparison register 105 with large and small values according to the large and small signals of the comparator 104. It consists of a sequential comparison register 105 which makes "1" and "0" bit by bit from the most significant bit to the least significant bit in synchronization with the clock of the clock generator 106. The operation will be described below.

First, the D / A converter 103 is set to 8 bits, the analog input is set to 6V, and the reference voltage of the reference voltage generator 107 is set to 10V. Although not shown in the drawing, the start conversion signal of the sequential comparison register 105 is shown. When (SC) is applied from the central processing unit 101 through the photocoupler stage 102, the difference comparison register 105 sets the most significant bit to "1" and all remaining bits to "0", that is, "10,000,000". The data is output to the D / A converter 103 while being stored.

로, 되는 식에 의해 5V로 되고 입력이 6V이므로 비교기(104)의 출력은 고전위로 된다. 이 신호를 축차비교 레지스터(105)가 받아 다음 클럭이 들어오면 7번째 비트를 1로 세트하여 "11,000,000"로 되는 값을 출력한다.At this time, the output of the D / A converter 103 is, as shown in FIG.

Since the voltage becomes 5V and the input is 6V, the output of the comparator 104 becomes high potential. The sequential comparison register 105 receives this signal and sets the seventh bit to 1 when the next clock comes in, and outputs a value of "11,000,000."

This time, the output of the D / A converter 103 becomes 7.5V, so the output of the comparator 104 becomes low potential, and the successive comparison register 105 sets the seventh bit to "0" and the sixth bit to "." 1 "is set. Thus, if the output of the comparator 104 has a high potential, the next bit is set to "1", and if the potential is low, the comparison comparison register 105 synchronizes the clock with the bit "0" and the next bit "1". By setting the LSB (Least Significant Bit), the D / A output is getting closer to the analog input value and the EC (End of Conversion) signal is sent after the ninth (n + 1) clock.

When the central processing unit 101 reading this signal opens the port PORT and reads it through the n-bit (here 8-bit) photocoupler 102, the A / D conversion is completed.

However, in the conventional A / D converter as described above, in the development of a device which is theoretically free from defects but has to be gradually minimized and the cost lowered, for example, a 12-bit A / D converter is a control signal for controlling by a CPU. In order to receive a signal for reading the information and the number of (12 + the number of control signals + the number of information lines) is required as the photocoupler has a problem that the area of the substrate is also increased.

In particular, there are usually 8 or more analog inputs, which are usually one or more. In order to send signals from the CPU to multiplexers, analog switches, samples and holders, etc., more photocouplers must be used and more CPU ports must be prepared. A problem occurred. In addition, as the intensity increases and the number of bits increases to 16 bits, 18 bits or more in the future, more and more serious problems have to be considered.

It is an object of the present invention to prevent the increase in the number of photocouplers and the number of CPU ports accordingly, and to reduce the number of components and the size of the substrate by using an addressable latch without using a difference comparison register. It is the invention of a sequential comparison type A / D conversion device using an addressable latch that provides a D conversion method.

In order to accomplish the above object, the present invention provides a central processing unit to control a multiplexer through an addressable latch to output an analog data signal applied to the multiplexer through an analog switch, and to control a reference data by controlling a D / A converter. After the signal is generated, the analog data signal is compared with the reference data signal, and then transmitted to the central processing unit.

3 is a configuration diagram of the A / D conversion device of the present invention, as shown therein, a photo coupler stage 2 in which signal lines through an input / output port of the central processing unit 1 are insulated from an analog unit, and the photo An addressable latch unit including an addressable latch LA ₁ (LA ₂ ) LA ₃ in which an output signal is controlled by a control signal of the central processing unit 1 input through the coupler stage ₂ ( 3) and an input unit 4 for selecting and outputting any one of analog data signals that are externally controlled by the addressable latch LA ₁ output signal of the addressable latch unit 3, and After comparing the reference data signal converted from the addressable latch LA ₂ (LA ₃ ) output signal of the addressable latch unit 3 to an analog signal and the analog data signal input from the input unit 4, the output signal is centered. It consists of the D / A conversion part 5 applied to the processing apparatus 1, Referring to Figure 3 will be described the effect.

First, the operation of the addressable latches LA ₁ , LA ₂ and LA ₃ will be described.

와

는 상기 어드레서블 래치(LA₁)(LA₂)(LA₃)의 모드를 정할 수 있는 두개의 콘트롤 신호이고 A₀~A₂는 어드레서블 래치(LA₁)(LA₂)(LA₃)의 어드레스를 결정해주는 셀렉트신호이다. 본 발명에서는 어드레서블 래치 모드와 클리어 모드를 사용하므로 이에 대해 설명한다.Q ₀ ~ Q ₇ is output and D is input data signal

Wow

Are two control signals that can determine the mode of the addressable latch (LA ₁ ) (LA ₂ ) (LA ₃ ) and A ₀ ~ A ₂ is the addressable latch (LA ₁ ) (LA ₂ ) (LA ₃ ) ) Is a select signal that determines the address of. In the present invention, the addressable latch mode and the clear mode are used.

와

에 (H,L)의 신호를 인가하면 클리어 모드의 경우로서 이때 모든 출력 Q₀~Q₇이 "L"로 클리어된다.

와

에 (L,H)의 신호를 인가하면 어드레서블 래치 모드의 경우로서 A₀~A₂의 셀렉트신호에 따라 선택된 출력만이 D에 들어오는 입력값을 갖게되고 나머지 출력은 이전상태를 유지한다.

Wow

If the signal of (H, L) is applied to the clear mode, all outputs Q ₀ to Q ₇ are cleared to "L".

Wow

When the signal of (L, H) is applied to, in the addressable latch mode, only the output selected according to the select signal of A ₀ ~ A _{2 has} the input value to D and the rest of the outputs remain the previous state.

,

)=(L,H)로 하면 그 때(Q₀,Q₁,Q₂,Q₃,Q₄,Q₅,Q₆,Q₇)은 (L,L,H,L,L,L,L,L)로서 3번째 신호가 D값인 H로 바뀌게 되고 나머지는 모두 이전값을 유지하게 된다. 이렇게 하면 Q₀~Q₇의 출력값을 마음대로 제어해 줄 수 있게 되므로 입력단 신호의 선택이나 축차 비교 레지스터 대용으로 사용이 가능한 것이다.For example, the state of Q ₀ ~ Q ₇ is (Q ₀ , Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₆ , Q ₇ ) = (L, L, L, L, L, L, L, L), (A ₀ , A ₁ , A ₂ ) is set to (L, H, L), and a signal of H is applied to D (

,

) = (L, H) then (Q ₀ , Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₆ , Q ₇ ) is (L, L, H, L, L, L, L, L), the third signal is changed to H, which is the D value, and all others remain at the previous values. In this way, the output value of Q ₀ ~ Q ₇ can be freely controlled, so that it can be used to select the input signal or to substitute the sequential comparison register.

,

)를, (H,L)로 인가하면 이 어드레서블 래치(LA₁~LA₃)의 모든 출력이 "L"로 클리어된다. 이후 어드레서블 래치(LA₁)에 콘트롤 신호(

,

)를 (L,H)상태로 인가하면 어드레서블 래치 모드가 된다.The central processing unit 1 transmits a control signal to the addressable latches LA ₁ to LA ₃ operating in this manner.

,

) Is applied to (H, L) to clear all outputs of the addressable latches LA ₁ to LA ₃ to " L ". Thereafter, the control latch (LA ₁ )

,

) Is applied to the (L, H) state to enter the addressable latch mode.

,

)를 (H,L)로 하여 어드레서블 래치(LA₁)의, 모든 출력(Q₀~Q₇)을 L로 한다. 멀티플렉서(MUX₁)의 3번째 입력을 선택하려면 멀티플렉서(MUX₁)의 A₀~A₇에 (L,H,L)의 신호를 인가해야 한다. A₀에 연결되어있는 어드레서블 래치(LA₁)의 출력(Q₆), A₂에 연결되어 있는 출력(Q₄)는 이미 L인 상태를 유지하고 있으므로 그대로 두고 Al에 H의 신호를 인가하려면 출력(Q₅)을 H로 만들어 주어야 한다. 즉 어드레서블 래치(LA₁)의 (A₀,A₁,A₂)에 (H,L,H)를 인가하고 입력데이타 신호(D)를 H로 하고 콘트롤 신호(

,

)를 (L,H)로 해주면 된다.The addressable latch LA ₁ controls the multiplexer MUX ₁ and MUX ₂ and the analog switch AS ₁ of the input unit 4 as follows. The analog data signal externally input to the multiplexer (MUX ₁ ) is set to (M ₁ to M ₈ ), the multiplexer (MUX ₂ ) input is set to (M ₉ to M ₁₆ ), and the third input (M ₃ ) is selected as an example. An example is as follows. First, addressable latch LA ₁ is a control signal (

,

) And (H, L) to set all outputs Q ₀ to Q ₇ of the addressable latch LA ₁ to L. To select the third input of a multiplexer (MUX ₁₎ should be applied to the signals of the A ₀ ~ A ₇ of a multiplexer _{(MUX 1) (L, H} , L). The output (Q ₆ ) of the addressable latch (LA ₁ ) connected to A ₀ and the output (Q ₄ ) connected to A ₂ are already in the state of L, so leave H and apply the signal of H to Al. To do this we need to make the output (Q ₅ ) H. That is, (H, L, H) is applied to (A ₀ , A ₁ , A ₂ ) of the addressable latch LA ₁ , the input data signal D is H, and the control signal (

,

) To (L, H).

,

)는 계속(L,H)로 해주면 된다.Now air in the same manner as in haejueoya a multiplexer (MUX ₁₎ output (Q ₃₎ of the addressable latch (LA ₁₎ are connected to a multiplexer (MUX ₁₎ (EN) in order to enable the by H addressable Apply (H, H, L) to (A ₀ , A ₁ , A ₂ ) of the latch LA ₁ , and apply the H and control signals to the input data signal D.

,

) To continue (L, H).

,

)는 그대로 유지하면 비로서 아날로그 스위치(AS₁)의 출력으로 멀티플렉서(MUX₁)의 3번째 입력신호(M₃)가 선택되어지게 된다.Finally, for the analog switches addressable latch (LA ₁₎ the output to do this, there is need to be created for (Q ₁₎ to H addressable latch (LA ₁₎ in order to turn on the switch (S ₁₎ of the (AS ₁₎ ( A _o , A ₁ , A ₂ ) to (L, H, L), D to H, (

,

If it is maintained as it is, the third input signal M ₃ of the multiplexer MUX ₁ is selected as the output of the analog switch AS ₁ .

,

)를 (H,H)로 하여 메모리 모드로 하여 상기 선택된 입력이 계속 유지되도록 하고 어드레서블 래치(LA₂)의 제어신호(

,

)를, (L,H)로 한 후 출력(Q₃)을 "1"로 세트할 수 있도록 입력 데이타 신호(D)를 H로 하고, 셀렉트신호(A₀,A₁,A₂)를 (H,H,L)로 하여 인가한다.In this way, when any one of the multiplexer (MUX ₁ ) (MUX ₂ ) external input analog data signals (M ₁ to M ₈ ) (M ₉ to M ₁₆ ) is selected, the control signal of the addressable latch (LA ₁ ) is subsequently selected. (

,

) Is set to (H, H) and the memory mode is maintained so that the selected input is maintained and the control signal of the addressable latch LA ₂

,

), And set the input data signal D to H so that the output (Q ₃ ) can be set to "1", and select signals (A ₀ , A ₁ , A ₂ ) H, H, L).

Thereafter, the output of the D / A converter DA ₁ , which digitally / analog-converts the output of the addressable latches LA ₂ and LA ₃ , which serve as a sequential comparison register, with the analog data signal output from the analog switch AS ₁ . After comparing through the comparator (CP ₁ ) and outputs the H or L signal to the central processing unit (1).

When the comparator (CP) output signal is H, the central processing unit 1 leaves the previous bit (for example, the output Q ₃ of the addressable latch LA ₂ , which is the 12th one here), and leaves the comparator CP. ₁ ) When the output signal is L, the input data signal D is set to 1 to set the previous bit (for example, the output Q ₂ of the addressable latch LA ₂ which is here 12th) to 1 The input latch signal LA ₂ output Q ₂ is selected as the select signals A ₀ , A ₁ , and A ₂ so that an input data signal D value is output.

,

)를, (H,L)로 하여 모든 출력을 클리어하고, 어드레서블 래치(LA₁)를 이용하여 다음 입력을 선택한다.In this way, after setting to the least significant bit, the control signal of the addressable latches LA ₁ and LA ₂ is again

,

) And (H, L) to clear all outputs and select the next input using addressable latch (LA ₁ ).

In this case, conventionally, when the comparison comparison register sends the end signal (EC) to the CPU, the CPU opens the ports and reads the 12-bit signals all at once. However, in the present invention, since the CPU directly switches the role of the succession comparison register, it is 12 bits. There is no need to read the signal. In this way, 16 inputs are selected in sequence to repeat the A / D conversion.

Here, the addressable latches LA ₁ to LA ₃ can be replaced with other components that are CMOS, and the logic circuit can be changed into various types. In addition, the input unit 4 may not be changed according to a specific circuit configuration, and the circuit configuration of the D / A converter 5 may also vary slightly depending on the designer.

As described in detail above, the present invention can reduce the number of control signals at the same time as transferring the inverse of the difference comparison register to the CPU by using an address comparison register and using an addressable latch that can be purchased as a low cost TTL or CMOS. Since the area of the substrate can be reduced and the number of photocouplers is reduced, the cost of the product can be significantly lowered.

Claims (1)

Selective control of the addressable latch unit 3 by transmission through the photocoupler stage 2 to the output of the central processing unit 1, Selective control of the input unit 4 to sequentially select an external input analog data signal, The reference data is output by controlling the D / A converter DA ₁ sequentially and then comparing the analog data signal through the comparator CP ₁ to transmit the data to the CPU 1. Sequential comparison type A / D converter using dressable latch.

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