KR940007952B1 - Test point monitoring circuit of asic internal - Google Patents

Abstract

The circuit connects a multiplexer to a multitude of flip-flops, selectively specifies a test point of the multiplexer, and limits an input channel of the multiplexer. The circuit includes a switching control unit (10) which outputs a switching control signals according to system clock signal (SCLK), a switching selector (20) which selectively outputs an outputs signals (Pi-Pi+(n-1)) of test points, a multiplexer (30) which selectively outputs an actual ouptut signal (Pi) or switching selector (20) output signal. The switching control unit (10) includes flip-flops (FF50-FF5n). The switching selector (20) includes buffers (B1-Bn).

Description

Internal test point monitoring circuit

1 is a conventional ASIC test point monitoring circuit.

2 is a test point monitoring circuit diagram of AIZ of the present invention.

3 is an input format of serial data input to the flip-flop of FIG.

* Explanation of symbols for main parts of the drawings

FF ₅₀ to FF _5n : Flip-flop B ₀ to B ₀ : Buffer

30: multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the design of an application specific integrated circuit. In particular, when testing the inside of an ASIC using a multiplexer, the number of bits of a point selection signal specifying a test point is minimized. This is a test point monitoring circuit inside AIZ that can monitor a desired test point with a multiplexer having a selection control terminal of.

In general, when testing the inside of AIZIC, each terminal signal of AIZIC is input to the multiplexer, and the output signal of the terminal is monitored by selecting a specific terminal by sending a selection control signal from the multiplexer.

Meanwhile, a conventional test point monitoring circuit generally used in this regard uses a multiplexer 1 having n select signal terminals to monitor 2 ⁿ test points, as shown in FIG. It is configured to withdraw the monitoring output therefrom, and the operation and problems will be described with respect to this conventional circuit.

First, the multiplexer (1) is to send a selection signal input terminal (1 ... n) outputs only the selected signal (P1 ~ P ₂ ⁿ⁾ of a specific type according to the value of the selection signal applied to the input signal is 2 ⁿ If it is composed of two pieces, n select signals are required to designate each input signal.

Therefore, when the number of input signals increases, the number of input selection signals increases in proportion to the number of input signals, which acts as an increase factor of cost.

Accordingly, the present invention has been invented to solve the problem that the conventional AIZ monitoring circuit employs a multiplexer having many input terminals to designate a specific test point of AIZ and draw out the force signal. In order to monitor the test points inside the AIZ, it is possible to selectively monitor the test points inside the AIZ by controlling the signal output terminal of the test points by serially applied serial data. The explanation is as follows.

2 is a test point monitoring circuit diagram of AIZ according to the present invention. As shown therein, flip-flops FF ₅₉ to FF _5n are connected in series, and the output of each flip-flop FF ₅₀ to FF _{5n-1 is} shown. The terminal (Q) signal is input to the input terminal (D) of the next flip-flops (FF ₅₁ to FF _5n ), respectively, and the reset signal to the reset terminal (R) of each flip-flop (FF ₅₀ to FF _5n ). is common to (RESET), and the system clock signal (SCLK), the buffer (B ₀₎ of the flip-flop, and common is to be connected to the clock terminal, the flip-flop (FF ₅₀₎ of (FF ₅₀ ~ FF _5n) via The switching control unit 10 is configured by connecting the serial data SD to the input terminal D, and inverting the output terminal of the flip-flop FF ₅₀ . ) Is connected to the channel select terminal CH of the multiplexer 30, and the inverted output terminal of the flip-flops FF ₅₁ to FF _5n ) Are connected to the control terminals of the buffers B ₁ to B _n , respectively, so that the output signals P _i to P _{i + (n-1)} of the test points are selectively input to the multiplexer 30. The selector 20 is configured, and the multiplexer 30 includes an inverted output terminal of the flip-flop FF ₅₀ . ) And selecting an output constituting the output select signal or real output signal (P _i) of said switching selecting portion 20 according to the signal.

The operation and the effect of the circuit of the present invention configured as described above will be described in detail as follows.

First, in the present invention, the serial data (SD) is transferred to the sub-connected flip-flop (FF ₅₀ ~ FF _5n ) to output a specific bit of data from the specific flip-flop (FF ₅₀ ~ FF _5n ) of the desired test point The output signals P _i to P _{i + (n-1)} are output to the multiplexer 30. This process will be described in detail based on the serial data format of FIG.

First, in the serial data SD as shown in FIG. 3A, flip-flops FF ₅₁ to FF _n corresponding to each bit are set, and the inverted output terminal ( ) (And enables the B ₁ ~ B _n), it yiettara the buffers (B ₁ ~ B _n), the output signal (P _i ~ P _{i + (n-1} of the test point which is input _to) the buffer over that enable) The multiplexer 30 is input to the multiplexer 30 through the buffers B ₁ to B _n . When monitoring the P _{i + 1} th test point, as shown in FIG. 3B, the serial clock SD is sequentially input to the input terminal D of the flip-flop FF ₅₀ . ) Is transferred to the flip-flops FF ₅₁ to FF _5n of the next stage in synchronization with each other, and a high potential signal is output only to the output terminals Q of the flip-flops FF ₅₀ and FF ₅₂ , and the remaining flip-flops ( A low potential signal is output to the output terminal Q of FF ₅₁ and FF ₅₃ to FF _5n ), that is, the inverted output terminals of flip-flops FF ₅₀ and FF ₅₂ (FF ₅₂ ). Since only the low potential signal is outputted, only the buffer B ₂ is enabled so that the output signal _{Pi + 1} of the test point is selectively output from the multiplexer 30 through the buffer B ₂ .

Similarly, in order to monitor the P _{i + (n−)} th test point, serial data SD as shown in FIG. 3C is sequentially applied to the input terminal D of the flip-flop FF ₅₀ according to the system clock SCLK. According to this, the inverted output terminal of the flip-flops (FF ₅₀ ) and (FF _{5 n-1} ) among the flip-flops (FF ₅₀ to FF _{5 n} ) Since only the low potential signal is outputted, it is selectively output from the multiplexer 30 through the buffer B _n-1 .

However, in outputting a signal of a specific test point to the multiplexer 30 by serial data having the above structure, when first loading data into each flip-flop FF ₅₀ to FF _5n , all flip-flops ( Serial data SD should be applied to output low potential signal to output terminal Q of FF ₅₀ ~ FF _5n ).

This is because data previously stored in each flip-flop FF ₅₀ to FF _5n may enable two or more buffers simultaneously to apply different signals to the same input terminal of the multiplexer 30.

Therefore, since the number of input pins of the multiplexer 30 for the test needs to be two regardless of the number of test points, it not only creates an effect of reducing the cost at the time of product creation but also doubles the test capability in the design of AIZ. Occurs.

As described above, the present invention can selectively designate a test point applied to the multiplexer by cascading a plurality of flip-flops to the multiplexer and setting a specific flip-flop by serial data. Regardless of the number, the input channel of the multiplexer can be limited to a few channels.

Claims (3)

Switching controller 10 for receiving the serial data (SD) for designating a test point in the AIZ and sequentially moving by the system clock signal (SCLK) to output a switching control signal, and the switching control unit 10 of A switching selector 20 for selectively outputting the output signals P _i to P _{i + (n-1)} of the test point according to the remaining switching control signals except the most significant bit, and the most significant bit switching control of the switching controller 10. And a multiplexer (30) for selectively outputting the output signal of the switching selector (20) or the actual output signal (P _i ) according to the signal. The switching control unit 10 is configured of flip-flops (FF ₅₀ ~ FF _5n ) to sequentially output the input serial data (SD) to the next stage in synchronization with the system clock signal (SCLK), switching control signal of the flip-flop (FF _50), the inverted output signal and an inverted output signal and the switching selecting portion 20 of the is applied to a channel selection signal of the multiplexer 30, the flip-flop (FF ₅₀ ~ FF _5n) of The test point monitoring circuit inside the AIZ, characterized in that configured to be applied to. The switching selector 20 is enabled according to the switching control signal of the remaining bits except for the most significant bit of the switching control unit 10, so that the output signals P _i to P _{i + ( n-1)} ) A test point monitoring circuit in the interior of the AICC, characterized in that consisting of a buffer (B ₁ ~ B _n ) for outputting.