KR930011431A - Test point monitoring circuit inside the ASIC - Google Patents

Test point monitoring circuit inside the ASIC Download PDF

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Publication number
KR930011431A
KR930011431A KR1019910020622A KR910020622A KR930011431A KR 930011431 A KR930011431 A KR 930011431A KR 1019910020622 A KR1019910020622 A KR 1019910020622A KR 910020622 A KR910020622 A KR 910020622A KR 930011431 A KR930011431 A KR 930011431A
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KR
South Korea
Prior art keywords
test point
monitoring circuit
asic
serial data
multiplexer
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KR1019910020622A
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Korean (ko)
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KR940007952B1 (en
Inventor
임문환
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이헌조
주식회사 금성사
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Priority to KR1019910020622A priority Critical patent/KR940007952B1/en
Publication of KR930011431A publication Critical patent/KR930011431A/en
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Publication of KR940007952B1 publication Critical patent/KR940007952B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

본 발명은 ASIC의 설계에 관한 것으로, 일반적으로 사용되고 있는 종래의 테스트 포인트 모니터링 회로는 2n개의 테스트 포인트를 모니터링하기 위해 n개의 선택신호단자를 갖는 멀티플랙서를 사용하고 그로부터 모니터링 출력을 인출하도록 구성되어 있으며 각 입력신호를 지정하기 위해서는 n개의 선택신호가 필요하며 따라서 입력신호가 많아질 경우에는 그에 비례하여 입력선택신호의 수도 같이 증가하게 된다.TECHNICAL FIELD The present invention relates to the design of an ASIC, and a conventional test point monitoring circuit, which is generally used, is configured to use a multiplexer having n select signal terminals and to draw a monitoring output therefrom to monitor 2 n test points. In order to designate each input signal, n number of selection signals are required. Therefore, when the number of input signals increases, the number of input selection signals increases proportionally.

이에 따라 본 발명은 상기와 같은 종래 ASIC 모니터링 회로의 결함을 감안하여 다수의 멀티플렉서를 캐스코드시키고 직렬 데이타에 의해 특정 플립플롭을 세트시킴으로써 멀티플렉서에 인가되는 테스트 포인트를 지정할 수 있고, 테스트 포인트의 입력 신호의 수에 관계없이 멀티플랙서의 입력신호 수를 소수를 제한할 수 있도록 창안된 것이다.Accordingly, the present invention can designate a test point applied to the multiplexer by cascading a plurality of multiplexers and setting a specific flip-flop by serial data in view of the deficiencies of the conventional ASIC monitoring circuit as described above, and the input signal of the test point. It is designed to limit the number of input signals of the multiplexer regardless of the number.

Description

ASIC 내부의 테스트 포인트 모니터링 회로Test point monitoring circuit inside the ASIC

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 ASIC 테스트 포인트 모니터링 회로도.2 is an ASIC test point monitoring circuit diagram of the present invention.

제3도는 제2도의 플립플롭에 입력되는 직렬 데이타의 입력포맷.3 is an input format of serial data input to the flip-flop of FIG.

Claims (4)

테스트 포인트를 지정하는 데이타를 직렬로 구성한 직렬 데이타(SD)와, 상기 직렬 데이타(SD)를 입력받아 출력을 제어하는 제어 수단(10)과, 상기 제어수단(10)의 출력에 의하여 스위치 동작을 하는 스위칭 소자(20)와, 상기 스위칭소자(20)에 의해 해당 테스트 포인트를 모니터링하는 멀티플렉서(30)로 구성된 ASIC 내부의 테스트 포인트 모니터링 회로.The switch operation is performed by serial data SD having serially configured data specifying a test point, a control means 10 for receiving the serial data SD and controlling an output, and an output of the control means 10. The test point monitoring circuit in the ASIC composed of a switching device 20 and a multiplexer (30) for monitoring the test point by the switching device (20). 제1항에 있어서, 상기 제어 수단(10)은 ASIC 내부 테스트 포인트의 데이타를 입출력하는 스위칭 소자(20)에 직렬 데이타(SD)를 순차적으로 인가하고, 상기 직렬데이타(SD)가 스위칭 소자(20)에 모두 인가되는 시점에서 하나의 스위칭 소자(20)만이 턴온되게 동작시킴을 특징으로 하는 ASIC 내부의 테스트 포인트 모니터링 회로.The method of claim 1, wherein the control means 10 sequentially applies the serial data (SD) to the switching element 20 for inputting and outputting data of the internal test point of the ASIC, the serial data (SD) is the switching element 20 The test point monitoring circuit inside the ASIC, characterized in that only one switching element (20) is turned on at the time when all are applied. 제1항 또는 제2항에 있어서, 상기 제어수단(10)은 직렬 데이타(SD)를 입력받아 후단의 플립플롭(FF51∼FFn)으로 출력하고, 멀티플랙서(30)의 채널 선택단자(CH)로 출력하는 제1플립플롭(FF50)과, 테스트 포인트의 수에 대응하여 후단의 플립플롭으로 직렬데이타(SD)를 출력하고 스위칭소자를 제어하는 플립플롭(FF51)으로 구성됨을 특징으로 하는 ASIC 내부의 테스트 포인트 모니터링 회로.The channel select terminal (CH) of the multiplexer (30) according to claim 1 or 2, wherein the control means (10) receives the serial data (SD) and outputs the flip-flops (FF51 to FFn) at the rear stage. ASFL characterized in that the first flip-flop (FF50) to output a) and the flip-flop (FF51) for outputting the serial data (SD) to the rear flip-flop corresponding to the number of test points and to control the switching element Internal test point monitoring circuit. 제1항 또는 제2항에 있어서, 상기 스위칭소자(20)는 제어수단(10)의 출력에 의해 스위치되어 해당 테스트 포인트를 모니터링하기 위한 버퍼(B2∼Bn)로 구성됨을 특징으로 하는 ASIC 내부의 테스트 포인트 모니터링 회로.The internal switching circuit according to claim 1 or 2, wherein the switching element (20) is composed of buffers (B2 to Bn) for switching by the output of the control means (10) to monitor the corresponding test points. Test Point Monitoring Circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910020622A 1991-11-19 1991-11-19 Test point monitoring circuit of asic internal KR940007952B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910020622A KR940007952B1 (en) 1991-11-19 1991-11-19 Test point monitoring circuit of asic internal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910020622A KR940007952B1 (en) 1991-11-19 1991-11-19 Test point monitoring circuit of asic internal

Publications (2)

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KR930011431A true KR930011431A (en) 1993-06-24
KR940007952B1 KR940007952B1 (en) 1994-08-29

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