JPS5913369A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To simplify the construction of the titled element without reducing the pitch of horizontal registers even when formation of the device to have high resolving power and in a small size is contrived by a method wherein the horizontal registers of two pieces are prepared, the registers are made to take partial charge of read action in the horizontal direction respectively, and electrodes of two phases to make both the horizontal registers to perform CCD action are made to act together. CONSTITUTION:The respective stages of the first horizontal register 3 are connected to the transference terminal of vertical registers 1A, 1B. A read gate 4 is provided at the connection part thereof, and transmission to the latter stages from the vertical registers 1A, 1B is controlled according to electric potential applied to the read gate thereof. The second horizontal register 5 is formed as to be positioned in parallel with the first horizontal register 3. The first and the second horizontal registers 3, 5 thereof are controlled by two phase clocks, for example, and moreover are made to perform CCD action according to common storage electrodes 6A, 6B and transfer electrodes 7A, 7B. Moreover electric charges of the vertical registers 1A on one side are transmitted to the storage parts of the second horizontal register 5 through the storage parts of the first horizontal register 3 according to channel regions 10.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a solid-state image sensing device consisting of a COD (charge-coupled device), and in particular, to a 5KL device that can increase the pitch of horizontal picture elements without increasing the pitch of horizontal registers. , L, etc., so that there is no need for a complicated configuration.

BACKGROUND ART AND PROBLEMS When a solid-state image pickup device made of COD, for example, a frame transformer type device, is made to have a high resolution, short channel effects and problems in electrode processing accuracy occur in the horizontal register. A similar problem occurs when the chip size is made smaller in response to optical systems becoming progressively smaller from 1 inch to % inch to 1/2 inch.

In other words, in a frame transfer type solid-state image sensor, a signal charge corresponding to an optical image is formed in an image section, this signal charge is transferred vertically to a storage section, and then the charge at the end of transfer in the storage section is transferred horizontally. Read out sequentially in the register. In this case, the horizontal register requires bits corresponding to the number of horizontal picture elements, and therefore, in order to achieve high resolution, the number of bits in the horizontal register must be increased. In this case, the pitch of the horizontal register becomes large, causing short channel effects and problems with electrode processing accuracy. A similar problem exists when downsizing a solid-state image sensor. This requires no explanation.

By the way, the present applicant has provided a solid-state image sensor comprising two horizontal registers (Japanese Patent Application No. 56-65657).
issue). In this solid-state image sensor, the signal charges transferred to every other column of the vertical registers forming the storage section are read out by one horizontal register, and the signal charges transferred to the remaining every other column are read out in many directions. It is read using the horizontal register. Therefore, the number of bits in one horizontal register is small, and the above-mentioned short channel effect and problems in electrode processing accuracy can be avoided.

However, in this solid-state image sensor, one horizontal register is placed at the transfer end of the vertical register, and the other horizontal register is placed slightly away from this one horizontal register in the transfer direction, and the other horizontal register is placed in parallel with this one horizontal register. Place registers. Due to this arrangement, the false parallel signal charges transferred from the vertical registers of the storage section are
It is necessary to jump from one horizontal register to the other horizontal register. Patent application 1986-65657
In the specific example of the solid-state image sensor in the issue, COD operation is performed by simultaneously driving both horizontal registers using the same storage electrode and transfer electrode. A bypass channel is formed to the storage section of the register, thereby allowing the signal charge of the vertical register to be transferred to the storage section of the other horizontal register.

However, in such a transfer, since the storage section of one register and the storage section of the other register are under the same electrode, the potentials of the channels of both storage sections are at the same level as they are, and as a result, a predetermined difference in the transfer direction Special measures are required to create a potential difference.

Purpose of the Invention The present invention has been made in consideration of the above circumstances, and it is possible to achieve high resolution and miniaturization of a solid-state image sensor without increasing the pitch of the horizontal register, and with a simple configuration. The purpose is to provide a solid-state image sensor.

Summary of the invention The present invention aims to achieve such an objective.

Two horizontal registers are prepared to share the horizontal read operation. When signal charges are transferred from the transfer end of the vertical register to the horizontal register spaced apart, the two phase electrodes that operate both horizontal registers in a CCU operation are made to work together.

According to the present invention, the short channel effect can be avoided, and there is no problem with electrode processing accuracy, and power consumption can be further suppressed. Furthermore, there is no need to adopt a particularly complicated configuration for transferring signal charges to the horizontal register spaced apart from the transfer end of the vertical register, and an extremely simple configuration can be achieved.

EXAMPLE Hereinafter, an example of the present invention will be explained with reference to the drawings.

1 and 2 show a part of the solid-state image sensing device of this example. direction). These vertical registers (LA) (IB) are separated from each other by channel stopper regions (2). These channel stopper areas (2) are marked with dots.

The same applies to other channel stopper regions. Signal charges are transferred to these vertical registers (IA) (IB) from an image portion (not shown), and then transferred sequentially in the direction of the arrow.

Each stage of the first horizontal register (3) is coupled to the transfer end of the vertical register (IA) (IB). A readout gate (4) is provided at this coupling position, and a vertical register (I
A) Transfer from (IB) to the subsequent stage is now controlled. A second horizontal register (5) is formed at 5 parallel to the first horizontal register (3).

These first and second horizontal registers (3) (5) are controlled by, for example, a two-phase clock, and have common storage electrodes (6A) (6B) and transfer electrodes (7A).
) (7B) (shown by broken lines in FIG. 1) allows the CCD to operate.

A T/S gate (transfer stop gate) (81) is provided between these horizontal registers (3) and (5).

A channel stopper region (9) and a partial channel region O1 are formed under this T/S gate (8).

The first horizontal register (3) below the storage electrode (6A)
A channel region QO) is formed extending from the storage section of ) to the storage section of the second horizontal register (5) below the other storage electrode (6B). Vertical register (
Focusing on IA) (IB), a channel region α1 is formed corresponding to one vertical register (IA). That is, channel regions α1 are formed every other vertical register (IA) (IB). According to this channel area αl, one vertical register (IA
) is transferred to the storage section of the second horizontal register (5) via the storage section of the first horizontal register (3) 12. The charge transferred through the other vertical register (IB) is blocked by the channel stopper region (9) and remains in the first horizontal register (3). You will understand this later.

In addition, in this example, electrodes (6A) (6B) (7A) (7
The shape of B) is made to be oblique in the region of the T/S gate (8).

That is, the electrode (6) in the area of the first horizontal register (3)
A) (6B) (7A) The spatial phase of (7B) is shifted with respect to the phase in the area of the second horizontal register (5). This makes it easy to bypass from the storage section under one storage electrode (6A) to the storage section of the other storage electrode (6B) just by slightly tilting the channel region (9). I can do it. Electrode (6A) (6B) (7A)
If the shape of (7B) is made straight, the channel region α [has to be extremely bent in the region of the T/S gate (8), while on the other hand, if the channel region (11) is made straight, the electrodes (6A) (6B) ( 7A) Same shape as (7B) K
An extreme bend must be made in the area of the T/S gate (8). Doing this poses a problem in terms of electrode accuracy and is also inconvenient in terms of charge transfer efficiency.

In addition, in one example, as is well known, the storage electrode (6A) and the transfer electrode (7A) are connected in common.
(IIA), and a clock φ1 is supplied to this via the clock terminal (12A). On the other hand,
Other storage electrodes (6B) and transfer electrodes (7
B) is also commonly connected to other nodes (-(IIB)
K connection and connect another clock signal φ2 to another clock terminal (
12B). This clock signal φ1. There is no need to explain that the horizontal register (3) (51) or CCD can be operated by φ2. In Fig. 2, α is the semiconductor substrate, α is the gate insulating film, and α9 is the insulating film. be.

Next, the operation of this embodiment will be explained with reference to FIGS. 3 and 4. In the following explanation, only the operations of the horizontal registers (3) and (5) will be mentioned.

A description of the equal pressure charge transfer from the image section to the storage section, which is not shown, will be omitted.

First, to read the final stage charges of the vertical registers (IA) (IB), turn on the read gate (4).

At time h (Figure 3), the clock terminal (12A) (t2B
) and T/S gate (8) are turned on (high level).

Then, as shown in Figure 4AK, one of the vertical registers (
The signal charge from the final stage of IA) is transferred to the horizontal register (
3) Transferred to the storage section in (5). In this case, the potential of the storage section (5) of the second horizontal register is set to be deeper than the potential of the storage section of the first horizontal register (3). For example, storage electrode (6A
) The on-potential of the storage electrode (6B) is made higher than the on-potential of the storage electrode (6B). Alternatively, the impurity concentration or the gate insulating film αa (
Adjust the thickness of Fig. 2). By doing this, the charge in the storage section of the first horizontal register (3) under the electrode (6A) is smoothly transferred to the storage section of the second horizontal register (5) under the electrode (6B). do. Of course,
The charge from the last stage of the other vertical register (IB) is blocked by the channel stopper region (9) and the first
remains in the storage section of the horizontal register (3).

Next, at time 12 (FIG. 3), the other clock terminal (12A) is turned off (low level) while keeping the clock terminal (12B) and the T/S gate (9) on.

Then, as shown in Figure 4B, after being transferred from the final stage of one vertical register (one person), the electrode (
The small amount of charge remaining in the storage section of the first horizontal register (3) under 6A) is completely transferred to the second horizontal register (3).
5) is transferred to the storage section. After this, one time t3 (
In FIG. 3), the T/8 gate (8) is also turned off to prevent charges from being erroneously transferred to the second horizontal register (5) by the subsequent CCD operation of the first horizontal register (3). Also, prevent this reverse erroneous transfer from occurring. Thereafter, the clocks φ1゛ and φ2 are inverted to the clock terminals (12A) and (12B) from the time point shown at time t4 in FIG.
is supplied to cause the horizontal register (31 (51) to operate as a CCD.

Horizontal register f3) (The signal read out at 51 may be read out separately by the output circuit, or horizontal register +31 (51)
) may be added to one of the stages for A bits, the phase may be changed by 1800 between both horizontal registers (3) and (5), and then the signals may be combined using a multi-blephr or the like.

According to this configuration, two horizontal registers (3) (5)
), the number of bits compared to the normal case of one is A, and there is a margin of twice the degree of integration.

For this reason, the number of horizontal pixels increases with higher resolution,
Even when miniaturized to suit a 1/I inch optical system, etc., it is strong against short channel effects and is preferable from the viewpoint of electrode processing accuracy. Also, the horizontal register (
Since the clock frequency for operating the CCD of 31(5) is only a small amount, it is extremely effective in terms of power consumption.

Also, from the first register (3) to the second register (5) K
When transferring charges, electrodes with different phases (6A) (6B
), the electrodes (
6A) There is a degree of freedom in setting the potential in (6B), and the request to deepen the potential well by moving in the transfer direction can be met very easily. For example, it is easy to make the potentials of the two electrodes (6A) and (6B) different, and the amount of ion implantation may be adjusted (51C). Same-
For example, T/
S gates (gates for eight countries, which require slopes in the transfer direction, etc., tend to complicate the configuration. In this example, the transfer efficiency can be easily increased).

Furthermore, in this example, electrodes (6A) (6B) (7A) (7
The shape of B) is tilted in the region of the T/S gate (8), and the channel region αQ is also tilted. For this reason, electrodes (6A) (6B) (7A) (7B) and Hichi'v
7. There is no need to sharply bend the channel la region αe at right angles, which is extremely favorable in terms of electrode processing and charge transfer.

As described in detail, according to the present invention, since two horizontal registers are provided, the number of bits of the horizontal register is reduced to Vz compared to the conventional single horizontal register. Even with miniaturization, there are no problems such as short channel effect or poor electrode processing accuracy. In addition, in order to drain and pass the charge from the vertical register side to the horizontal register that is spaced from the temporary transfer end of the vertical register, the first horizontal register and the second horizontal register are connected to each other.
Because the horizontal resistor electrodes have different phases to form a channel between the storage parts.

Charges can be transferred to the second horizontal register side without delay.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing essential parts of an embodiment of the present invention, FIG. 2 is a sectional view taken along the line ■-B in FIG. 1, and FIG. 3 is a time chart for explaining the embodiment in FIG. 1. . FIG. 4 is a diagram showing the state of the oil potential on the -R line of FIG. 1. (IA) (IB) are vertical registers, (3) (5) are horizontal registers, (6A) (6B) are storage electrodes, (7A) (7B) are transfer electrodes, (8) are T
/S gate. Figure 1 Figure 2 1 t3 Figure 4 Procedural amendment 1, Indication of the case Patent Application No. 121678 of 1982 2, Title of the invention Solid-state imaging device 3, Person making the amendment Relationship to the case Patent applicant address Tokyo Parts Ward Kitashina 6] Nai 7 No. 35 Name (21
8) Sony Corporation Representative Director Ohga JIIH/Jl16, number of inventions increased by amendment 7, month of amendment Claims column of specification, Detailed description of invention column il+ Claims attached. Correct the quality. (2) In the specification, "large" in line 2ji2 is corrected to "small". (3) Same, same page, line 3, ``large'' is corrected to ``small.'' (4) On the same page, line 8, after "Ikuto", "The pitch of the horizontal register (i.e. channel length) becomes shorter,"
join. (5) Same page, lines 18-20 “In this case...
・Requires bits and deletes. (6) Same, same ji 20th line "High resolution for this reason" is changed to "
For this reason, the number of horizontal pixels is increased to achieve high resolution.'' (Power, same, page 3, line 2, 1 larger" is corrected to ``smaller.'' (8) Same, 4th line, lines 1 to 5, "It is necessary." is deleted. ( 9) Same page, lines 8 to 9, delete ``With the arrangement of every other storage electrode.'' σ2 Same, same page, line 12 “storage section” is corrected to “storage electrode (6A) J.” 03 fi’j1. same page, lines 12-13 “under other storage electrode (6B)” is deleted. I. Same, same page, line 13, "storage section" is corrected to "storage electrode (6B) J. a9 Same, page 8, line 15, "bypass" is changed to "charge transfer."
I am corrected. (161 Ibid., page 9, line 19 “Then horizontal register (3)
"The operation of 51" is corrected to "The operation of charge transfer from the end of the vertical register to the horizontal register (31 (51)." Correct. 帥 Same, Key; Delete "invert" on page 11, line 15. Q!l Same, line 12 - 2 "Phase between...
・You may do so. '' should be corrected to ``You may merge at the end of the line and exit.'' ■ On the same page, in line 5, "integration degree" is corrected to "microfabrication." c211 Same page, line 7, "IA inch" is corrected to "1/2 inch". (22, p. 12, line 13 to p. 13, line 5 “Again...
can. ``Delete ``@ Above Claims Comprising a plurality of vertical transfer registers arranged in parallel, and an output section for reading signal charges for each line from the vertical transfer registers, the output section is a control gate. It is composed of a first horizontal output register and a second horizontal output register that are arranged in parallel with each other in between, and outputs every other signal charge among the signal charges of the one line to the first horizontal output register. , in a solid-state sensor in which every other signal charge is outputted to the second horizontal output register, the signal charge is transferred from the first horizontal output register to the second horizontal output register. 2. A solid-state sensor, wherein the transfer is performed between an accumulation section of one phase of the first horizontal output register and an accumulation section of the other phase of the second horizontal output register.

Claims (1)

[Claims] It is equipped with a plurality of vertical transfer registers arranged in parallel and an output section that reads signal charges for each line from the vertical transfer registers. It is composed of a first horizontal output register and a horizontal output register of ritg2 which are arranged in parallel in number, and outputs every other signal charge among the signal charges of the one line to the first horizontal output register. , in a solid-state imaging device in which every other signal charge is outputted from the second horizontal output register, the signal charges are transferred from the first horizontal output register to the second horizontal output register. A solid-state image pickup device, wherein transfer is performed between a 1' phase storage section of the first horizontal output register and another phase storage section of the second horizontal output register.