JPH0542829B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a solid-state image sensing device consisting of a CCD (charge-coupled device), and in particular, to a solid-state image sensing device that is capable of reducing the pitch of horizontal picture elements without reducing the pitch of horizontal registers. , and also avoids the need for a complicated configuration for this purpose.

BACKGROUND TECHNOLOGY AND PROBLEMS As solid-state imaging devices consisting of CCDs, such as frame transfer type ones, are made to have high resolution, the pitch of the horizontal register (that is, the channel length) becomes short, and the short channel effect and electrode Problems with machining accuracy arise. A similar problem arises when the chip size is reduced in response to optical systems becoming progressively smaller from 1 inch to 2/3 inch to 1/2 inch.

That is, in a frame transfer type solid-state image sensor, a signal charge corresponding to an image part and an optical image is formed, the signal charge is transferred vertically to a storage part, and then the charge at the end of the transfer in the storage part is transferred. Read out sequentially using the horizontal register. Therefore, when increasing the number of horizontal picture elements to achieve high resolution, it is necessary to increase the number of bits in the horizontal register. If this happens, the pitch of the horizontal register becomes smaller, causing short channel effects and problems with electrode processing accuracy. A similar problem exists when downsizing a solid-state image sensor. This requires no explanation.

By the way, the present applicant has provided a solid-state image sensor comprising two horizontal registers (Japanese Unexamined Patent Application Publication No. 1983-1999).
No. 181274). In this solid-state image sensor, the signal charges transferred from every other column of the vertical registers forming the storage section are read out by one horizontal register, and the signal charges transferred from the remaining every other column are read out by the other horizontal register. It is read using the horizontal register. Therefore, the number of bits in one horizontal register can be reduced to 1/2, and the above-mentioned short channel effect and problems with electrode processing accuracy can be avoided.

However, in this solid-state image sensor, one horizontal register is placed at the transfer end of the vertical register, and the other horizontal register is placed slightly away from this one horizontal register in the transfer direction, and the other horizontal register is placed in parallel with this one horizontal register. Place registers. Japanese Patent Publication No. 57-181274
In the specific example of the solid-state image sensor in the issue, both horizontal registers are simultaneously driven with the same storage electrode and transfer electrode to operate the CCD, and the storage section of one horizontal register is bypassed to the storage section of the other horizontal register. A channel is formed through which the signal charge of the vertical register can be transferred to the storage section of the other horizontal register.

However, in such a transfer, since the storage section of one register and the storage section of the other register are under the same electrode, the potentials of the channels of both storage sections remain at the same level, and as a result, a certain Special measures are required to create a potential difference.

Purpose of the Invention The present invention has been made in consideration of the above circumstances, and it is possible to achieve high resolution and miniaturization of a solid-state image sensor without reducing the pitch of the horizontal register, and which has a simple configuration. The purpose is to provide a solid-state image sensor.

Summary of the Invention In order to achieve the above object, the present invention provides two horizontal registers to share the horizontal read operation. When transferring the signal charge from the transfer end of the vertical register to the horizontal register separated from the terminal, both horizontal registers are
The two phase electrodes used to operate the CCD are made to work together.

According to the present invention, the short channel effect can be avoided, and power consumption can be further suppressed without causing problems in electrode processing accuracy. Furthermore, there is no need to adopt a particularly complicated configuration for transferring signal charges to the horizontal register spaced apart from the transfer end of the vertical register, and an extremely simple configuration can be achieved.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

1 and 2 show a part of the solid-state image sensing device of this example, and in these FIGS. 1 and 2, vertical registers 1A and 1B forming the storage section are vertically arranged (vertical direction in FIG. 1). are arranged in parallel. These vertical registers 1A and 1B are separated from each other by a channel stopper region 2.
These channel stopper areas 2 are marked with dots. The same applies to other channel stopper areas. Signal charges are transferred to these vertical registers 1A and 1B from an image portion (not shown), and then sequentially transferred in the direction of the arrow.

Each stage of the first horizontal register 3 is coupled to the transfer end of the vertical registers 1A, 1B.
A readout gate 4 is provided at this coupling position, and the transfer from the vertical registers 1A, 1B to the subsequent stage is controlled by the potential applied to this readout gate. A second horizontal register 5 is formed parallel to the first horizontal register 3. These first and second horizontal registers 3, 5 are controlled by, for example, a two-phase clock, and are controlled by common storage electrodes 6A, 6B and transfer electrodes 7A, 7B (shown by broken lines in FIG. 1).
be made to work.

A T/S gate (transfer stop gate) 8 is provided between these horizontal registers 3 and 5. A channel stopper region 9 and a channel region 10 are formed under this T/S gate 8 . Storage electrode 6 of first horizontal register 3
A to the storage electrode 6 of the second horizontal register 5
A channel region 10 is formed toward B. Focusing on the vertical registers 1A and 1B, a channel region 10 is formed corresponding to one vertical register 1A. That is, all vertical registers 1
Channel area 1 every other channel for A, 1B
0 is formed. This chin yannel area 10
As a result, the charges in one vertical register 1A are transferred to the storage section of the second horizontal register 5 via the storage section of the first horizontal register 3.
Transfer of the charges transferred through the other vertical register 1B is blocked by the channel stopper region 9 and remains in the first horizontal register 3.
You will understand this later.

In this example, the shapes of the electrodes 6A, 6B, 7A, and 7B are made oblique in the region of the T/S gate 8. That is, the spatial phase of the electrodes 6A, 6B, 7A, 7B in the area of the first horizontal register 3 is shifted from the phase in the area of the second horizontal register 5. That is, these storage electrodes 6A, 6B and transfer electrodes 7A, 7
B on the first horizontal register 3 and the second horizontal register 5, respectively, on the vertical register 1A.
and 1B are formed as a pattern shifted in a direction perpendicular to the extending vertical transfer direction. In this way, charge can be easily transferred from the storage section under one storage electrode 6A to the storage section of the other storage electrode 6B by slightly tilting the channel region 10. If the shapes of the electrodes 6A, 6B, 7A, and 7B are made straight, the channel region 10 must be extremely bent in the region of the T/S gate 8, and in this way, the width of the channel region 10, which is a charge transfer path, is substantially reduced. As the area becomes narrower, the potential in that area becomes higher due to the narrow channel effect, forming a barrier, and charges accumulate in front of the barrier. In addition, in this case, the channel length becomes long, and the area to which the high potential for transfer to the second horizontal output register is applied is only the planar triangular part where the bending part and the electrode overlap, allowing the charge to be transferred smoothly. There is a risk that it will not be possible. Moreover, if the channel region 10 is made straight, the electrodes 6A, 6B,
The shapes of 7A and 7B must also be extremely bent in the region of the T/S gate 8. Doing this poses a problem in terms of electrode processing accuracy.

In contrast, in this example, since the degree of bending of the channel region 10 is relaxed as described above, the transfer path can be kept wide and the channel length can be made relatively short. The region to which the potential is applied occupies a large proportion of the channel region, creating a gradient of potential in this vicinity, allowing for smooth charge transfer.
Good transfer efficiency can be maintained.

In addition, in this example, as is well known, the storage electrode 6A
and the transmission electrode 7A are commonly connected to the bus bar 11A, and the clock terminal 12A is connected to the bus bar 11A.
The clock _φ1 is supplied through the circuit.
On the other hand, other storage electrodes 6B and transfer electrodes 7B are similarly connected in common to other bus bars 11.
B, and another clock signal _φ2 is supplied through another clock terminal 12B.
These clock signals φ ₁ and φ ₂ cause the horizontal register 3,
No need to explain that 5 is operated by CCD.

In addition, in FIG. 2, 13 is a semiconductor substrate, 1
4 is a gate insulating film, and 15 is an insulating film.

Next, we will explain the operation of this embodiment in Figures 3 and 4.
Let me explain with reference to the diagram. In the following explanation, only the charge transfer operation from the end of the vertical register to the horizontal registers 3 and 5 will be mentioned. A description of charge transfer from the image section to the storage section, which is not shown, will be omitted.

First, in order to read out the charges at the final stage of the vertical registers 1A, 1B, after turning on the read gate 4, the clock terminals 12A, 1 are turned on at time _t1 (Fig. 3).
2B and T/S gate 8 are turned on (high level). Then, as shown in FIG. 4A, the signal charges from the final stage of one vertical register 1A are transferred to the storage sections of horizontal registers 3 and 5. In this case, the potential of the storage section 5 of the second horizontal register may be made deeper than the potential of the storage section of the first horizontal register 3. For example, the on-potential of the storage electrode 6B is made higher than the on-potential of the storage electrode 6A. or,
The impurity concentration and the thickness of the gate insulating film 14 (FIG. 2) are adjusted. By doing this, the electrode 6
The charge in the storage section of the first horizontal register 3 under A smoothly transfers to the storage section of the second horizontal register 5 under electrode 6B. Of course, charges from the final stage of the other vertical registers 1B are blocked by the channel stopper region 9 and remain in the storage section of the first horizontal register 3.

Next, at time t ₂ (FIG. 3), the other clock terminal 12A is turned off (low level) while keeping the clock terminal 12B and the T/S gate 9 on. Then, as shown in FIG. 4B, the slight amount of charge remaining in the storage section of the first horizontal register 3 under the electrode 6A after being transferred from the final stage of one vertical register 1A is also completely transferred to the storage section of the first horizontal register 3 under the electrode 6A. 2
The data is transferred to the storage section of the horizontal register 5.
After this, at time t ₃ (Figure 3), the T/S gate 8 is also turned off to prevent charges from being mistakenly transferred to the second horizontal register 5 due to the subsequent CCD operation of the first horizontal register 3. Make it. Also, prevent this reverse erroneous transfer from occurring. From then on, the clock terminals 12A, 12 are connected from the time point _t4 in FIG.
B, supplying clocks φ ₁ and φ ₂ to horizontal register 3,
5 to operate the CCD.

The signals read out by the horizontal registers 3 and 5 may be read out separately by output circuits, or the signals read out by the horizontal registers 3 and
It is also possible to add a stage for 1/2 bit to one of the horizontal registers 3 and 5 so that the registers merge at the ends of both horizontal registers 3 and 5 and output.

According to this configuration, since two horizontal registers 3 and 5 are used, the number of bits is halved compared to the usual case of one, and there is twice the margin in terms of fine processing. For this reason, even when the number of horizontal pixels increases with higher resolution, or when downsizing to accommodate a 1/2-inch optical system, it is resistant to short channel effects and has a high level of accuracy in electrode processing. It is also preferable from the point of view. Furthermore, since the clock frequency for operating the horizontal registers 3 and 5 on the CCD can be reduced to 1/2, it is extremely effective in terms of power consumption.

Furthermore, in this example, the shapes of the electrodes 6A, 6B, 7A, and 7B are tilted in the region of the T/S gate 8, and the channel region 10 is also tilted. Therefore, there is no need to sharply bend the electrodes 6A, 6B, 7A, 7B and the channel region 10 at right angles, which is extremely favorable in terms of electrode processing and charge transfer.

Effects of the Invention As explained above, according to the present invention, since two horizontal registers are provided, the number of horizontal register bits is halved compared to the conventional single horizontal register, and the high resolution of the solid-state image sensor is achieved. Even with miniaturization and miniaturization, there is no problem in terms of short channel effect or electrode processing accuracy. In addition, in order to bypass the charge from the vertical register side to the horizontal register that is spaced from the transfer end of the vertical register, the first horizontal register and the second
Since a channel is formed between the storage portions of the electrodes of the horizontal registers having different phases, charges can be easily transferred to the second horizontal register side.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing essential parts of an embodiment of the present invention, FIG. 2 is a sectional view taken along the line - in FIG. 1, and FIG. 3 is a time chart for explaining the embodiment in FIG.
FIG. 4 is a diagram showing the state of the potential along the - line in FIG. 1. 1A, 1B are vertical registers, 3, 5 are horizontal registers, 6A, 6B are storage electrodes, 7A, 7B
is a transfer electrode, and 8 is a T/S gate.

Claims (1)

[Claims] 1. A plurality of vertical transfer registers arranged in parallel, and an output section for reading signal charges for each line from the vertical transfer registers, and the output section is provided side by side with a transfer/stop gate section in between. and each first clock is supplied to a first horizontal transfer electrode pair consisting of every other commonly connected storage electrode and transfer electrode,
The first horizontal output register and the second horizontal output register are configured such that a second clock is supplied to a second horizontal transfer electrode pair consisting of every other storage electrode and transfer electrode that are commonly connected. Outputs every other signal charge among the signal charges of the one line to the first horizontal output register, and outputs the other every other signal charge from the first horizontal register to the transfer/stop gate section. In the solid-state imaging device which outputs signal charges to the second horizontal output register via a channel, the transfer of signal charges from the first horizontal output register to the second horizontal output register is performed in the two adjacent horizontal output registers. between the storage section under the first horizontal transfer electrode pair of the first horizontal output register and the storage section under the second horizontal transfer electrode pair of the second horizontal output register via the channel, Bend in one direction, and connect the first and second horizontal transfer electrode pairs to the transfer/transfer electrode pair.
A solid-state image sensor characterized in that it is arranged by being bent in the other direction at a stop gate portion.