JPH0750409A - Solid state image pick-up element - Google Patents

Abstract

PURPOSE:To enable a subject in low brightness to be image picked-up by enhancing the sensitivity during high sensitivity time within the sensitivity transfer functional image pick-up element. CONSTITUTION:A charge transfer channel 18 is branched into two parts to transfer low, high of the control signals phiC1, phiC2 impressed on control electrodes 10, 11; 12, 13 so that signal charge may be transferred to either one transfer channel. At this time, the floating regions 101, 102 in different areas for charge.voltage conversion are arranged in the output part of respective transfer channels. In such a constitution, the charge voltage conversion is to be performed for low and high brightness subject image pick-up times respectively using the small area region 102 and the large area region 101.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to FDA (Floating Dif
More specifically, the present invention relates to a solid-state image sensor that can switch the charge / voltage conversion efficiency thereof.

[0002]

2. Description of the Related Art A solid-state image pickup device using a CCD shift register is used as an autofocus sensor for a camera and an image sensor for a fax scanner. In particular, in the case of a camera, there is a demand for a sensor having high sensitivity at low brightness and wide dynamic range at high brightness so that focusing can be performed from low brightness to high brightness. Therefore, in the conventional solid-state image pickup device, means for changing the capacitance of the charge / voltage conversion unit is provided.

FIG. 6 is a plan view showing a state near an output portion of a conventional solid-state image pickup device. In FIG. 6, 5 is an n-type diffusion layer to be a reset drain, 6 is a reset gate electrode, 7 is an output gate electrode to which a constant output gate voltage V _OG is applied, and 8 and 9 are a pair. Transfer clock φ
Transfer electrodes 1 and φ2 are applied, reference numerals 20 and 21 are sensitivity switching gate electrodes to which the selection signals SEL1 and SEL2 are applied, respectively, and 14 is an output amplifier. Here, the selection signals SEL1 and SEL2 are signals that are in opposite phase to each other.

Next, the operation of the charge / voltage converter will be described with reference to FIG. 7A is a cross-sectional view taken along the line BB ′ of FIG. 6, and FIGS. 7B, 7C, and 7D are potential diagrams under the line BB ′ of FIG. 6, respectively. In FIG. 7A, 1 is an n-type semiconductor substrate, 2 is a p-type diffusion layer, 3 is an n-type diffusion layer that serves as a charge transfer channel, and 4 is a p-type diffusion layer that serves as a barrier layer. A case where the selection signal SEL1 is at low level will be described. In FIG. 7B, the clock φ1
Is high level, clock φ2 is low level, φ1
Signal charges are accumulated below the transfer electrode 8 to which is applied. Further, the reset pulse φR is at high level,
The potential of the floating region 110 is reset to the potential of the n-type diffusion layer 5 to which a constant reset drain voltage V _RD is applied. In FIG. 7C, when φR becomes low level, a potential barrier is formed below the reset gate electrode 6, and the region 110 becomes in a floating state.
In FIG. 7D, φ1 becomes low level and φ2 becomes high level, and the signal charge Qsig is transferred to the region 110. As a result, the potential of the floating region 110 changes, and the potential change is taken out through the output amplifier 14.

Next, a mode of charge / voltage conversion at low brightness and high brightness will be described with reference to FIGS. 8 and 9, respectively. FIG. 8A is a sectional view taken along the line CC ′ of FIG. 6, and FIG.
FIG. 7 is a potential diagram under the line CC ′ of FIG. 6 at the timing of FIG. 7D when the selection signal SEL1 is set to low level and the selection signal SEL2 is set to high level. Figure 8 (b)
As shown by, the SEL1 is set to the low level when the luminance is low, and a potential barrier is formed under the sensitivity switching gate electrode 20. The signal charge Qsig is accumulated under the region 110, and the potential of the region 110 changes by ΔVsigA,
This potential change is output through the output amplifier 14 to the output terminal Vou.
It is taken out as a signal voltage from t. Now, assuming that the sum of the parasitic capacitances in the region 110 is C110, the potential change ΔVsigA is ΔVsigA = Qsig / C110.

FIG. 9 (a) is a sectional view taken along the line CC 'of FIG. 6, and FIG. 9 (b) is of FIG. 7 (d) when SEL1 is at a high level and SEL2 is at a low level. FIG. 7 is a potential diagram under the line CC ′ of FIG. 6 at a timing. Figure 9
As shown in (b), when the brightness is high, SEL1 is set to a high level and SEL2 is set to a low level to form a potential barrier below the sensitivity switching gate electrode 21. As a result, the region 111 is added to the floating region 110, and the combined region of both regions 110 and 111 functions as a floating region. Transferred signal charge Qsig
Are accumulated in the regions 110 and 111, the potentials of the regions 110 and 111 change by ΔVsigB, and this potential change is taken out from the output terminal Vout as a signal voltage through the output amplifier 14.

Now, the sum of the parasitic capacitances in the region 111 is C
When the value is 111, the potential change ΔVsigB is ΔVsigB = Qsig / (C110 + C111). Here, since C110 + C111> C110, ΔVsigB <ΔVsigA holds, and even in the case of the same signal charge amount, the potential change is different between the case shown in FIG. 8 and the case shown in FIG. That is, the charge
The voltage conversion efficiency is different. FIG. 10 is a graph showing the relationship between the exposure amount and the output signal when the brightness is low and when the brightness is high. in this way,
In the solid-state image sensor shown in FIG. 6, the selection signals SEL1 and S
By switching the EL2 between low and high, it is possible to increase the charge / voltage conversion efficiency at low brightness and increase sensitivity, and decrease the charge / voltage conversion efficiency at high brightness to widen the dynamic range.

[0008]

However, in spite of the demand for further increasing the sensitivity at low luminance, that is, the charge / voltage conversion efficiency, in the above-mentioned conventional solid-state image pickup device, the capacitance parasitic on the floating region 110 is required. among,
In particular, since the parasitic capacitance with the sensitivity switching gate electrode 20 is large and the structure of the charge / voltage conversion unit is complicated and the area is large, there is a limit to the improvement of the charge / voltage conversion efficiency. . Therefore, it is an object of the present invention to reduce the capacitance of the floating region that performs charge / voltage conversion at low luminance and increase the sensitivity at low luminance in a solid-state imaging device having a sensitivity switching function. .

[0009]

To achieve the above object, according to the present invention, a signal charge generated by photoelectric conversion, which is branched into at least two transfer channels in the charge transfer direction, is transferred. And a charge / voltage conversion unit provided at the tip of each branched transfer channel of the CCD shift register. The charge / voltage conversion units have charge / voltage conversion efficiencies with each other. There is provided a solid-state image sensor characterized by being different.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a plan view showing a state in the vicinity of a charge detection unit according to an embodiment of the present invention. The illustrated CCD shift register is adjacent to the pixel column at the left side of the branch point, receives the signal charges from the pixels in the pixel column, and transfers the signal charges to the right in the figure. In FIG. 1, 5 is
An n-type diffusion layer that constitutes a reset drain that resets the potentials of the floating regions 101 and 102, and a reset drain voltage V _RD of a constant voltage is applied to this diffusion layer. 6 is the floating regions 101, 10
It is a reset gate electrode for resetting the potential of 2, and a reset pulse φR is applied. 7 is an output gate electrode to which a constant output gate voltage V _OG is applied,
Reference numerals 8 and 9 denote transfer electrodes for transferring the signal charges toward the region 101 or the region 102. These electrodes are pairs of adjacent electrodes, and the transfer clocks φ1 and φ2 is applied.

Numerals 10 to 13 are control electrodes for controlling whether the signal charges are transferred to the floating region 101 or the floating region 102, and the control electrodes φC1 and the control electrodes 10 and 11 are also controlled. Electrode 12,
A control signal φC2 is applied to 13. 14 is area 1
This is an output amplifier for extracting the potentials of 01 and 102 to the outside as an output signal, and performs impedance conversion and signal amplification. Reference numerals 15 and 16 are control switches for selecting whether to take out the potential of the region 101 or the potential of the region 102 as an output signal, and the selection signals SEL1 and SEL2 are applied to the switches 15 and 16, respectively. The output signal selected by the control switches 15 and 16 is taken out from the output terminal Vout. Reference numeral 17 denotes a transfer electrode adjacent to the control electrodes 11 and 13, and the charge transfer channel 18 branches under this transfer electrode.

The areas of the floating region 101 and the floating region 102 are different from each other. Therefore, the charge / voltage conversion efficiency for converting the signal charge into a potential change is different. Here, the area 102 is the area 10
It is smaller than 1 and about half the size. Of course, the size ratio is not limited to this and may be any value. Next, the operation of the present embodiment will be described with reference to FIGS. 2, 3 and 4 and 5. FIG. 2 shows clocks φ1, φ2, control signals φC1, when converting the amount of signal charges into a signal voltage using the floating region 102.
It is a figure which shows the timing of (phi) C2 and reset pulse (phi) R. FIG. 3A is a cross-sectional view taken along the line AA ′ in FIG. 1, but the number of transfer electrodes 8 and 9 is omitted to be 6 for simplifying the description. But this is enough to understand the behavior. In FIG. 3A, 1 is an n-type semiconductor substrate, 2
Is a p-type diffusion layer, 3 is an n-type diffusion layer, and constitutes the charge transfer channel 18 and the floating regions 101 and 102. Reference numeral 4 is a p-type diffusion layer for determining the charge transfer direction.

3 (b), (c), (d), (e),
(F) indicates times t1, t2, t3, and t in FIG. 2, respectively.
It is a potential diagram in 4 and t5. Signal charge Q1, Q
Normal C until 2 and Q3 are transferred under the transfer electrode 17.
This is the same as the transfer of the CD shift register. As shown in FIG. 2, the signal φC1 is always at the low level. As shown in FIG. 3B, at time t1, the signal charge Q1 is accumulated in the potential well below the transfer electrode 17 to which the clock φ1 is applied. At time t2, the clock φ
1, φ2, the level of the control signal φC2 changes, and
As shown in (c), the signal charge Q1 is transferred to the potential well below the transfer electrode 12 to which the signal φC2 is applied.

At time t3, clocks φ1,
When the levels of φ2 and the control signal φC2 change, FIG.
As shown in (d), the next signal charge Q2 is transferred to the potential well under the transfer electrode 17, and at the same time, the signal charge Q1 is also transferred under the next transfer electrode. At time t4, FIG.
As shown in (e), the signal charge Q2 is transferred to the potential well below the transfer electrode 12 to which the signal φC2 is applied, similarly to the signal charge Q1 at the time t2, and at the same time, the signal charge Q1 is further transferred to the next transfer electrode. Transferred to. Next, when φ1 becomes high and φ2 becomes low, the next signal charge Q3 is transferred to below the transfer electrode 17, as in the case shown in FIG.
The signal charge Q1 is transferred to the potential well below the final transfer electrode 8. Further, at time t5, as shown in FIG. 3 (f), the signal charge Q1 is transferred to the region 102 and the region 10
The potential of 2 is changed by ΔVsig2. By turning on the control switch 16 and turning off the control switch 15, the potential change in the region 102 is taken out as a signal voltage from the output terminal Vout to the outside through the output amplifier 14. Here, assuming that the sum of parasitic capacitances in the floating region 102 is C102, the potential change ΔVsig2 is ΔVsig2 = Q1 / C102.

FIG. 4 is a diagram showing timings of the transfer clocks φ1 and φ2, the control signals φC1 and φC2, and the reset pulse φR when the signal charge amount is converted into the signal voltage using the region 101. 5A is a cross-sectional view taken along the line AA ′ of FIG. 1 and is the same as FIG. 3A. Figure 5
(B), (c), (d), (e) and (f) are potential diagrams at times t6, t7, t8, t9 and t10 in FIG. 4, respectively.

The signal charges Q4, Q5 and Q6 are transferred to the transfer electrode 17.
Until it is transferred downward, it is the same as the transfer in the case of a normal CCD shift register. As shown in FIG. 4, the control signal φC
2 is always low level. As shown in FIG. 5 (b),
At time t6 in FIG. 4, the signal charge Q4 is accumulated in the potential well below the transfer electrode 17 to which the signal φ1 is applied. At time t7, the levels of the clocks φ1 and φ2 and the control signal φC1 change, and the signal charge Q4 becomes as shown in FIG.
As shown in (c), the signal φC1 is transferred to the potential well below the transfer electrode 10 to which the signal φC1 is applied. Time t
8, clocks φ1, φ2, control signal φC
When the level of 1 changes, as shown in FIG. 5D, the next signal charge Q is transferred to the potential well below the transfer electrode 17.
5 is transferred, and at the same time, the signal charge Q4 is also transferred below the next transfer electrode. At time t9, as shown in FIG.
Like the signal charge Q4 at time t7, the signal charge Q5 is transferred to the potential well below the transfer electrode 10 to which the signal φC1 is applied, and at the same time, the signal charge Q4 is further transferred to the next transfer electrode. Next, when φ1 becomes high and φ2 becomes low, the next signal charge Q6 is transferred below the transfer electrode 17 and the signal charge Q4 is transferred below the final transfer electrode 8 as in the case shown in FIG. 5D. Transferred to the potential well. Further, at time t10, as shown in FIG.
The signal charge Q4 is transferred to the region 101, and the potential of the floating region 101 changes by ΔVsig1.

When the control switch 16 is turned off and the control switch 15 is turned on, the potential change ΔVsig1 in the region 101 is taken out as a signal voltage from the output terminal Vout to the outside through the output amplifier 14. Here, assuming that the total of the parasitic capacitances in the region 101 is C101, the potential change ΔVsig1
Is ΔVsig1 = Q4 / C101. As described above, in this embodiment, the area of the region 102 is about 1/2 of the area of the region 101, so C101 is C
It is about twice that of 102. Therefore, ΔVsig2≈2 × ΔVsig1 is established, and by controlling the control signals φC1 and φC2 to induce the signal charge to either of the transfer electrodes 10, 11; 12, 13 to convert the signal charge amount into the output voltage. The charge / voltage conversion efficiency can be switched.

According to this embodiment, the floating region 1
01 and the floating region 102 do not require a sensitivity switching gate electrode as in the conventional example, so that the parasitic capacitance can be reduced by about 10% even in the same area. Further, since the structure of the charge / voltage conversion unit is simplified, the area itself can be reduced by about 10%, and the charge / voltage conversion efficiency can be improved by about 20% as compared with the conventional case.

In the above description, the case where the charge transfer channel is branched into two has been described, but the above embodiment may be modified to branch into three or more. Further, after branching once into several lines, each may be further branched into several lines. By doing so, the charge / voltage conversion efficiency can be switched in several stages. Further, although the above description has been made on the embedded channel type solid-state image pickup device, the present invention can be applied to a solid-state image pickup device in which a part or all of the device is a surface channel. Further, although the one-dimensional solid-state imaging device has been described in the embodiment, the present invention can be similarly applied to the two-dimensional solid-state imaging device by adding a branch to the horizontal transfer shift register. Further, it is also possible to reverse all the polarities of the conductivity types in the embodiments, reverse the positive and negative signs of the applied power source and signal potential, and configure a similar solid-state imaging device on the p-type semiconductor substrate.

[0020]

As described above, in the solid-state image pickup device of the present invention, the transfer channel of the CCD shift register is branched into a plurality of channels near the final stage of the transfer channel,
According to the present invention, since an output part having different charge / voltage conversion efficiency is connected to each of the branched channels so that the signal charge can be induced to one of the branched channels, an extra output is provided to each output part. It is possible to switch the charge / voltage conversion efficiency without attaching a special gate electrode or the like. Therefore, according to the present invention, it is possible to provide a solid-state imaging device with a sensitivity switching function, which can perform imaging with sufficiently high sensitivity when imaging a low-luminance subject.

[Brief description of drawings]

FIG. 1 is a plan view showing the vicinity of an output unit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment shown in FIG.

3 is a cross-sectional view taken along the line AA ′ in FIG. 1 and a potential diagram at the timing shown in FIG. 2 in the cross section.

FIG. 4 is another timing diagram for explaining the operation of the embodiment of FIG.

5 is a cross-sectional view taken along the line AA ′ in FIG. 1 and a potential diagram at the timing shown in FIG. 4 in the cross section.

FIG. 6 is a plan view of the vicinity of an output section of a conventional example.

7A and 7B are a cross-sectional view taken along the line BB 'in FIG. 6 and a potential diagram at each timing in the cross-section.

FIG. 8 is a cross-sectional view taken along the line CC ′ of FIG. 6 and a potential diagram in the cross section.

9 is a sectional view taken along the line CC ′ of FIG. 6 and a potential diagram in the section.

FIG. 10 is a graph showing a relationship between an exposure amount and an output signal in a conventional example.

[Explanation of symbols]

 1 n-type semiconductor substrate 2, 4 p-type diffusion layer 3, 5 n-type diffusion layer 6 reset gate electrode 7 output gate electrode 8, 9, 17 transfer electrode 10, 11, 12, 13 control electrode 14 output amplifier 15, 16 control Switch 18 Charge transfer channel 20, 21 Sensitivity switching gate electrode 101, 102, 110 Floating region 111 Region

Claims (4)

[Claims] 1. A CCD shift register for transferring signal charges generated by photoelectric conversion, which is branched into at least two transfer channels in a charge transfer direction,
In a solid-state imaging device having a charge / voltage converter provided at the tip of each branched transfer channel of the CCD shift register, the charge / voltage converters have different charge / voltage conversion efficiencies. A solid-state image sensor characterized by the above. 2. The solid-state imaging device according to claim 1, wherein each of the branched transfer channels is provided with a control electrode adjacent to the branch point for inducing a signal charge in the transfer channel. . 3. The solid-state imaging device according to claim 1, wherein each charge / voltage conversion unit includes a floating diffusion layer, and each diffusion layer has a different surface area. 4. The solid-state imaging device according to claim 1, wherein an output amplifier is connected to each charge / voltage conversion unit, and each output amplifier is provided with means for invalidating its output. element.