JPS59132170A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59132170A JPS59132170A JP702083A JP702083A JPS59132170A JP S59132170 A JPS59132170 A JP S59132170A JP 702083 A JP702083 A JP 702083A JP 702083 A JP702083 A JP 702083A JP S59132170 A JPS59132170 A JP S59132170A
- Authority
- JP
- Japan
- Prior art keywords
- silicon film
- film
- polycrystalline silicon
- silicon
- concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 17
- 229910052710 silicon Inorganic materials 0.000 abstract description 17
- 239000010703 silicon Substances 0.000 abstract description 17
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 17
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- 239000011574 phosphorus Substances 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 55
- 238000000034 method Methods 0.000 description 16
- 238000005530 etching Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000927 vapour-phase epitaxy Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 229920006268 silicone film Polymers 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- QVMHUALAQYRRBM-UHFFFAOYSA-N [P].[P] Chemical compound [P].[P] QVMHUALAQYRRBM-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置、特にフローティングゲートをも
つ、二重ゲート型の不揮発性記憶装置に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a double-gate nonvolatile memory device having a floating gate.
第１図（ａ）および第１図中）は従来の半導体装置を示
す主な製造工程別の断面図である。同図において、（１
）ｉｊシリコン基板、（２）はこのシリコン基板０）上
の不活性領域上に選択的に形成した比較的厚い酸化膜、
（３）は活性領域上に形成した比較的薄い例えば１００
ＯＡの第１の酸化シリコン膜、（４）はこの第１の酸化
シリコン膜０）上に例えば３０００Ａの厚さに形成した
第１の多結晶シリコン膜、６）は比較的薄い例えば１０
０ＯＸの厚さの第２の酸化シリコン膜、（６）は例えば
３５００Ａの厚さに形成した第２の多結晶シリコン膜で
ある。FIG. 1(a) and FIG. 1(a) are cross-sectional views showing a conventional semiconductor device according to the main manufacturing steps. In the same figure, (1
)ij silicon substrate, (2) is a relatively thick oxide film selectively formed on the inactive region on this silicon substrate 0),
(3) is a relatively thin film formed on the active region, e.g.
The first silicon oxide film of OA, (4) is a first polycrystalline silicon film formed to a thickness of, for example, 3000A on this first silicon oxide film (0), and (6) is a relatively thin film of, for example, 10A.
The second silicon oxide film (6) with a thickness of 0OX is a second polycrystalline silicon film formed with a thickness of 3500A, for example.
次に上記構成による半導体装置の製造工程について説明
する。まず、シリコン基板（１）上の不活性領域に比較
的厚い酸化膜Ｃ２）を選択的に形成したのち、活性領域
上に例えば９５０℃、Ｈν喝、雰囲気で熱処理すること
によシ、比較的薄い例えば１００ＯＡの第１の酸化シリ
コン膜（３）全生成する。次に、この第１の酸化シリコ
ン膜（３）上に第１の多結晶シリコン膜（４）を例えば
減圧気相成長法によシ、例えば３０００Ａの厚さに成長
させる。次に、°例えば９００℃。Next, the manufacturing process of the semiconductor device with the above configuration will be explained. First, a relatively thick oxide film C2) is selectively formed on the inactive region on the silicon substrate (1), and then a relatively thick oxide film C2) is formed on the active region by heat treatment at, for example, 950° C. in an atmosphere. A first silicon oxide film (3) having a thickness of, for example, 100 OA is completely formed. Next, a first polycrystalline silicon film (4) is grown on this first silicon oxide film (3) to a thickness of, for example, 3000 Å by, for example, a low pressure vapor phase growth method. Next, °for example 900 °C.
Ｐｕ５１０．雰囲気で熱処理することはよシ、前記第１
の多結晶シリコン膜（４）中にリンを拡散し、１×１０
”ＯＦ＋−’程度の濃【にする。次に、この第１の多結
晶シリコン膜（４）および第１の酸化シリコン膜（３）
を選択的に除去する。次に例えば９５０℃Ｈｚ１０ｓ雰
囲気で熱処理することによシ、第１の多結晶シリコン膜
（４）および先のｔ択除去にょシ露出したシリコン基板
（１）上に比較的薄い例えばｘｏｏｏ′Ａの厚さに第２
の酸化シリコン膜（５渣生成する。次に、第２の多結晶
シリコン膜（６渣減圧気相成長法にょシ、例えば３５０
０Ａの厚さに生成する。次に、第２の多結晶シリコン膜
（６）中に、？’ｉｌ エバ１０００ｐ 、 ＰＨａ
１０゜雰囲気で熱処理することにょシ、リンを例えば２
×１０ｔ１ｎ 程度に拡散する。次に、第２の多結晶
シリコン膜（６）、第２の酸化シリコ／１（５）、ｉ
１の多結晶シリコン膜（４）および第１の酸化シリコン
膜（３）を自己整合的に、連続的にかつ選択的に除去す
る。次に、例えばイオン注入法でＡｓを注入し、ソース
領域およびドレイン領域を形成する。次に表面平坦化工
程、コンタクト工程、配線工程１表面保護工程をへて、
フローティングゲート型、不揮発生記憶装置の記憶素子
部を形成することができる。このとき、第１の多結晶シ
リコン膜（４）はフローティングゲルトとして動作し、
第２の多結晶シリコン膜（６）は制御ゲートとして動作
する。Pu510. It is better not to perform heat treatment in an atmosphere.
Phosphorus is diffused into the polycrystalline silicon film (4) of 1×10
The density should be about "OF+-".Next, this first polycrystalline silicon film (4) and first silicon oxide film (3)
selectively remove. Next, a relatively thin layer of, for example, 2nd in thickness
Next, a second polycrystalline silicon film (6 residues) is formed by low pressure vapor phase epitaxy, e.g.
Produced to a thickness of 0A. Next, in the second polycrystalline silicon film (6), ? 'il Eva 1000p, PHa
For example, when heat-treating in a 10° atmosphere, phosphorus is
Diffusion to approximately ×10t1n. Next, the second polycrystalline silicon film (6), the second silicon oxide/1 (5), i
The first polycrystalline silicon film (4) and the first silicon oxide film (3) are removed continuously and selectively in a self-aligned manner. Next, As is implanted using, for example, an ion implantation method to form a source region and a drain region. Next, through the surface flattening process, contact process, wiring process 1 surface protection process,
A storage element portion of a floating gate type nonvolatile storage device can be formed. At this time, the first polycrystalline silicon film (4) operates as a floating gel,
The second polycrystalline silicon film (6) operates as a control gate.
なお、上述の構成による記憶装置ではドレインに例えば
１８．Ｖ奪印加し、制御ゲートに例えば ２５Ｖを印加
すると、ソースとドレイン間でポットエレクトロンを形
成し、これを゛制御ゲートと容量的に結合し、高・電位
に力っているフローティングゲートに注入すΣ。このエ
レクトロンが７０−ティングゲートに保持されることに
ょシ、このＭＯ８素子の閾値電圧が増加することにょシ
、記憶の有無が判別でき名。そして、制御ゲートに印加
する電圧をエレクトロンの注入前の閾値電圧とエレクト
ロンが注入された後の閾値電圧の中間値に設定すること
により、エレクトロン注入の有無を外部的に簡単に読み
出すことができる。Note that in the storage device having the above-described configuration, for example, 18. When V is deprived and, for example, 25V is applied to the control gate, pot electrons are formed between the source and drain, which are capacitively coupled to the control gate and injected into the floating gate, which is being applied to a high potential. Σ. If these electrons are held in the 70-digit gate, the threshold voltage of this MO8 element increases, and the presence or absence of memory can be determined. By setting the voltage applied to the control gate to an intermediate value between the threshold voltage before electron injection and the threshold voltage after electron injection, the presence or absence of electron injection can be easily read externally.
しかしながら、従来の半導体装置では自己整合的にエツ
チングする際、第２の多結晶シリコン膜（６）、第λの
酸化シリコン膜６）を除去したのち、第１の多結晶シリ
コン膜（４）を除去する際、第１の多結晶シリコン膜（
４）のＰ濃度が低いため、エツチング速展が遅く、これ
にょ広 Ｐ濃度の高い第２のす結晶シリコーン膜（６）
のサイドエッチが進み、制御ゲートとフローティングゲ
ートの容量が減少し、・エレクトロン注入時（書き込み
時）に、フローティング電圧が上がらず、書き込み効率
が低下し、書き込み不良が発生し易くなる。また、第２
の酸化シリコン膜（５）を生成したのち、第１の多結晶
シリコン膜（４）のエツジの下側が鋭角と彦り、第１の
多籍晶シリコン膜（４）と第２の多結晶シリコン膜（６
）の間の耐圧が悪く、−フローティングゲートに注入さ
れたエレクトロンが、この間を通して流れ易くなシ、エ
レクトロンの保持が悪く、揮発し易くなるなどの欠点が
あった。However, in conventional semiconductor devices, when performing self-aligned etching, after removing the second polycrystalline silicon film (6) and the λth silicon oxide film (6), the first polycrystalline silicon film (4) is removed. When removing, the first polycrystalline silicon film (
Since the P concentration in 4) is low, the etching rate is slow and this is wide.Second crystalline silicone film with high P concentration (6)
As side etching progresses, the capacitance of the control gate and floating gate decreases. - During electron injection (writing), the floating voltage does not rise, writing efficiency decreases, and writing failures are more likely to occur. Also, the second
After forming the silicon oxide film (5), the lower side of the edge of the first polycrystalline silicon film (4) turns into an acute angle, and the first polycrystalline silicon film (4) and the second polycrystalline silicon film Membrane (6
), the electrons injected into the floating gate do not easily flow through this gap, and the electrons are poorly retained and easily volatilized.
したがって、この発明の目的は書き込み効率がよく、シ
かも保持特性のすぐれた二重ゲート型の不揮発性記憶装
置の半導体装置を提供するものである。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device of a double gate type non-volatile memory device which has good write efficiency and excellent retention characteristics.
このような目的を達成するため、この発明はフローティ
ングゲートを構成する多結晶シリコン中に添加する不純
物濃＃’ｔ Ｉ Ｘ １０”０ｃｒｎ−”以上に形成す
るものであり、以下実施例を用いて詳細に説明する。In order to achieve such an object, the present invention is to form a floating gate with an impurity concentration of #'t I Explain in detail.
第２図Ｇ）および第２図（ロ）はこの発明に係る半導体
装置の一実施例を示す主な工程別の断面図である。同図
において、（７）は不純物濃度を１ ｘ １ｏ”Ｉｙｎ
−８以上に添加したフローティングゲートとして動作す
る第１の多結晶シリコン膜である。なお、第３図は横軸
に第１の多結晶シリ、コン膜（７）のＰ濃度をとシ、縦
軸に第１の多結晶シリコン膜と第２の多結晶シリコン膜
との間に耐圧番とったときのＰ濃度依存性を示す図であ
る。FIG. 2G) and FIG. 2(B) are sectional views showing one embodiment of the semiconductor device according to the present invention, showing each main process. In the same figure, (7) means that the impurity concentration is 1 x 1o"Iyn
This is a first polycrystalline silicon film that operates as a floating gate with a doping concentration of −8 or more. In addition, in FIG. 3, the horizontal axis shows the P concentration of the first polycrystalline silicon film (7), and the vertical axis shows the P concentration between the first polycrystalline silicon film and the second polycrystalline silicon film. FIG. 3 is a diagram showing the P concentration dependence when the breakdown voltage number is taken.
次に、上記構成による半導体装置、特に二重ゲート型子
揮発Ｊ１生記憶装置の製造工程について説明する。まず
、シリコン基板（１）上の不活性領域に比較的厚い酸化
膜（２）全選択的に形成したのち、活性領域上に例えば
９５０℃’ 、 Ｈｚ １０２雰囲気で熱処理すること
によシ、比較的薄い例えば１００ＯＡの第１の酸化シリ
コン族（３）全生成する。次に、この第１の酸化シリコ
ン族（３）上に第１−の多結晶シリコン膜（７）ヲ例え
ば減圧気相成長法によシ例えば３０００Ａの厚さに成長
させる。次に、例えば１０００℃、 ＰＨｓ／Ｑ’ｓ雰
囲気で熱処理することによシ、前記第１の多結晶シリコ
ン、＠（７）中にリンを拡散し、２ Ｘ １０”ｏｎ
’程度の濃度にする。次に、この第１の多結晶シリコン
膜（７）および第１の酸化シリコン膜（３）を選択的に
除去する。次に、例えば９５Ｑ℃ Ｉ（ｔｌｏ、雰囲気
で熱処理することにより、第１の多結晶シリコン膜σ）
コン膜（５）全生成する。次に、第２の多結晶シリコン
膜（６）ヲ例えば減圧気相成長法により３５００Ａの厚
さに生成する。そして、１０００℃、 ＰＨ５１０，雰
囲気で熱処理することによシ、前記第２の多藷晶シリコ
ン膜（６）中にリンを拡散し、例えば２×１０１１０Ｑ
ｎ−８程度の濃度にする。次に、第２の多％ｉｉｉ品シ
リコシ膜（６）、第２の酸化シ・リコン膜（５）、第１
の多結晶シリコン族（７）および第１の酸化シリコンＮ
（３）ｋ自己整合的に連続的に・力・つ選択的に除去す
る。次に例えばイオン注入法で砒素（Ａ８）を注入し、
ソース領域およびドレイン領域を形成する。次に、表面
平坦化工程、コンタクト工程、配線工程２表面保護工程
をへて、二重ゲート型不揮発柱記憶装置の記憶素子部を
形成することができる。このとき、第１の多結晶シリコ
ン膜（７）はフローティングゲートとして動作し、２：
２の多結晶シリコン膜（６）は制御ゲートとして動作す
る。Next, the manufacturing process of the semiconductor device having the above structure, particularly the double gate type volatile J1 raw memory device, will be explained. First, a relatively thick oxide film (2) is completely selectively formed on an inactive region on a silicon substrate (1), and then a heat treatment is performed on the active region in an atmosphere of 950° C. and 102 Hz for comparison. A first silicon oxide group (3) with a thin target, for example, 100 OA is produced. Next, a first polycrystalline silicon film (7) is grown on the first silicon oxide group (3) to a thickness of, for example, 3000 Å by, for example, a low pressure vapor phase growth method. Next, phosphorus is diffused into the first polycrystalline silicon @(7) by heat treatment at 1000° C. in a PHs/Q's atmosphere, for example, to form a 2×10”on
Make the concentration about '. Next, this first polycrystalline silicon film (7) and first silicon oxide film (3) are selectively removed. Next, for example, the first polycrystalline silicon film σ is heated at 95Q°C I (tlo) by heat treatment in an atmosphere.
Con membrane (5) is completely generated. Next, a second polycrystalline silicon film (6) is formed to a thickness of 3500 Å by, for example, low pressure vapor phase epitaxy. Then, phosphorus is diffused into the second polycrystalline silicon film (6) by heat treatment at 1000° C. and pH 510 in an atmosphere to form, for example, 2×10110Q.
Make the concentration about n-8. Next, the second polyurethane silicone film (6), the second silicon oxide film (5), and the first
of the polycrystalline silicon group (7) and the first silicon oxide N
(3) k Self-aligned continuous/force/selective removal. Next, for example, arsenic (A8) is implanted by ion implantation method,
Form source and drain regions. Next, through a surface flattening process, a contact process, a wiring process, and a surface protection process, a memory element portion of a double-gate nonvolatile columnar memory device can be formed. At this time, the first polycrystalline silicon film (7) operates as a floating gate, and 2:
The polycrystalline silicon film (6) of No. 2 operates as a control gate.
なお、上述の実施例では第１の多結晶シリコン膜（７）
ｆ：２ Ｘ １０ ｃｍ 程度の濃度にしたが、ｌ
Ｘｌ０”ｃｍ−”以上であればよいことはもちろんであ
る。また、この第１の多結晶シリコン膜（７）および第
２の多結晶シリコン膜（６）の成長に、減圧気相成長法
を用いたが、常圧気相成長法、プラズマ気相成長法。Note that in the above embodiment, the first polycrystalline silicon film (7)
f: The density was set to about 2 x 10 cm, but l
Of course, it is sufficient if it is not less than Xl0"cm-". Further, although the first polycrystalline silicon film (7) and the second polycrystalline silicon film (6) were grown using a low pressure vapor phase epitaxy method, a normal pressure vapor phase epitaxy method and a plasma vapor phase epitaxy method were used.
スパッター法２分子線成長法を用いてもよいことはもち
ろんである。また、不純物として、リン使）を用いたが
・砒素（Ａｓ）ｔボロン（Ｂ）、アンチモン（ｓｂ）な
どを用いてもよいことはもちろんである。Of course, the sputtering bimolecular beam growth method may also be used. Further, although phosphorus (phosphorus) was used as an impurity, it goes without saying that arsenic (As), boron (B), antimony (sb), etc. may also be used.
また、不純物の導入は多結晶シリコン成長時に行ない、
イオン注入法、他の熱拡散法を用いてもよいことはもち
ろんであ゛る。In addition, impurities are introduced during polycrystalline silicon growth.
Of course, ion implantation and other thermal diffusion methods may be used.
〔発明の効果〕
以上詳細に説明したように、この発明に係る半導体装置
によれば自己整合的にエツチングした際に、第１の多結
晶シリコン層の除去を行なうときに、第２の多結晶シリ
コン層のサイドエッチ量が軽減され、書き込み効率がよ
くなる。また、第２の酸化シリコン膜を形成したのち、
第１の多結晶シリコン膜のエツジが丸みを持ち、第１の
多結晶シリコン膜と第２の多結晶シリコン膜間の耐圧が
飛躍的に向上し、フローティングゲートに注入されたエ
レクトロンの保持特性が飛謂的に向上するなどの効果が
ある。[Effects of the Invention] As explained in detail above, according to the semiconductor device according to the present invention, when the first polycrystalline silicon layer is removed during self-aligned etching, the second polycrystalline silicon layer is removed. The amount of side etching of the silicon layer is reduced, improving writing efficiency. Further, after forming the second silicon oxide film,
The edges of the first polycrystalline silicon film are rounded, and the breakdown voltage between the first polycrystalline silicon film and the second polycrystalline silicon film is dramatically improved, and the retention characteristics of electrons injected into the floating gate are improved. It has the effect of dramatically improving performance.
第１図は従来の半導体装置を示す菫な製造工程別の断面
図、第２図はこの発明に係る半導体装置の一実施例を示
す主な製造工程別の断面図、第３゛・図は第２図のＰ濃
度依存性を示す図である。
（１）・・・・シリコン基板、Ｃ２）・・・・比較的厚
い酸化膜、（３）・・・・第１の酸化シリコンｉ、（４
）・・・・第１の多結晶シリコン膜、（５）・・・・第
２の酸化シリコン膜、（６）・・・・第２の多結晶シリ
コン膜、（７）・・・・第１の多結晶シリコン膜。
なお、図中、同一符号は同一または相当部分を示す。
代 理 人 葛 野 信 −第３
図
γ１４９峠１０シリコン Ｐ導度
手続補正書（自発）
２、発明の名称
半導体装置
３、補正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目２番３号名
称 （６０１）三菱電機株式会社代表者片山仁八部
４、代理人
５、補正の対象
明細書の発明の詳細な説明の欄
６、補正の内容
明細書第３頁第２行のｒ１０００λ」をｒ１２００Ａ」
と補正する。
以 上FIG. 1 is a cross-sectional view showing a conventional semiconductor device according to various manufacturing steps, FIG. 2 is a cross-sectional view showing an embodiment of a semiconductor device according to the present invention according to main manufacturing steps, and FIG. FIG. 3 is a diagram showing the P concentration dependence of FIG. 2; (1)...Silicon substrate, C2)...Relatively thick oxide film, (3)...First silicon oxide i, (4
)...first polycrystalline silicon film, (5)...second silicon oxide film, (6)...second polycrystalline silicon film, (7)...second 1 polycrystalline silicon film. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Makoto Kuzuno - 3rd
Figure γ149 Pass 10 Silicon P conductivity procedural amendment (voluntary) 2. Name of the invention Semiconductor device 3. Relationship with the case of the person making the amendment Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name ( 601) Mitsubishi Electric Co., Ltd. Representative Hitoshi Katayama 4, Agent 5, Detailed explanation of the invention column 6 of the specification to be amended, page 3, line 2 of the specification of the contents of the amendment, r1000λ'' to r1200A''
and correct it. that's all
Claims (1)
て、フローティングゲートを構成する多結晶シリコシ中
に添加する不純物濃度をＩ×１０″６の 以上に形成し
たことを特徴とする半導体装置。1. A semiconductor device such as a double-gate non-volatile memory device, characterized in that the impurity concentration added to polycrystalline silicon constituting a floating gate is I×10″6 or higher.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP702083A JPS59132170A (en) | 1983-01-17 | 1983-01-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP702083A JPS59132170A (en) | 1983-01-17 | 1983-01-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59132170A true JPS59132170A (en) | 1984-07-30 |
Family
ID=11654351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP702083A Pending JPS59132170A (en) | 1983-01-17 | 1983-01-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59132170A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61120472A (en) * | 1984-11-16 | 1986-06-07 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
-
1983
- 1983-01-17 JP JP702083A patent/JPS59132170A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61120472A (en) * | 1984-11-16 | 1986-06-07 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
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