JPS59128650A - High speed correcting circuit of byte error - Google Patents

Abstract

PURPOSE:To attain rapid decoding of a byte error correcting code and to correct rapidly the error by providing the titled circuit with a syndrome generating circuit and a decoding circuit finding out a byte position having an error by the syndrome. CONSTITUTION:Since syndrome registers S1, S2 are simultaneously shifted in parallel, the maximum number of shifting times necessary for the syndrome registers S1, S2 is equal to a larger one out of 2e1-1 and e2-1. When the registers S1, S2 coincide with a register So by the number of shifting times within 2e1-1 and e2-1 respectively, an error position is calculated by circuits 14, 15. Namely, the circuit 14 converts the number of shifting times stored in a counter 12 and the circuit 15 calculates the error position by the result obtained from the circuit 14. Thus, the rapid decoding of a byte error correcting code is attained and the error can be corrected rapidly by processing said decoding circuit.

Description

[Detailed description of the invention]

The present invention relates to a circuit for correcting single byte errors, and more particularly to a circuit for correcting errors at high speed. Fire codes are often used to improve the data reliability of file devices such as magnetic disk files.
A modified Fire code, which is a modified Sarawoko Fire code that enables high-speed decoding, is in use. However, as a recent trend, adjacent error correction codes (1'J, hereinafter referred to as byte error correction codes), which can encode data by byte-by-byte processing, are being used. However, the method of modifying a byte error correction code so that it can be decoded at high speed and its circuit configuration are well known. ?″1″1″ No. 6RI circuit is provided. The story correction circuit of the present invention uses a valid test matrix H. In a system that encodes data according to K+3
A circuit is provided for high-speed decoding of a single byte error occurring in a code block of bytes (K is the number of information bytes). Here, m is any even number iF, an integer and Lz7. = time, I
(j m >' m identity matrix, TI is G, (X) = Pl
(X!20) m X m companion matrix. However, p+M is an arbitrary irreducible polynomial of degree 100 and order el.T2 is an arbitrary irreducible polynomial G2(X
) is an m×m companion matrix of el and e2 are relatively prime, and the number of information bytes is given by = e1・e2,
A byte represents m bits. The error correction circuit of the present invention includes the first row of the parity check matrix Hct),
Syndrome 86 corresponding to the second and third rows, respectively. It consists of a syndrome generation circuit that generates St and G2, and a decoding circuit that determines the position of an erroneous byte from syndromes S 6 + 81 and G2. Syndrome S,, S□ and G2 generation circuit n,
It consists of a 1m-bit feedback shift register. In the case of the S1 generation circuit, there is a multiplication circuit of the matrix TI in the feedback loop, and in the case of the G2 generation circuit, there is a multiplication circuit of the matrix TI in the feedback loop.
The multiplication circuits of the burnt matrix T2 are respectively inserted. (86
A gJ arithmetic circuit of a degree matrix engineer is inserted into the generation circuit, but this is the same as not inserting anything). The decoding circuit is a syndrome shift and G2 generation circuit.
This circuit shifts the St and G2 registers by η until the contents of the registers match the contents of the syndrome So, and calculates the position of the erroneous byte based on the number of shifts. The characteristics of the error J1° positive circuit of the present invention are 1 in both equations (1).
1T parity matrix ■] r, Neuite error correction mark +! The point is to use f. Matrix I in matrix H, T1. T2Gs next (1)-i
4 Ria. . I: mXm matrix Tl: G, (X+ = P, 002a>-y companion matrix (mXm matrix). P! (3) is the order e1
is an irreducible multi-divertical formula. The period of otrX) is 2et, and it is more rp!
2el =='rlO= I T2 quadratic quadratic order 1st order Pe2 approximately polynomial G2 companion matrix (mXm matrix). Order e2 yon T2e2=
T2°=I K: Number of information bytes. Byteco m bit. Zhao (= et 4z where 01 (X
)= PsOO” == no+n+x+axx2+-
=−−−−=−・・+a,,,lx”−’ (aI=0
Also, t-s 1 > torque: l n ttnion matrix I
II, H Go ^. It is easily proven that the single companion matrix has the following properties. Vector E=(66dl-...
'm-5)''('' is a transpose symbol, and the polynomial corresponding to di=O or 1) is expressed as E(3)== (IQ+d, X+d,
2X+・・・・・・・・・+d□−xffl When property (al E(3) is divisible by P and prisoner (i.e. E QQ= Omod PH(X) no R), T I
” B+T t ' E=0 is ' jEO
Limited to model. However, Tll represents the i-th power of the mxm matrix T1, and TI'·E represents the product of the matrix T1' and the vector E modulo 2. Sex7fr+hFJ)Of+s P, (X) TeQ4Incutyn, r, c when <v'r, xwa% EDCIM n
mod P 1(X)θ), 't', tg-4-
'll'', 1 'E=n (''f, fruno<1 i
−j = Q moc12e1σ). Same FO(ko, irreducible many) 1']'1ltl''()2+X・
=h(, +h, x+b2x +・=-・・+b, n-1
x''-'(hI=n'y4:j1) Oyconhanin@-n matrix T2Tgo.Matrix T2hko1-1ml, Tekeji()) property noerh<addn.Property ( C) ri'2'E+'l"2'Fi==0tr
j6 (1) Gjj-jmi Q mod n only when C2
Ru. It is easily proven using the properties (a), (bl, and (e)) that the parity check matrix H has single-byte error correction capability.Detailed explanation of the present invention using the JLI drawings below 1 is a block diagram showing an encoder circuit (encoding circuit) conforming to the parity check matrix H. In FIG. .Circuit 4, 5 and 6 Gi + TE, J
n'c) (1) Exclusive OR (EXCLU8 I
VE-OR) circuit. Further, circuit 7 is a multiplication circuit for the matrix T1, and circuit 8 is a multiplication circuit for the matrix T2. K
(= es ・C2, '4 information hides E I)K
-11DK-2, T)X-s l --, Dt, no
If expressed as (Di Lt m-dimensional column vector), checkby+-C6HC1+02 (Cth 1m-dimensional column vector I) is generated by the following equation. ((-) T+ 'lT2'('json, zofl
, matrix 'r, , T20)! represents the power. )m1
Figure 0) In the circuit, data input 5k7i-intermediate 4゛ blue report high) DK-I J) + c-2, ---------,
Dt, T'). If input in this order, check bytes Co, C+bi C2 conforming to cutting allowance (2) will be generated. Here, Co,
The outputs of C1 and C21 registers 1, 2, and 3 are 6° before t'1. -X'
+X2+1, the companion matrix TI is expressed by the following formula. The input to the T1 multiplication circuit 7 is expressed as vector A=(aoa182
a3)' (where a1=0 or 1, t is the transposition symbol),
The output is vector B = Cbob + b2b3)'
(Here, %bl=0 or 1) and the output of the T1 multiplier circuit B cz B-T-A. In other words, it becomes C2. (Here, the number 10 in b2=a1+a3 is a power calculation modulo 2, that is, exclusive OR.)
FIG. 2 is a block diagram showing an example of a multiplication circuit based on Tri. In FIG. 2, the circuit 100 is a two-person exclusive OR
It is a circuit. Since the multiplication circuits using companion matrices Tl and T2 corresponding to general Gl(X) and (MX) are similarly configured, no further explanation is necessary. The encoder circuit shown in FIG. 1 is also used for syndrome generation. The received information bytes and check bytes are
-1, D knee 2. D,, -3,...,D;. Do, C2, C:, C; then syndrome So, 8
1. and S2 are generated by the following formula, and the margin below 1 (Kokote, 8 layers + DJ l c'e'3, zoi 1. m-dimensional column vector. Ti is mxm matrix.) Both formulas (
3) Generate a syndrome that follows Lj using the circuit shown in Figure 1 above. Reception M'fl information c'f) DK-1, TJK-2, --
, I) 2 , rt, , I) Of Input into the circuit of Fig. 1 in this order 7, check by one F, c 2, c, , c
≦ is input in this order T6o, but 1c≦ is controlled so that n is input only to register 1, CI'f register 2, and bow register 3, respectively. When the input of the received byte is completed, registers 1, 2, and 3) write both formulas (
3) n, 6 syndromes S 6 + 81 and S2 are output. Encoding (generation of check bytes) and generation of syndromes are performed as described above. Next, the i4Q circuit that decodes the pattern and position of the error byte from the syndrome is
, reveal. If an error of the error pattern 'Fli' (E + m-dimensional column vector) occurs in the first (okuj<K-1) byte, syndrome S occurs. , 81.82 are expressed by the following equations, and it is easily shown from both equations (21, (31). Here, only the syndromes So, S, and 82GIl are known, and the error pattern E and the error position are j is an unknown number. Decoding is to find the error pattern E and error position j from the known number 86.81 and S2. From Equation (4), since it matches the error pattern E (S), The error position j can be found as follows.In order to find the error position, in the circuit shown in Figure 1, the syndrome S, σ) register 2 syndrome S2)
Shift register 3 until it matches the output of register 1 of the n,zor12 syndrome So. However, during this shift f, the data input line is held at logic zero, and 8
Register 1 of 6 shifts and floats. S Lujista 2i6
and the output +-r of S2 register 3 is shifted 0), T+ 'S 1°T24S2 (shift,
81 and the initial #) of the contents of the S2C register. Already

[As stated above, since +p, 2et=1°T2e2=■, the number of large shift times for registers 2 and 3 are respectively il, 2el-1, and e2-1. Great talent! If the contents of 8 registers 2 are changed by 11 SO registers in the first shift, then 1■ From equation (4), 86=
T1 “5I=T1”Month F+=E(O<11<2e+
1) and 6° Therefore, @ property (a) and (bl
From, 11 + j= Omod e1 or LJ tt
+J = 0 "0d2er + In other words, n, b, 1.1 = -j mOd e! or A1 = -j mo
d 2e1(5) holds true T6゜ Both equations (5) (including r16 The two equations become a new number r
1 is introduced, n is unified into one equation as shown in equation (7) below. rI=-jmodel, (11<rl<e+ 1)(
Because of the force, both formulas (5) (Koke 611E-j mod
2e T and rl=t1 mod in both equations (6)
el is −j=a・2e+ +LH(a,
14 (j is the quotient and remainder when dividing −j by 2el, respectively) and t1=b−el+rl (b and rl are respectively ll';; the quotient and remainder when dividing by 6f) n
5. From this, -j=a-2e1+b-e1+r1=(2
This is because aI - b) eI + "l, and rt jmode is established. Similarly, if the contents of 82 register 3 match the So register at the r second shift σ), then from both equations (4) So= T2r2S2=T2r2+l E, =E. From the property (c) above, r2 + j=Q mod e2
, in other words, r2 = −j mod e2 , (o<r2<e
2-1) (8) holds true. To summarize the above. Here, r1/-r2jj is known and j is unknown.
There are some things you can do to easily solve the problem. −r7T, that is, 1゛II formula 00) 7j T j (
0(j < T(-1, K=e+-ez), calculated using the lowering formula, 6°J = K (A+r++Azrz) modx
fll) where (A+r++A2r2) modKfj
A+rl+A2r2 f=I Indicates the remainder when divided by . World, K=e】・ez, AI= a1e2. A2 =
a2e1oal and a2 are aI62+a2e1=1
mod x 02), and find it from . Formula (like the field, j is rl, r2 & showa.) The number AT r 1 + A - 2r 2 f which is 44% by multiplying and adding the n constants A1 and A2 is divided by K and the remainder when ivy is subtracted from K. (a) and (1) in FIG. 3 show the decoding θ) flowchart using the above principle. However, Fig. 3(a) and No. 31'Xl) are connected via destination/origin link number A. As shown in the figure, regarding the syndrome, 5O = 81 = 8
When it is 2-0, there is no error. If only one of S 6 + S 1 and S2 is non-zero (0), check byte c
For example, check 5oj0, 81-(1, 82 == O if 1 byte error is detected in o, C1 or co).
(Information byte and check byte C, ,C2ζ have 4f errors).Also, when two of So, S, ,S are non-zero (for example, 5o== Q, Sl〆0.S2〆0), it is determined that an uncorrectable error, that is, an error of 2 bytes or more has occurred.When So〆o, 5lpin and S2〆0, it is determined that an error has occurred in the information byte. The above-mentioned decoding procedure is executed, that is, the contents of the syndrome register S0 and the syndrome register S2 are shifted until they match the syndrome S. As shown in the flowchart of FIG.
The contents of register S1 do not match register So within 2e1-1 shifts, or the contents of register S2 do not match register S within ez-1 shifts. 4 seconds and f(
If not, it is determined that a burnt uncorrectable error, that is, an error of 2 bytes or more has occurred.In this case, in the flowchart of FIG. (This is what it looks like, but actually registers S1 and 82
(1) Shifts are performed simultaneously. FIG. 4 (This is a block diagram showing a decoding circuit that takes a practical look at the displacement principle above 1. In the figure, circuits 1, 2, and 3 are respectively

[Syndrome register SQ, 8I mentioned above]
And S2, circuits 7 and 8 are complicated, T, which I have already mentioned,...
This is a T2 multiplication circuit. In the figure, syndrome registers S and 82 are shifted simultaneously. The circuit I2 is a counter that counts the number of shifts of the syndrome register S1, and the circuit 13 is a counter that counts the number of shifts of the syndrome register S2. Circuits 10 and 11 are each a register S. and Sl and register So and 825
: Comparison circuit for comparison. When So and 81 match, the circuit 10 stops the counting operation of the counter 12 via the output signal line 20. Similarly, if So and 82 match, circuit 1
1 causes the counter 13 to stop counting via the output signal line 21. Therefore, the counter 12 holds the number of shifts tl required until Sl matches So (1), and the counter 13 holds the number of shifts r2 required until S2 matches SO. From the flowchart in FIG. 3, the number of shifts necessary for syndrome register 81ζ is at most 2e1-1 times, and the number of shifts required for syndrome 7 register S2 is at most e2-1 times.Syndrome registers Sl and 82 are Since they are shifted simultaneously and in parallel, the maximum number of shifts required for the syndrome register is equal to the larger of 2el-1 and ez-1.Even if the count value of counter 12 exceeds 2e1-1, Sl
o, or the count value of the counter 13 is e.
If S2 matches 8o+ even if it exceeds z-1, it is assumed that an uncorrectable error has occurred, and the error correction operation ends. Hey, I'm nervous n2e do' times, e
If the number of shifts is within l-1, the error position is calculated by the circuit 14 and the circuit 15. 2el-1) into the number of shifts r1 according to both equations (6).
Mr】4 is the remainder rl when input t1 is divided by el (O<
r+<6. -1) and outputs it. The circuit 15 calculates the number of shifts r1 and r2 (0×r2 <:,
el −1), the error position j according to both equations (11)
There are 6 circuits to calculate . That is, circuit 15gej =
This is a circuit that calculates K − (AHrl + A2r2 ) m□d K. Here, the comparison circuits 10 and 11 and the counters 12 and 13 are easily constructed using commercially available integrated circuits (ICs) in terms of hardware (
This can be done. Maf:, circuit 14 and circuit 15 can be realized by hardware (this can be expressed literally, but it can also be realized by firmware method.Many solid disk systems + RFFI adopt a microprogram control method (firmware method), so the circuit It is relatively easy to implement the computer systems 14 and 15 in firmware, and in this case, there is no need for the hardware circuitry required to implement circuits 14 and 15. As is clear, 2fi: In the winning circuit of the invention, G-1r, the maximum number of shifts of the syndrome register S1 is 2el-1 times, and the maximum number of shifts of the syndrome register S2 (goe2-1 times).Syndrome register S, and 32 are shifted at the same time, so the number of syndrome register shifts required for the error code is equal to the greater of 2el-1 and el-1.Therefore, the decoding time is the syndrome register a) shift time (2ex
-1 and el (the larger one) and calculation time ('j
= = equal to the sum of - (A4rl+A2rz) mod the time to calculate K). On the other hand, since the reverse normal method requires a number of shifts equal to the number of information bytes K (=el-62), the present invention can reduce the decoding time by 1C. In the following, the present invention will be explained in more detail using specific examples. G1(X), G2(X) as 4th order (m=4
), so byte-4 bits rm=4). Gl(X>: Gl(X'1=Pl(X)2=X"
+
X+1. Ga = 5 (J) irreducible polynomial. G, (X), G, Q t corresponding companion matrix (4 x 4 matrix) 5 - each, T, , T2, 4 x
The 4-unit matrix is expressed as follows: I, a, and stiffness. Here, the number of information bytes is equal to e1 and e2=15. Also, since the order e1=3, the period of T is 6 (=2e2), that is, T,' = T. Since the order e2=5, the period of T2 is 5, that is, T2'=I. Stiffness can be confirmed as follows. Regarding T, the following is true. Furthermore, regarding T2t, the following is true. If error pattern E occurs in the i-th information byte (here byte - 4 bits), the syndrome SO+81+
82 is expressed by the following formula. 86=E s1='r,'E S 2 "T2 ' R where ot<14. Decoding is performed according to the following steps 1 to 3. [Step 1] Syndrome register Sl and SzP shift and register 86] register S1 and 80C are the first time rOklIku2e1-1=5), and register S2 and 80 are the second time (0<C2<62-1 = 4) T!Sot
1. Suppose that they match. That is, 8g-=T1”St
, so "T2C282tv;a. [Step 2] r+= C1+ ) mod e1= (tt ) mod
3'E: Ask. [Step 3] Amusement level tf'ij =K (A+rt+A2r2)m
od x= 15- (10r++6r2)mocl+
Find s. Here, the constants A1=10 and A2=6 are determined as follows. The first two insertions, i.e. a+ e2:l mod
el. a2ex":] From mod e2, first find al and 32. (ale2) mode1= (5al) mods=
1 and (a2el)mode2=(3az)mods
=1, so al=2゜a2=2゜Therefore, AI=ale2
==2X5=10. Az=azet=2x3=6. Next, an example will be given of how the error position is actually determined using the above steps. [Example 1] Error pattern E = (101
1) Assume that '(t is the transposition symbol) has occurred. Here, the polynomial E (3) = X3 + X'' + 1 corresponding to the vector E is not divisible by P1 = X2 +
)j Omod P 1(X). syndrome 8
．． ．． 8. , S2 are as follows. Next, according to the Fl 11th step, it is determined that the closing position j = 14 is ice Mera n, /). [Non-step 1] Shown in Figure 5. From this T1, tl = 4, C2 = 1
[Step 2] rr= (Lt)rnod 3=] [Step 3] j = 15- (10X1+6X1) mod+5
=15-1=14 Next, error pattern g(x, is P!lX
) 〇 [Example 2] Error pattern E = (1001)' in the 7th information byte
Assume that this occurs. Here, E(m=x'+x=(X
+1)(X''+X+1)'=(X+1)P, prison, i.e. ChiE□(l30 mod P+(3).The syndrome is. Step 1) It is shown in Figure 6.From this, tt= 2.rz=3゜[Step 2] rx= (tl) mods=2 rStep 3] j=15- (10X2+6X3) mod+5=15-
From 8m7 and above, errors are correctly decoded and decoded by the present invention. It was shown that l'15. However, the advantage of the decoding circuit Q of the present invention is that a code with a shorter byte width is sufficient. For example, if we consider the case of bytes - 16 bits (m = 16),
The advantages of the present invention can be fully understood. As the generator polynomial G, (3), the next degree 16 (m=
16) is selected. (hoo: GIQG-P1%2=X16+X8+X'
+X2+ 1゜However, P+(X) has degree 8 and order e+
=51 irreducible polynomial P+(X)=X8+X' 1X3
+X+ 1゜G200: G2(X)=X” +X15
+X14+X13+X9+X8+Xfu+X'+X2+X
+1° However, Ga is an irreducible polynomial with order e2=257. Number of information bytes K: K=el-e2=13107/
q. Byte = 16 bits. Here, G! (3), the companion matrix corresponding to G2(X) (of order 1 is as follows: '0010000000000(+01 110001
000000000000! 10000100000
000000 □1oonoo1oooooooooo
o 1 In the case of this code, the error position j is determined by the following equation. j = to - (A, + rl + A, 2 r2) mod x
=ni-(fi682r+ +6426rz) mod
K However, K=13107. Here, constants A1 and A2 are determined as follows. AlA2 is Ax=ate2=257a, A2=a2e
l=51a2. Also, al, a2 is (257a1)
mods, +”1+ (51a2) mod25y=
1 '29 plus the number of legs, which is obtained by Yuk1) Rad's algorithm as follows. 257-
5X51) = 126X51-25X257° From this, (126X51.) mod2sy=1. 6th 82
=126゜Also, ((-25) x257)rmd5+=
(26×257) mods1-1. Therefore, since al=26° or more, AI=ale2=26X257=6682.
A2=azet=126X51=6426. Here, in the conventional decoding method, it is necessary to shift the syndrome register a number of times equal to the number of information bytes=13107. Therefore, if the decoding time of the conventional decoding method is Tl, then T=13107 shift times. On the other hand, in the decoding method of the present invention, the syndrome register F2
et 1 (=101) or ez-1 (=256)
All you have to do is shift the number of times equal to Noizuwa or the larger one. In other words, the required number of shifts is 256, which is 6.Therefore, the amount of cloth for the uninvented circuit is T2 and 'I'.
It is the time required for calculation of 2-256 shifts 116 + calculations open 16 + calculations. Since it is possible to execute the total W at a high speed using the software, it is possible to predict the time T2 of the item J according to the present invention to be much smaller than the conventional time T1 of the item V. As can be seen from the above, the byte error counting circuit of the present invention is capable of detecting errors at high speed, and the purpose of the invention is fully exploited to the extent of 60.

[Brief explanation of the drawing]

11th part 1 is a block south showing an encoding circuit of a 6-byte error correction code according to the present invention, a blower 4 diagram showing a circuit for multiplying the companion matrix T of Hatake 2, G-X4+X2,
Fig. 3 is a flowchart showing the i-cho method, Fig. 4 is the block 1' of the weighing circuit, and Fig. 5 and irises 6 are examples of the i-1 process. In the figure, ], 2.3 is a syndrome register, /
1, 5.6 are exclusive OR circuits, and 7, 8 are G+(
A circuit for multiplying the companion matrix 'r+ and H T2 between X) and G1, 100 (exclusive OR, circuit, 10; 11 is a comparison circuit for detecting a match; 14 is an output signal for input signal 1. rl to r1 = (1-1) mod
A circuit for converting according to el, 15 is the signal t1 and rl
The circuit calculates the location of the erroneous byte based on the . Representative patent attorney:, H f7 Shinoff Figure 2 Figure 7 3 Figure (α) Figure 3 (b)

Claims (1)

[Claims] Parity check matrix (where m is any even positive integer, IGet
m x m identity matrix, T+ Gl G+(X) =
p, (x-20) m X m companion matrix. P,
(XI is any irreducible polynomial of degree 11th?i&e+.T2 is any irreducible polynomial G2(
m of X) :/m companion matrix. el and e2 are disjoint from each other, and the number of information bytes is K (jK=e
, ·e In a system for encoding data according to two bytes (representing m bits), the received data byte force 1 to the parity check matrix Gl+@1 . Corresponding to the second and third rows, the syndrome S(i, 81 and 82.
After the generation of the syndrome, the second and third
a first counter that counts and holds the number of shifts until the content Sl of the second syndrome register matches the content So of the first syndrome register; a second counter for counting and holding the number of shifts required for dispersing the content S2 of the third syndrome register to the content SO of the tenth syndrome register; ) a circuit that calculates the location of the erroneous byte based on the number of shifts held in a counter; and a high-speed byte error correction circuit.