JPS59163650A - High-speed correcting circuit for byte error - Google Patents

Abstract

PURPOSE:To correct an error of a single byte and to decode it at a high speed by using a means which produces syndromes corresponding to the rows of a check matrix from the reception data byte and a means which counts the shifting frequencies until the coincidence of contents is obtained. CONSTITUTION:The 1st-3rd syndrome registers 1-3 are provided to an error correcting/coding circuit of a parity check matrix of an formula. Then the 1st- 3rd syndromes S0-S2 are generated in response to the 1st-3rd rows of the check matrix. Then the 2nd and 3rd registers 2 and 3 are sifted by means of circuits 7 and 8 which multiply matrices T1 and T2 of a decoding circuit. A counter 12 counts the frequencies of coincidence between the contents S1 of the register 2 and the contents of the register 1. In the same way, a counter 13 counts the frequencies of coincidence between the contents of registers 1 and 3. A counter circuit 15 calculates the byte position from output signals r1 and r2 of counters 12 and 13, and an error position (j) is delivered. Thus the error of a single byte is corrected at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for correcting single byte errors, and more particularly to a circuit for correcting errors at high speed.

Fire codes are often used to improve the data reliability of file devices such as magnetic disk files.
Furthermore, a modified fire code is used, which is a modified fire code that can be decoded at high speed.

(hereinafter referred to as a byte error correction code) came to be used. However, a method for modifying a byte error correction code so that it can be decoded at high speed and its circuit configuration have not been known so far.

Therefore, an object of the present invention is to provide a byte error correction code that can be decoded at high speed and a decoding circuit thereof.

The error prevention circuit of the present invention can be used in a system that encodes data according to a parity check matrix H.
A circuit is provided for quickly decoding a single byte error occurring in a code block where K is the number of information bytes. Here, when m is an arbitrary even positive integer, I is an mxm identity matrix, and - is m of an arbitrary irreducible polynomial 91(3) of degree m1 order el.
is an m X m companion matrix of an arbitrary irreducible polynomial 92oO of degree m1 and order e. el and el are relatively prime, and the number of information bytes is K.
= el 11 e2 is given. A byte represents m bits.

The error correction circuit of the present invention is arranged in the first and second rows of the parity check matrix H.
Shin corresponding to row and 3rd row respectively)” ROHM SO
, a syndrome generation circuit that generates Sl and Sl;
It consists of a decoding circuit that finds the position of the byte with an error from the syndromes So, S+, and Sl.

The generation circuits for the syndromes SO, S, and SZ each consist of an m-bit feedback shift register. In the case of the S1 generation circuit, a multiplication circuit of the matrix T1 is inserted in the feedback loop, and in the case of the s2 generation circuit, a multiplication circuit of the matrix T: is inserted. (Although a unit matrix processor multiplication circuit is inserted into the So generation circuit, this is the same as inserting nothing.) The decoding circuit determines whether the contents of the shift registers of the syndrome s1 and s2 generation circuits are the same as those of the syndrome So. This circuit shifts the S1 and SZ registers until they match the contents, and calculates the position of the erroneous byte based on the number of shifts.

A feature of the error correction circuit of the present invention is that it uses a byte error correction code expressed by the parity check matrix H of both equations (1).

The matrix ■+'r, , % in the matrix H is as follows.

(:'mxm matrix TI: 91 (companion matrix of Xi (tnXm matrix) 9t (Xi is an irreducible polynomial of degree m2 and order e1, gt
(The order of Xl is el, so Tt=Tt=I(.

T2: Order m9 order e! The irreducible polynomial 9*(companion matrix (rnxm matrix) of Xl.

14.

From the order e2, Tx=Tz=1. ) K: Number of information bytes. Byte 2m bits.

If el and 82 are relatively prime, then K = el・02kokote, 91(xl = ao+ aI X+αaX2+・
...+αrIX (α=0 or 1), the companion matrix T1 is. It is easily proven that the companion matrix n has the following properties. Vector E=(do
4...ζ-1) t (t is the transposition symbol, d, = O or 1
) corresponding to the polynomial E(Xl=c4+AX-1-c4
! ＋・・−・−・+dX、! - Then, the following property IJLI holds true.

Property t&l: THE+ZE=O is t-)
= Limited to Omod el.

Similarly, the companion matrix T2 of the irreducible polynomial 9Jt3 = bo + bs
! 'E +7',, 'E = 0 is i - jy
Qmod e Limited to times of laziness.

That the parity check matrix H has the ability to correct single-byte errors is easily proven using the properties fat, (bl.

The present invention will be described in detail below using the drawings.

FIG. 1 is a block diagram showing an encoder circuit (encoding circuit) conforming to the parity check matrix H. In FIG. 1, circuits 1, 2 and 3 are each m-bit registers. Circuits 4.5 and 6 are each m-bit EXCLUSIVE-OR circuits.

Further, circuit 7 is a multiplication circuit for the matrix T1, and circuit 8 is a multiplication circuit for the matrix 1.

K (=e11I82) information bytes as "%-I Dk
-! Expressed as Dk-s..., DI, Do (D is an m-dimensional column vector), check bytes co, Cs,
C! (C6 is an m-dimensional column vector) is generated by the following equation.

(Here, Tl", T: are 2 of the matrix T1.T, respectively.
represents the power. ) In the circuit shown in Figure 1, if the information bytes Dk-1t Dk-z+..., D□, Do are input in this order via the data input line, a check pie conforming to both equations (2) is obtained.
C0, C, and C! is generated. Here, C0, C1
and C3 are the outputs of registers 2 and 3, respectively.

The T1 multiplication circuit 7 and the -multiplication circuit 8 are configured as follows. For example, if 91(3) = Te + X2 + 1, the companion matrix Tl is given by the following formula, T1
The input to the multiplication circuit 7 is expressed as vector A=(α.α1a2α3
) (where α, = 0 or 1, t is the transpose symbol), and output the vector B = (bob, h, b, >t<where 6.
= 0 or 1), the output B of the T1 multiplier circuit is B = T-
It is represented by A. In other words, there is. ) Therefore, the multiplication circuit according to 'T11= is as shown in FIG.

In FIG. 2, circuit 100 is a two-person exclusive OR circuit.

General 9□(3), 9. (The multiplication circuit using the companion matrices T1 and T corresponding to XI is similarly configured, so no further explanation is necessary.

The encoder circuit of FIG. 1 is also used for syndrome generation. Generated from received information bytes and check formula.

le, T is an mxm matrix. ) To generate the syndrome according to both equations (3) using the circuit shown in FIG. do. After entering the received bytes,
From registers 1, 2, and 3, the syndrome S expressed by both equations (3). , S, and S2 are output, respectively.

Encoding (check byte generation) and syndrome generation are performed as described above.

Next, a decoding circuit for decoding the pattern and position of an erroneous sybyte from the syndrome will be explained.

Now, if an error of 9 patterns E (E is an m-dimensional column vector) occurs in the th (0th) degree < k-1) information byte, syndrome S occurs. , Sl, and S2 are easily shown by the following equations (2) and (31).

Here, syndrome S0. Only S, S, and S have already been mentioned, and the wrong turn (E) and the wrong position (E) are unknown. Decoding is performed using known number S0. The purpose is to find the erroneous shift pattern E and the erroneous shift position from Sl and S. From equation (4), the incorrect repattern E is S. Since it matches, E is S. more immediately required. The error position is found as follows: 0 To find the error position (=, in the circuit of FIG. 1, register 2 of syndrome 81 and register 3 of syndrome S2 are
Syndrome S respectively.

Shift until it matches the output of register 1.

However, in this shift, the data input line is held at logic zero, and register 1 of S0 is not shifted ~bSt register 2 and S! The output of register 3 is the first shift of the cup,
T181 and Tt St (however, Sl and S2 are the initial values of the register contents), respectively. As already mentioned, since +: T, -I, T,' = I, the maximum number of shifts for register 2 and register 3 is e
0 which is l-1 and e, -1 Now, the contents of 88 register 2 are So at the r1th shift.
If it matches register 1, So from both equations (4)
=< 5t-T4 +JE =E (O<7.<es
1). Therefore, the above property (τ1+ from al)w
Omod e1 In other words, ding--no゛ mod em...
...(5) holds true.

Similarly (2nd, r, if the contents of S register 3 match the 80th register at the 8th shift, then from both equations (4) S
o = T, 'S, = T, "E = E. The property (from bl, r, +) = 0, in other words mod e.

Then, r'a-mod e, , (O<rfie2-1
)...”・(6) Goose is established.To summarize the above, we get.

Here, rl and - are known, and n is an unknown quantity.

Both equations (7) are based on the Chinese remainder theorem.
RemalnderTh@orem)' can be easily solved.

In other words, the value that satisfies both equations (7) is -1゜k
=61''ez) is obtained by the following formula.

ノ = ni - (he r □ + he z). . dk・・・・・・
(8) Kokote, (he-, ten-he”!) m6d k indicates the remainder when r1+he- is divided by k.

However, = 61° @ P = 'l @ l = 6?1ゝ "1 and α
2 is αe + αzes” 1 mod k “””
(912 ′Ir: is a constant that increases. As shown in equation (8), rI
+ is equal to the remainder when T2 is divided by k, which is subtracted from k.

(!L) and (bl) in Figure 3 show a flowchart of decoding using the above principle.
Figure (bl is connected via the destination/return symbol A.

S regarding the syndrome as shown. =S1=S,=0
At 0:00, there is no error. So, S, and S! 1 in
If only the number is non-zero, check 2) It is determined that one byte in C0, C1 or co is incorrect.

For example, when S0≠o, s,=o, s,=o, there is an error in check byte C0 (information byte and check byte C, , C, has no error).

Also, when two of So, S, and S2 are non-zero (for example, when s0=o, S1≠O, S, ≠0), it is an uncorrectable error.

In other words, it is determined that an error of 2 or more bytes has occurred.

When S0≠O, S≠0 and S≠0, it is determined that an error has occurred in the information byte, and the above-described decoding procedure is executed.

The contents of syndrome register S and syndrome register S are syndrome register S0.
Shift until it matches.

However, as shown in the flowchart in Figure 3, if the contents of register S1 do not match register S0 within el-1 shifts, or if the contents of register S do not match register S0 within e,-1 shifts, If they do not match, it is an uncorrectable error;
In other words, it is determined that an error of 2 bytes or more has occurred. Here, in the flowchart of FIG. 3, it is written that the syndrome ψ register SP shift is started after the shift of the syndrome register S1 is completed, but in reality, the shifts of registers S1 and S are performed at the same time. Do it in two parallels.

FIG. 4 shows a decoding circuit that realizes the above decoding principle.

In the figure, circuits 1, 2 and 3 are respectively the syndrome registers S0. S, and 82 circuits 7 and 8 are the already mentioned T, , and T multiplication circuits, respectively. In the figure, syndrome registers S1 and S are shifted simultaneously. The circuit 12 is a counter that counts the number of shifts of the syndrome register S, and the circuit 13 is a counter that counts the number of shifts of the syndrome register S. Circuits 10 and 11 are each a register S. This is a comparison circuit that compares S and S and registers S0 and S.

When So and 81 match, the circuit 10 stops the counting operation of the counter 2 via the output signal line 20. Similarly, when S and S match, the circuit 11 stops the counting operation of the counter 3 via the output signal line 21. Therefore, the counter 2 holds the number of shifts r required until S matches S, and the counter 3 holds the number r of shifts required until S matches So.

Here, from the flowchart of FIG. 3, the maximum number of shifts required for the syndrome register S is el-1 times, and the maximum number of shifts required for the syndrome register S is e-1 times.

Since syndrome registers S1 and 82 are shifted simultaneously and in parallel, the maximum number of shifts required for the syndrome registers is equal to the greater of e-1 and e-1.

Even if the count value of counter 2 exceeds e r-1, Sl and 8
0 (if they do not match or the count value of counter 3 is 8)
, -1 but S does not match So, an uncorrectable ab has occurred, and the error correction operation ends.

If not, i.e. syndrome register S
! and S, is syndrome S. et-1 time each,
e, if the number of shifts within -1 matches, circuit 1
The error position is calculated by 5.

The circuit 15 calculates the number of shifts r1 and r! From, both formulas (8
) is a circuit that calculates the pb position no.

That is, the circuit 15 is a circuit that calculates τ mod k to = k - (A, r1+).

Here, the comparison circuits 10 and 11 and the counters 2 and 13 are available, but they can also be implemented using firmware. Since many magnetic disk drives employ a microprogram control method (firmware method), it is relatively easy to implement the calculation function of the circuit 15 using firmware.
In this case, there is an advantage that the hardware circuit required to realize the circuit 15 is not required.

As is clear from the above explanation, in the decoding circuit of the present invention, the maximum number of shifts of the syndrome register S1 is el.
−1 times, and the maximum number of shifts of the syndrome register S is e −1 times. Syndrome register S, and S,
are shifted simultaneously, so the number of syndrome register shifts required for decoding is equal to the larger of el-1 and e-1. Therefore, the decoding time is the syndrome register shift time (whichever is greater of e-1 and e-1)! Calculation time () = equal to the sum of - (r1 + x) time to calculate mod k).

On the other hand, in the normal decoding method, the number of information bytes k (= e k
) i2 Since a number of shifts equal to 2 is required, it is possible to considerably reduce the decoding time with the present invention.

As described above, the byte error correction circuit of the present invention can decode errors at high speed, and the object of the present invention can be fully achieved.

[Brief explanation of the drawing]

FIG. 1 shows a byte error correction/me code according to the present invention.
a-1, (bl is a flowchart showing the decoding method, 4th
The figure is a block diagram of a decoding circuit. In the figure, 1, 2.3 is syndrome register 4,
5.6 is an exclusive OR circuit, 7 and 8 are each glLxl
and g, a circuit for multiplying companion matrices T1 and 'r2 of 00, 100 is an exclusive OR circuit, 10, 11 are comparison circuits for detecting a match, 15 is an erroneous byte based on signals r and r, The circuits for calculating the position of are shown respectively. O 1 Roa 22 O 3 Figure (0,)

Claims (1)

[Claims] Parity check matrix (where m is an arbitrary positive integer, t is an m×m unit matrix. TI is an arbitrary irreducible polynomial r of degree m2 and order 61,
(x) mxm companion matrix, T2 is of order m9
Any irreducible polynomial of order 82! It is an mxm companion matrix of (X). However, Kame to e! are relatively prime, and the number of information bytes is k = e1·el. The first .pi of the check matrix. Syndrome S corresponding to the second and third rows
, , S, and S2, respectively.
After the syndrome generation is completed, the second and third syndrome registers are shifted, and the contents of the second syndrome register St
a first counter that counts and holds the number of shifts required until S0 matches the content S0 of the first syndrome register; A second function that counts and holds the number of shifts required to match the content So.
and a circuit for calculating the position of an erroneous byte based on the number of shifts held in the first and second counters.