JPH0351008B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for correcting single byte errors, and more particularly to a circuit for correcting errors at high speed.

In order to improve the data reliability of file devices such as magnetic disk files, Fire codes and modified Fire codes that are modified to enable high-speed decoding of Fire codes are often used. However, as a recent trend, b-adjacent error correction codes (hereinafter referred to as byte error correction codes) can encode data in byte-by-byte processing.
came to be used. However, a method for modifying a byte error correction code so that it can be decoded at high speed and its circuit configuration have not been known so far.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a byte error correction code that can be decoded at high speed and a decoding circuit thereof.

The story correction circuit of the present invention has a parity check matrix H, H=I I...I...II00 T ₁ ^K-1 T ₁ ^K-2 ...T ₁ ⁱ ...T ₀ ^o 0I0 T ₂ ^K-1 T ₂ ^{K- 2} …T ₂ ⁱ …T ₂ ^o 00I In a system that encodes data according to (1),
A circuit is provided for quickly decoding a single byte error occurring in a code block of K+3 bytes (K is the number of information bytes). Here, when m is an arbitrary even positive integer, I is an m×m identity matrix, and T ₁ is G ₁ (X)=P ₁
(X) is an m×m companion matrix of ² . However, P ₁
(X) is an arbitrary irreducible polynomial with degree m/2 and order e ₁ . T ₂ is any irreducible polynomial G ₂ of degree m and order e ₂
(X) is an m×m companion matrix of (X). e ₁ and e ₂
are relatively prime, the number of information bytes K is given by K=e ₁ ·e ₂ , and a byte represents m bits.

The error correction circuit of the present invention has the first error correction circuit of the parity check matrix H.
A syndrome generation circuit that generates syndromes S ₀ , S ₁ and S ₂ corresponding to the second and third rows, respectively, and a decoding circuit that determines the position of the erroneous byte from the syndromes S ₀ , S ₁ and S ₂ . It consists of The generation circuits for the syndromes S ₀ , S ₁ and S ₂ are each composed of m-bit feedback shift registers. In the case of the S ₁ generation circuit, there is a multiplication circuit for the matrix T ₁ in the feedback loop, and an S ₂
In the case of a generation circuit, a multiplication circuit of matrix T ₂ is inserted respectively. (Although a multiplication circuit for the unit matrix I is inserted into the S ₀ generation circuit, this is the same as not inserting anything.)

The decoding circuit shifts the registers of S ₁ and S ₂ , respectively, until the contents of the shift registers of the syndrome S ₁ and S ₂ generation circuit match the contents of syndrome S ₀ , and detects the erroneous bytes based on the respective shift circuits. This is a circuit that calculates position.

A feature of the error correction circuit of the present invention is that it uses a byte error correction code expressed by the parity check matrix H of the above equation (1).

The matrices I, T ₁ , and T ₂ in the matrix H are as follows.

I: m×m matrix T ₁ :G ₁ (X)=P ₁ (X) ² companion matrix (m×
m matrix). P ₁ (X) is an irreducible polynomial with degree m/2 and order e ₁ . The period of G ₁ (X) is 2e ₁ , and from this
T ₁ ^2e1 = T ₀ ^o = I T ₂ : Companion matrix (m×m matrix) of irreducible polynomial G ₂ (X) with degree m and order e ₂ . From order e ₂
T ₂ ^e2 = T ₂ ^o = I K: Number of information bytes. Byte = m bits. If e ₁ and e ₂ are mutually prime, then K = e ₁・e ₂ where G ₁ (X) = P ₁ (X) ² = a ₀ + a ₁ x + a ₂ x ² +...
+a _n-1 x ^m-1 (a _i = 0 or 1), the companion matrix T ₁ is It is. It is easily proven that the companion matrix T ₁ has the following properties. Vector E=(d ₀ d ₁ ...
d _n-1 ) ^t (t is the transpose symbol, d _i =0 or 1) is the polynomial corresponding to E(X) = d ₀ + d ₁ x + d ₂ x ² +...+
Assuming d _n-1 x ^m-1 , property (a) When E(X) is divisible by P ₁ (X) (that is, when E(X)≡0modP ₁ (X)), T ₁ ⁱ
E+T ₁ ^j E=0 is i−j≡0mode ₁
limited to the time of However, T ₁ ⁱ is an m×m matrix
It represents T ₁ to the i power, and T ₁ ⁱ ·E represents the product of matrix T ₁ ⁱ and vector E, modulo 2.

Property (b) When E(X) is not divisible by P ₁ (X) (that is, when E(X)≡0modP ₁ (X)),
T ₁ ⁱ E+T ₁ ^j E=0 when i−j≡
Limited to 0mod2e ₁ .

Similarly, the irreducible polynomial G ₂ (X) = b ₀ + b ₁ x + b ₂ x ² +
...+b _n-1 x ^m-1 (b _i = 0 or 1) companion matrix T ₂ is It is. The following properties of matrix T ₂ are known.

Property (c)T ₂ ⁱ E+T ₂ ^j E=0 if i−j≡
Limited to 0mod e ₂ .

That the parity check matrix H has a single-byte error correction capability is easily proven using the properties (a), (b), and (c).

The present invention will be explained in detail below using the drawings.

FIG. 1 is a block diagram showing an encoder circuit (encoding circuit) conforming to the parity check matrix H. In FIG. 1, circuits 1, 2 and 3 are each m-bit registers. Circuits 4, 5 and 6 each have an exclusive ^OR of m bits.
(EXCLUSIVE-OR) circuit. Also, circuit 7
is a multiplication circuit for the matrix T ₁ , and circuit 8 is a multiplication circuit for the matrix T _2.
This is a multiplication circuit. If K (=e ₁・e ₂ ) information bytes are expressed as D _K-1 , D _K-2 , D _K-3 , ..., D ₁ , D ₀ (D _i is an m-dimensional column vector), then Check bite C ₀ ,
C ₁ and C ₂ (C _i is an m-dimensional column vector) are generated using the following equation.

(Here, T ₁ ⁱ and T ₂ ⁱ are the i of matrices T ₁ and T ₂ , respectively.
represents the power. ) In the circuit of FIG. 1, the information bytes D _K-1 , D _K-2 , ..., D ₁ ,
If D ₀ is input in this order, check bytes C ₀ , C ₁ and C ₂ are generated according to the above equation (2). here,
C ₀ , C ₁ and C ₂ are registers 1, 2 and 3 respectively
This is the output of The T ₁ multiplication circuit 7 and the T ₂ multiplication circuit 8 are constructed as follows. For example, G ₁ (X)=
If X ⁴ +X ² +1, then the companion matrix
T ₁ is expressed by the following formula.

T ₁ = 0001 1000 0101 0010 T ₁ The input to the multiplier circuit 7 is vector A = (a ₀ , a ₁ ,
a ₂ , a ₃ ) ^t (where a _i = 0 or 1, t is the transpose symbol), and the output as vector B = (b ₀ , b ₁ , b ₂ , b ₃ ) ^t (where b _i = 0 or 1), the output B of the _T1 multiplier circuit is expressed as B=T·A. That is, b ₀ b ₁ b ₂ b ₃ =0001 1000 0101 0010 a ₀ a ₁ a ₂ a ₃ . From this formula, b ₀ = a ₃ , b ₁ = a ₀ , b ₂ = a ₁ +
a ₃ , b ₃ = a ₂ . (Here, the symbol + in b ₂ = a ₁ + a ₃ is an addition modulo 2, or exclusive OR.) FIG. 2 is a block diagram showing an example of a multiplication circuit using T ₁ . In FIG. 2, circuit 100 is a two-input exclusive OR circuit. General G ₁ (X), G ₂ (X)
Since the multiplication circuits using the companion matrices T ₁ and T ₂ corresponding to T 1 and T 2 are similarly configured, no further explanation is necessary. The encoder circuit of FIG. 1 is also used for syndrome generation. The received information bytes and check bytes are denoted as D′ _K-1 , D′ _K-2 , D′ _K-3 ,
..., D′ ₁ , D′ ₀ , C′ ₀ , C′ ₁ , C′ ₂ , syndromes S ₀ , S ₁ , and S ₂ are generated by the following equations.

(Here, S _i , D′ _j , and C′ _e are each m-dimensional matrix vectors. _{T i} is an m×m matrix.) A syndrome according to the previous equation (3) is generated using the circuit shown in Figure 1 above. To do this, the received information bytes D′ _K-1 , D′ _K-2 , ..., D′ ₂ ,
D' ₁ and D' ₀ are input in this order to the circuit of FIG. 1, and then check bytes C' ₀ , C' ₁ and C' ₂ are input in this order. However, C' ₀ is controlled to be input only to register 1, C' ₁ to only register 2, and C' ₂ to only register 3. When the input of the received byte is completed, syndromes S ₀ , S 1 and S 2 expressed by the above equation (3) are output from registers 1, ₂ and _3, respectively. Encoding (generation of check bytes) and generation of syndromes are performed as described above. Next, a decoding circuit for decoding the pattern and position of an error byte from the syndrome will be described.

Now, if an error of error pattern E (E is an m-dimensional column vector) occurs in the j-th (0jK-1) information byte, the syndromes S ₀ , S ₁ , and S ₂ can be expressed by the following equations. This can be easily demonstrated from (2) and (3) above.

S ₀ = E S ₁ = T ₁ ^j E S ₂ = T ₂ ^j E (4) Here, only the syndromes S ₀ , S ₁ and S ₂ are known, and the error pattern E and error position j are unknown. . Decoding involves finding the error pattern E and error position j from the known numbers S ₀ , S ₁ and S ₂ . Since error pattern E matches S ₀ from equation (4), E can be immediately obtained from S ₀ . The error position j is determined as follows. To find the error location, register 2 of syndrome S ₁ and register 3 of syndrome S ₂ are shifted in the circuit of FIG. 1 until they respectively match the output of register 1 of syndrome S ₀ . However, in this shift, the data input line is held at logic zero, and register 1 of S ₀ is not shifted. The outputs of _S1 register 2 and _S2 register 3 are l
At the second shift, T ₁ ^l S ₁ and T ₂ ^l S ₂ (however, S ₁
and S ₂ is the initial value of the contents of the register). As mentioned above, since T ₁ ^2e1 = I and T ₂ ^e2 = I, the maximum number of shifts for register 2 and register 3 is
2e ₁ -1 and e ₂ -1, respectively.

Now, the contents of S ₁ register 2 are changed by l _1st shift.
If it matches S ₀ register 1, then from the previous equation (4), S ₀ =
T ₁ ^l1 S ₁ =T ₁ ^l1+j E=E(0l ₁ 2e ₁ -1).
Therefore, from the above properties (a) and (b), l ₁ +j≡
0mod e ₁ or l ₁ +j≡0mod 2e ₁ , in other words, l ₁ =−jmod e ₁ or l ₁ =−jmod 2e ₁ (5) holds true.

The two equations included in the above (5) are r ₁ ≡l ₁ mod e ₁ (however, 0r ₁ e ₁ -1, _{0l 1} 2e ₁ -1) (6) If we introduce a new number r ₁ , the following equation becomes It is unified into one formula as shown in (7).

r ₁ ≡−jmod e ₁ , (0r ₁ e ₁ −1) (7) Because l ₁ ≡jmod2e ₁ in the previous equation (5) and the above (6)
r ₁ ≡l ₁ mod e ₁ in -j=a・2e ₁
+l ₁ (-a, l ₁ are the quotient and remainder when -j is divided by 2e _1, respectively) and l ₁ = b・e ₁ + r ₁ (B, r ₁ are respectively
It is expressed as the quotient and remainder when l ₁ is divided by e ₁ ,
From this -j=a・2e ₁ +b・e ₁ +r ₁ = (2a+b)
This is because e ₁ + r ₁ and r ₁ − jmod e ₁ holds true.

Similarly, if the contents of _{S 2 register} 3 match S ₀ register 1 in the second shift of r, then from the previous equation (4), S ₀ = T ₂ ^r2 S ₂ = T ₂ ^r2+j E = E. . From the above property (c), r ₂ +j≡0mod e ₂ , in other words, r ₂ ≡−jmod e ₂ , (0r ₂ e ₂ −1) (8) holds true. To summarize the above, r ₁ ≡−jmod e ₁ (however, r ₁ ≡l ₁ mod e ₁ ) r ₂ =−jmod e ₂ (10).

Here, r ₁ and r ₂ are known, and j is unknown. (10) above is “Chinese Remainder Theorem”
It can be easily solved by ``Remainder Theorem''.

That is, j(0jK−1,
K=e ₁ ·e ₂ ) is obtained by the following formula.

j=K-(A ₁ r ₁ + A ₂ r ₂ ) mod _K (11) Here, (A ₁ r ₁ + A ₂ r ₂ ) mod _K is the remainder when A ₁ r ₁ + A ₂ r ₂ is divided by K. shows. However, K=e ₁・e ₂ , A ₁ =
a ₁ e ₂ , A ₂ = a ₂ e _1p a ₁ and a ₂ are constants that satisfy a ₁ e ₂ + a ₂ e ₁ ≡1mod _K (12), a ₁ e ₂ ≡1mod e ₁ a ₂ e ₁ ≡ 1mod e ₂ (13). As shown in equation (10), j is the number obtained by multiplying r ₁ and r ₂ by constants A ₁ and A ₂ , respectively, and adding them.
It is equal to the remainder when A ₁ r ₁ + A ₂ r ₂ is divided by K and the remainder is subtracted from K.

Figures 3a and 3b show a flowchart of decoding using the above principle. However, FIG. 3a and FIG. 3b are connected via a destination/return symbol A.
As shown in the figure, for the syndrome, S ₀ = S ₁ = S ₂
When = 0, there is no error. If only one of S ₀ , S ₁ and S ₂ is non-zero, check bytes C ₀ , C ₁
Or it is determined that there is a 1-byte error in C ₀ . for example
Check byte when S ₀ ≠ 0, S ₂ = 0, S ₂ = 0
There is an error in C ₀ (there is no error in the information byte and check bytes C ₁ and C ₂ ).

In addition, when two of S ₀ , S ₁ , and S ₂ are nonzero (for example, when S ₀ = 0, S ₁ ≠ 0, and S ₂ ≠), it is an uncorrectable error, that is, an error of 2 or more bytes. It is determined that this has occurred.

When S ₀ ≠0, S ₁ ≠0 and S ₂ ≠0, it is determined that an error has occurred in the information byte, and the above-described decoding procedure is executed. That is, the syndrome register S ₁
and shift the contents of syndrome register _S2 until it matches syndrome _S0 . However, as shown in the flow in Figure 3, the contents of register S ₁ are 2e ₁ -1
If the shift does not match register S ₀ within times,
or an uncorrectable error if the contents of register S ₂ do not match register S ₀ within a shift of e ₂ −1;
In other words, it is determined that an error of 2 bytes or more has occurred. Here, in the flowchart in Figure 3, it is written that the shift of syndrome register S ₂ is started after the shift of syndrome register S ₁ is completed, but in reality, the shift of registers S ₁ and S ₂ is started. Do it in parallel at the same time.

FIG. 4 is a block diagram showing a decoding circuit that realizes the above decoding principle. In the figure, circuits 1, 2 and 3 are the previously mentioned syndrome registers S ₀ , S ₁ and S ₂ respectively, and circuits 7 and 8 are the previously mentioned T ₁ and T ₂ multiplication circuits, respectively. In the figure, syndrome registers S ₁ and S ₂ are shifted simultaneously.
The circuit 12 is a counter that counts the number of shifts of the syndrome register _S1 , and the circuit 13 is a counter that counts the number of shifts of the syndrome register _S2 . Circuits 10 and 11 are each a register
This is a comparison circuit that compares S ₀ and S ₁ and registers S ₀ and S ₂ . When S ₀ and S ₁ match, the circuit 10 stops the counting operation of the counter 12 via the output signal line 20. Similarly, when S ₀ and S ₂ match, the circuit 11 stops the counting operation of the counter 13 via the output signal line 21. Therefore, the counter 12 holds the number of shifts l ₁ required until S ₁ matches S ₀ , and the counter 13 holds the number of shifts r ₂ required until S ₂ matches S ₀ . . Here, from the flowchart in FIG. 3, the number of shifts required for syndrome register S ₁ is at most 2e ₁ -1 times, and the number of shifts required for syndrome register S ₂ is at most e ₂ -1.
times.

Since the syndrome registers S ₁ and S ₂ are shifted simultaneously and in parallel, the maximum number of shifts required for the syndrome registers is equal to the greater of 2e ₁ -1 and e ₁ -1.

Even if the count value of counter 12 exceeds 2e ₁ -1, S ₁
If does not match _S0 , or if _S2 does not match _S0 even if the count value of the counter 13 exceeds _e2-1 , it is assumed that an uncorrectable error has occurred, and the error correction operation ends. If not, i.e. syndromes S ₁ and S ₂ become syndrome S ₀ , respectively
If there is a match within the number of shifts within 2e ₁ -1 times and e ₂ -1 times, the error position is calculated by circuits 14 and 15.

The circuit 14 is a circuit that converts the number of shifts l ₁ (0l ₁ 2e ₁ -1) held in the counter 12 into the number of shifts r ₁ according to the above equation (6). In other words _{, the circuit 14 receives the remainder r 1 ( 0r 1}
This is a circuit that calculates and outputs e ₁ -1). circuit 15
is a circuit that calculates the error position j from the number of shifts r ₁ and r ₂ (0r ₂ e ₂ -1) according to the above equation (11). That is, the circuit 15 has j=K−(A ₁ r ₁ +
A ₂ r ₂ ) This is a circuit that calculates mod _K.

Here, the comparison circuits 10 and 11 and the counters 12 and 13 can be easily implemented in terms of hardware using commercially available integrated circuits (ICs). Furthermore, although the circuit 14 and the circuit 15 can be realized by hardware, they can also be realized by firmware. Since many magnetic disk devices employ a microprogram control method (firmware method), the circuit 14
It is relatively easy to implement the calculation functions of circuits 14 and 15 in firmware, and in this case, circuits 14, 1
There is an advantage that the hardware circuit required to realize 5 is not required.

As is clear from the above description, in the decoding circuit of the present invention, the maximum number of shifts of the syndrome register S ₁ is 2e ₁ -1 times, and the maximum number of shifts of the syndrome register S ₂ is e ₂ -1 times. Since syndrome registers S ₁ and S ₂ are shifted simultaneously, the number of syndrome register shifts required for decoding is
Equal to the greater of 2e ₁ -1 and e ₂ -1.
Therefore, the decoding time is the shift time of the syndrome register (the larger of 2e ₁ - 1 and e ₂ ) and the calculation time (time to calculate j = K - (A ₁ r ₁ + A ₂ r ₂ ) mod _K ) is equal to the sum of On the other hand, since the normal decoding method requires a number of shifts equal to the number of information bytes K (=e ₁ ·e ₂ ), the present invention can considerably shorten the decoding time.

In the following, the present invention will be explained in more detail using specific examples. As G ₁ (X) and G ₂ (X), the fourth order (m
=4) is used. Therefore, byte=4 bits (m=4).

G ₁ (X): G ₁ (X) = P ₁ (X) ² = X ⁴ +X ² +1. However, P ₁ (X)=X ² +X +1 is an irreducible polynomial with order e ₁ =3.

G ₂ (X): G ₂ (X) = X ⁴ +X ³ +X ² +X+1 _p G ₂ (X)
is an irreducible polynomial of order e ₂ =5.

Let T ₁ and T ₂ be the companion matrices (4×4 matrices) corresponding to G ₁ (X) and G ₂ (X), respectively, and let I be the 4×4 identity matrix, and these can be expressed as follows.

I=1000 0100 0010 0001, T ₁ =0001 1000 0101 0010, T ₂ =0001 1001 0101 0011 Here, the number of information bytes K is K=e ₁ ·e ₂ =15. Also, from the order e ₁ = 3, the period of T ₁ is 6 (= 2e ₂ ),
That is, T ₁ ⁶ =I. Since the order e ₂ =5, the period of T ₂ is 5, that is, T ₂ ⁵ =I. These can be confirmed as follows.

Regarding T ₁ , it is as follows.

T ₁ ＝0001 1000 0101 0010 T ₁ ² ＝0010 0001 1010 ₀₁₀₁ T ₁ ³ ＝0101 0010 0100 1010 T 1 4 ＝1010 0101 1000 0100 ^T ₁ ⁵ ＝0100 1010 0001 1000 T ₁ ⁶ = I = 1000 0100 0010 0001 Furthermore Regarding T ₂ , it is as follows.

T ₂ ＝0001 1001 0101 0011 T ₂ ² ＝0011 0010 1010 0110 T ₂ ³ ＝0110 0101 0100 1100 T ₂ ⁴ ＝1100 1010 1001 1000 T ₂ ⁵ ＝I＝1000 0100 001 0 0001 i-th information byte (here byte = 4 bits)
If error pattern E occurs in
S ₀ , S ₁ , and S ₂ are expressed by the following equations.

S ₀ =E S ₁ =T ₁ ⁱ E S ₂ =T ₂ ⁱ E where 0i14.

Decoding is performed according to the following steps 1-3.

[Step 1] Shift syndrome registers _S1 and _S2 and compare with register _S0 . Assume that registers S ₁ and S ₀ match at the _first time (0l ₁ 2e ₁ -1=5), and registers S ₂ and S ₀ match at _{the second} time (0r ₂ e ₂ -1=4). That is, S ₀ =T ₁ ^l1 S ₁ and S ₀ =T ₂ ^r2 S ₂ .

[Step 2] Find r ₁ = (l ₁ ) mod e ₁ = (l ₁ ) mod ₃ .

[Step 3] Find the error position j = K - (A ₁ r ₁ + A ₂ r ₂ ) mod _K = 15 - (10 r ₁ + 6 r ₂ ) mod ₁₅ .

Here, the constants A ₁ =10 and A ₂ =6 are determined as follows. The previous equation (13), that is, a ₁ e ₂ ≡1mod
First, find a ₁ and a ₂ from e ₁ , a ₂ e ₁ ≡1mod e ₂ .

(a ₁ e ₂ )mod e ₁ = (5a ₁ )mod ₃ = 1 and (a ₂ e ₁ )mod e ₂ = (3a ₂ )mod ₅ = 1, so a ₁ = 2, a ₂ =
2. Therefore, A ₁ =a ₁ e ₂ =2×5=10, A ₂ =a ₂ e ₁
=2×3=6.

Next, an example will be given of how the error position is actually determined using the above steps.

[Example 1] Error pattern E = (1011) in the 14th information byte
Suppose that ^t (t is the transpose symbol) occurs. Here, polynomial E(X) corresponding to vector E=X ³ +X ² +
1 is not divisible by P ₁ (X)=X ² +X+1. That is, E(X)/≡0modP ₁ (X). The syndromes S ₀ , S ₁ , and S ₂ are as follows.

S ₀ =E=1 0 1 1 S ₁ =T ₁ ¹⁴ E=T ₁ ² E=0010 0001 1010 0101 1 0 1 1=1 1 01 S ₂ =T ₂ ¹⁴ E=T ₂ ⁴ E=1100 1010 1001 1000 1 0 1 1=1 0 0 1 Next, it will be shown that the error position j=14 is found according to the above steps.

[Step 1] Shown in Figure 5. From this, l ₁ = 4, r ₂ = 1 [Step 2] r ₁ = (l ₁ ) mod ₃ = 1 [Step 3] j = 15 - (10 × 1 + 6 × 1) mod ₁₅ = 15 - 1 = 14 Next, a case where the error pattern E(X) is divisible by P ₁ (X) will be exemplified.

[Example 2] Error pattern E = (1001) in the 7th information byte
Suppose that ^t has occurred. Here, E(X)=X ³ +1
=(X+1)( _X2 +X+1)=(X+1) _P1 (X),
That is, E(X)≡0modP ₁ (X). The syndrome is S ₀ = E = 1 0 0 1 S ₁ = T ₁ ⁷ E = T ₁ ¹ E = 0001 1000 0101 0010 1 0 0 1 = 1 1 1 1 S ₂ = T ₂ ⁷ E = T ₂ ² E = 0011 0010 1010 0110 1 0 0 1=1 0 1 0.

[Step 1] Shown in Figure 6. From this, l ₁ = 2, r ₂ = 3.

[Step 2] r ₁ = (l ₁ ) mod ₃ = 2 [Step 3] j = 15 - (10 x 2 + 6 x 3) mod 15 = ₁₅ - 8 =
7 From the above, it has been shown that errors can be correctly decoded by the present invention.

However, the advantages of the decoding circuit of the present invention cannot be fully appreciated with such short byte-width codes. The decoding circuit of the present invention has a long byte width (where the byte width is m in byte=m bits).
is the value of ). for example,
Considering the case where byte = 16 bits (m = 16),
The advantages of the present invention can be fully understood. _{The following} order 16 (m
= 16).

G ₁ (X): G ₁ (X) = P ₁ (X) ² = X ¹⁶ +X ⁸ +X ⁶ +X ²
+1. However, P ₁ (X) has order 8 and order e ₁ = 51
The irreducible polynomial of P ₁ (X) = X ⁸ +X ⁴ +X ³ +X+
1.

G ₂ (X): G ₂ (X) = X ¹⁶ +X ¹⁵ +X ¹⁴ +X ¹³ +X ⁹ +
X ⁸ +X ⁷ +X ³ +X ² +X+1. However, G ₂ (X)
is an irreducible polynomial of order e ₂ = 257.

Number of information bytes K: K= _e1・_e2 =13107 bytes. However, byte = 16 bits.

Here, companion matrices corresponding to G ₁ (X) and G ₂ (X) are as follows.

In the case of this code, the error position j is determined by the following equation.

j=K−(A ₁ r ₁ +A ₂ r ₂ )mod _K =K−(6682r ₁ +
6426r ₂ ) mod _K However, K=13107.

Here, the constants A ₁ and A ₂ are determined as follows. A ₁ A ₂ is A ₁ = a ₁ e ₂ = 257a, A ₂ = a ₂ e ₁ = 51a ₂
It is. Also, a ₁ and a ₂ are (257a ₁ ) mod ₅₁ = 1,
(51a ₂ ) is an integer that satisfies mod ₂₅₇ = 1, and can be obtained by Euclid's algorithm as follows.

257=5×51+2, 51=25×2+1, from this 1=51−2×25=51−25×(257−5×51)=126×
51−25×257. From this, (126×51) mod ₂₅₇ =
1, so a ₂ = 126. Also, ((-25) x 257) mod ₅₁
= (26 x 257) mod ₅₁ = 1, so a ₁ = 26.

From the above, A ₁ = a ₁ e ₂ = 26 x 257 = 6682, A ₂ =
a ₂ e ₁ = 126 x 51 = 6426.

Here, in the conventional decoding method, it is necessary to shift the syndrome register a number of times equal to the number of information bytes K=13107. Therefore, if the decoding time of the conventional decoding method is T ₁ , then T ₁ =13107 shift times.

On the other hand, in the decoding method of the present invention, it is sufficient to shift the syndrome register a number of times equal to the larger of 2e ₁ -1 (=101) or e ₂ -1 (=256). In other words, the required number of shifts is 256.
Therefore, if the decoding time of the decoding circuit of the present invention is _T2 , then _T2 =256 shift time+calculation time. Here, the calculation time is j = K - (6682r ₁ + 6426r ₂ ) mod _K
This is the time required to calculate . This calculation can be performed at high speed by using software, so
It is possible to make the decoding time T ₂ according to the invention considerably smaller than the conventional decoding time T ₁ .

As described above, the byte error correction circuit of the present invention is capable of decoding errors at high speed, and the object of the present invention can be fully achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a coding circuit for a byte error correction code according to the present invention, and FIG.
A block diagram showing a circuit for multiplying the companion matrix T of X ^{4 +} FIG. 6 is a diagram showing an example of a decoding process. In the figure, 1, 2, and 3 are syndrome registers, 4, 5, and 6 are exclusive OR circuits, and 7 and 8 are companion matrices of G ₁ (X) and G ₁ (X), respectively.
A circuit for multiplying T ₁ and T ₂ , 100 is an exclusive OR circuit, 10 and 11 are comparison circuits for detecting a match, 14 is an input signal l ₁ to an output signal r ₁ , r ₁ = (l ₁ )
A circuit for converting according to mod e ₁ , 15 respectively subtracts a circuit for calculating the position of the erroneous byte on the basis of the signals l ₁ and r ₁ .

Claims (1)

[Claims] 1 Parity check matrix I I I...I...I I00 T ₁ ^K-1 T ₁ ^{K-2 T} ₁ ^K-3 ...T ₁ ⁱ ...T ₁ ⁰ 0I0 T ₂ ^K-1 T ₂ ^{K -2} T ₂ ^K-3 ...T ₂ ⁱ ...T ₂ ⁰ 00I (Here, if m is any even positive integer,
I is m × 1 identity matrix, T ₁ is m of G ₁ (X) = P ₁ (X) ²
×m companion matrix. P ₁ (X) is an arbitrary irreducible polynomial with degree m/2 and order e ₁ . T ₂ is of order m,
m×m companion matrix of any irreducible polynomial G ₂ (X) of order e ₂ . e ₁ and e ₂ are relatively prime, and the number of information bytes K is K=e ₁ ·e _2p . A byte represents m bits. )
In a system that encodes data according to
From the received data bytes, the first and second parity check matrix
and the syndromes S ₀ , S ₁ and S ₂ corresponding to the third row
and shift the second and third syndrome registers after the generation of the syndrome respectively, so that the content _S1 of the second syndrome register becomes the a first counter that counts and holds the number of shifts required until the content _S2 of the third syndrome register matches the content _S0 of the first syndrome register; a second counter that counts and holds the number of shifts required to match the content S ₀ ; and a circuit that calculates the position of the erroneous byte based on the number of shifts held in the first and second counters. A high-speed byte error correction circuit consisting of.