JPH0429414A - Step-by-step type coding of cyclic code and decoder - Google Patents

Abstract

PURPOSE: To accurately decode all received words by performing cycle shifts and calculation on each received work step by step. CONSTITUTION: A decoder is composed of an n-symbol shift register buffer 110a which reads and temporarily stores received words r(x), a syndrome value computing circuit 111 which obtains a decision vector H deg. by calculating S1 (x),i=m1 , m2 ,..., mp , a vector value comparator 112 which obtains a decision vector H<j> by calculating S1 <(1)> (X)+α<p> and i=m1 , m2 ,..., mp , a shift control circuit 113 which forcibly executes a shift when the output becomes '1', and an error number and positions deciding circuit 114 which detects the position and number of errors when the output becomes '1'. Therefore, all decision sets ϕv can be detects for an error correcting cyclic code even when the code has a different correcting ability (t).

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a decoding method for detecting and correcting errors that occur during data transmission or storage, and a decoder using the decoding method, and particularly to a cyclic The present invention relates to a step-by-step decoding method based on a code and a decoder configured using the decoding method as a decoding circuit for error correction.

[Conventional technology]

In the prior art, error detection and error correction codes (
The application of error-correcting codes (hereinafter abbreviated as error-correcting codes) is well known, and a typical error-correcting code is a cyclic code.

This cyclic code includes a BCH (Bos e Chaudhu) suitable for random error correction.
r i-Hocquenghem) code, non-binary BC
There was an H code, and an R3 (Reed Solomon) code suitable for byte error correction.

Therefore, to explain the general characteristics of cyclic codes, the Galois domain (Galois field) for any one work is
The following was known about the cyclic code in which the code length is n in s Field) GF (q).

<a> One received word to obtain the corresponding syndrome value by cyclic shift is r (X)"ro +r+ X +r2X' 10...
10rn-+ x"-' ・・・・・・(1)
where rl is one coefficient included in the Galois field GF (q), that is, r1 day GF (q'), j=o.

l, 2. ..., n-1. And let q' be one coefficient of q. For example, in the RS code, q=q',
(11,6,5) volley code (G.

1ay), q'=3 and q=36.

From the polynomial r(x) of this received word, the Galois field GF(q)
Some syndrome values belonging to Sl+1 ”m 1
＋m! +...2m (integer) can be obtained.

Here, whether the syndrome value S can be expressed as a polynomial %(2) having the same form as the polynomial r(x), or the number of terms thereof varies depending on the difference in the Galois field GF (q'). For example, for a binary cyclic code with q=23, St (x)=Sio+Si+x+...+ S +
, m −+ X m −+ ・・・・・・(3
), and its coefficient S,. +Si++ ...+31
．． All m-1 belongs to the Galois domain GF (2).

Therefore, by the definition of the cyclic code, the polynomial r
When (x) is cyclically shifted by one digit to the right, r ” (X) ”ra-r +rs-,,xi 10++++ r s-+ X '-' + r o X
'10r IX ''+... + r *-r-i X ''-' ・・・・・・
(4) can be obtained, and this r L I l (
The corresponding syndrome value obtained by cyclically shifting the initial syndrome value by one digit from
! +...+, ITL...(5).

<b> In a binary cyclic code, β = l. If β is Galois domain GF (Q”) = (O, l.

α1 α2 ..., α@-2), the corresponding syndrome value of r I I l (X ) + β is Sl cJl (x) + β+ 1 = ml m2
.

・・・1m, ・・・・・・(6) Here, α is the primordial light in the Galois field GF (q'). However, regarding the binary cyclic code,
Since each coefficient ro+r++...1 r,, -1 belongs to the Galois domain GF (2), β is always 1.

In the error correcting cyclic code, when the number of errors is less than t or 1, the relationship characteristics between each syndrome value differ depending on the number of errors. For example, for a double error correctorality two-dimensional BCH code (t = 2), which is a type of cyclic code, the relational characteristics between the syndrome values that differ depending on the number of errors are as follows.When the number of errors is 0, ,Sl=S2=0;S,
−r(α).

S3 = r (α3) When the number of errors is 1, S, ≠ 0: (St) ' +31z = Q When the number of errors is 2, S, ≠ 0: (Sl)'' 10Ss≠0...・It was (7).

[Problem to be solved by the invention]

However, in a conventional error-correcting decoding method using a cyclic code such as a BCH code and a decoder based on the decoding method, it is necessary to increase the decoding speed due to the demand for faster data processing speed as the amount of data increases. The circuit configuration was extremely complex. Therefore, since it requires an extremely complex circuit configuration, decoders that apply the multiple error correcting cyclic code decoding method have not yet been put into practical use, except for those with extremely slow decoding speeds. Ta.

The present invention was made based on the above-mentioned circumstances, and by adopting a step-by-step decoding method that is simple and easy to implement in an error correcting cyclic code with a correction ability of t, This paper provides a step-by-step decoding method for an error-correcting cyclic code with a correction capacity t that is sufficient to cope with high-speed data processing, and a step-by-step decoding method that simplifies the circuit configuration of the decoder to facilitate manufacturing. The purpose is to provide a decoder that can be used.

[Means to solve the problem]

The present invention is a decoding method using a cyclic code in order to solve the above-mentioned problems and achieve the desired purpose, in which the received word r (x) is read and the syndrome value S 1 (
X) + 12m I+ rl'12 + "'+
Step 1 of determining m++ and obtaining the decision vector H0;
Step 2 where j=1 and syndrome value S + (X) + 1 = m+
Cyclic shift of r m2'''m9 and syndrome value S + ''' (X) + 1 = rrl+ +
Step 3 to obtain ml + "'+ m, Step 4 to set p=Q, and S ) "' (X) +CI' + 1 "rn
l + m2 + ”'m, and determine the decision vector H
Step 5 to obtain 1; If Heθφ1 and H'Eφ1゜, and if 0≦1≦t, proceed to step 9; Step 6, if HOE
If φ1 is H'Eφ, -1 and O<1≦t, (I) rゎ1,=rゎ15+α' : (II) S + ''' (X) + α' +
1 = m+ + m2+..., m, ; (III) H' = H'; (IV) Go to step 9; and if p<q-t, set p=p+1. Step 8 of returning to step 5; Step 9 of returning to step 3 with j=j11 if j<H; otherwise step lO of returning to step 3 with j=n.
It is effective to use the steps of and as the basic configuration.

A decoder according to the above method includes an n-symbol shift register buffer for temporarily storing received words, and S + (X) + I = m + + m2 +
``・+ rrlp to obtain the decision vector H0, a syndrome value calculation circuit, S + ``' (X) + CI' + 1''
A vector value comparison circuit that calculates rl'l+ + m2+ . a shift control circuit that executes the shift control circuit; an error value position determination circuit that is connected to the vector value comparison circuit to execute the above step 7 and detects the error position and the number of errors when the output thereof becomes 1; and the syndrome. a check value output circuit that outputs a check value β=α9 to the value calculation circuit and the vector value comparison circuit; and a check value output circuit that is connected to the check value output circuit and outputs the check value β=α9.
α', p=o, 1. ..., a check confirmation circuit for confirming whether or not all of q-2 have been checked; Controls the shift operation of the buffer and syndrome value calculation circuit, and when its output becomes l, all shift registers shift the symbol by one digit to the right, and check whether this symbol has already been checked or decoding is completed. The system basically consists of a shift operation control circuit that represents the above-mentioned n-symbol shift register buffer and check value output circuit, and an adder on the Galois domain GF (q) that connects the n-symbol shift register buffer and check value output circuit and adds the output values of these two. It is convenient to configure this.

[Effect]

In the error correcting cyclic code with correction capacity t explained in the prior art, the following <A><B>
By focusing on these two points, it is possible to further simplify the conventional error correcting cyclic code and provide a method of increasing the decoding speed, as well as provide a decoder with a simple circuit configuration.

<A> Since the characteristics of the relationship between each syndrome value to obtain the decision bit and decision vector depend on whether the result of the combination operation is zero, we focused on the fact that the result of the operation can be expressed using bits. . Determine this bit bit h
1, as an improvement of the prior art error-correcting cyclic code, this decision bit h, if S, = O, = 1°, and vice versa, h1 = 0 or Sl)" +32 "If 0, then It can be defined as hi=1 - its inverse h2=0 (8), and the decision vector H can be obtained as a set of decision bits.

This decision vector H is H= (h+, hz)...
9), the error correcting cyclic code of the prior art with correction capability t can be simplified as follows.

When the number of errors is zero, H = (1, 1) When the number of errors is 1, H = (0, 1) When the number of errors is 2, H = (0, 0) ...
α0)<B> Even if the number of errors to obtain the decision set is the same, the error occurrence positions are different, so the correlation between the syndrome values is not limited to just one type. In this way, different decision vectors caused by errors with the same number of errors but different error patterns can be collected into one set. Here, when the set φ is defined as the number of errors=V, a set of decision vector patterns may appear, and this is defined as a decision set.

Therefore, the step-by-step decoding method of the present invention using the above <A> and <B> will be explained in the following three basic steps.

Step 1) - When the initial syndrome value of the received word r (x) is determined, a correspondence decision vector is obtained, so it is defined as Ho.

Step 2) Convert one symbol of the received word, e.g. +
m' and the corresponding decision vector H1 can be found.

Step 3) Directly comparing Ho and Hl, β is r, -
It is possible to check whether the number of errors is 8 or not.

By performing step-by-step cyclic shifts and calculations on the received word r (x) in this way, the entire received word can be decoded accurately. All decision sets are known for t error correcting codes existing in the Galois field GF (q), and the set φV.

v=1.2. The step-by-step decoding method described in the following example is capable of accurately decoding any received word with t or less than t errors, assuming that there are no intersects between ... can.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the step-by-step decoding method and decoder of the present invention will be described below with reference to the drawings.

<First embodiment of step-by-step decoding method> A preferred embodiment of the step-by-step decoding method of the present invention is comprised of the following steps.

Step 1. Read the received word r (x) and obtain the initial syndrome value Si (x), i=m 11 m 2
+...2m, and obtain the decision vector He.

Step 2. Set 3=1.

Step 3. Initial syndrome value Si(x).

t = m I * m x...+ m, is cyclically shifted, and the syndrome value S 1 ''' (X) +' 1 = m + r m2
+...1m is obtained.

Step 4. Let p=Q.

Step 5.8+”(x)+α’ 1 1”
m 1+mt+ ...+mp is calculated to obtain the decision vector H1.

Step 6, if H0εφ1 and HIEφ, +.

Moreover, if 0≦1≦t, the step Move on to step 9.

Step 7: If H'Eφ1 and H1εφl−1 and 0<1≦t, (I) r m−1:= r s−1+αp; (I
I) Si ” (x) + α′ i ”m+ r m2+ ”'+ m,; (I[[)H
'=H'; (IV) Go to step 9; Execute.

Step 8. If p<q'-1, p=p+1
and return to step 5.

Step 9. If j<1, set j=j+1 and return to step 3.

Step 10. Otherwise, j=n and the decoding is completed.

In the above decoding method, step 6 converts r*-1 to indicate that the number of errors has increased by one, so r,-1 is always an accurate code.

Therefore, it is possible to proceed directly to step 9 without having to determine that the error value is incorrect.

This step 6 is an optional step used to accelerate decoding speed.

In step 7, it is shown that r++-1 is an erroneous code, and changing α9 reduces the number of errors by one, so r, -, +α9 is always an accurate code. This step 7 small step (IF)
There is selectivity in executing (I), but by setting it to be executed here, the error detection capability can be increased to t or more. For example, in step 9, it can be measured when j = n, and if all syndrome values become zero, it indicates that the decoding was successful; otherwise, the number of errors present in the received code is always t. becomes larger than the individual. In addition, the execution of small steps (II) and (I) increases the chance that step 6 will occur, so the decoding speed can be accelerated.

<First embodiment of decoder related to the decoding method of the first embodiment> A first embodiment of the decoder related to the present invention will be described below with reference to the drawings.

In FIG. 1, the cyclic code decoder according to the present invention operates according to steps 1-10 above, and mainly reads the received word r (x) corresponding to step 1 above. n-symbol shift register buffer 110a, which also corresponds to step l above, temporarily stores Si (X) + 1"m+ + ms
+...'+ The syndrome value calculation circuit 111 which calculates mt to obtain the decision vector Ho, and the step 5 described above.
Corresponding to 3, tr) (X) + α' + i =
A vector value comparison circuit 112 that calculates m+ + ms + "'m to obtain the decision vector H1, and a shift control circuit 113 that forcibly executes a shift when the output becomes 1, corresponding to step 6 above. and an error numerical position determination circuit 114 which detects the error position and the number of errors when the output becomes 1, corresponding to step 7 above.
It consists of

The check value output circuit 115 is for outputting the check value β=α9, and the check confirmation circuit 116 is for outputting the check value β=α′, p=Q, 1. ... This is to confirm whether all q-2 have been checked.

The shift operation control circuit 117 is for controlling the shift operations of the n-symbol shift register buffer 110a and the syndrome value calculation circuit 111. When this shift operation control circuit 117 outputs C3=1,
All shift registers shift one symbol to the right to indicate that this symbol has already been checked or that decoding is complete.

The adder 118a on the Galois field GF (q) is for connecting the n-symbol shift register buffer 110a and the check value output circuit 115 and adding their output values.

With the above circuit configuration, for any error correcting cyclic code with correction capacity t,
Under the condition that all decision sets φ7 can be detected and the decision sets φ do not intersect, decoding can be performed by a decoder based on the decoding method of the present invention.

<Second embodiment of decoding method: non-binary RS code> An error correcting RS code with correction capability t for Galois domain GF (2''') is here code length n = 2'''-
1, integer m≧3.

First, from the received code r (x), the syndrome value S, = M
od (r (x)/M+ (x)) l x=α
1. i=1, 2. ... Obtain a total of 2 pieces of 2t.

Here, M,=X0α1 is called the minimum polynomial of α1. In addition, each syndrome value can be expressed using m bits.

continue, Expressed as a matrix, it looks like this:

v=1.2. . . , t+1 . . . αD If the order det(N,) = O, then = 1. Opposite beam, = 0
．． V=1,2.・t, and det(N
, ) indicates that the value of the matrix Nv formula is to be determined.

In addition, if da t (N+++) = de t(
Nl, +) +St+++d a t (Nt)
=o, =1; Opposite, +1 = 0. In this equation, the first term on the right side has S! Since S 2 + 41 cannot be obtained for an error correcting RS code with correction capability t, the first term on the right side contains zt++d e t(
N1) and 3 in d e t (Nl++')
The element 2t+1 was deleted. In other words, d
et (N,,I) is Si, i=1.2.・
..., 2t.

From the above t+1 decision bits, the decision vector H=
(h,,h,,...h,,,) can be synthesized, and φ. = ((1”')) can be found.Here,
1″1 represents a vector composed of t+1 consecutive bits as one unit.

φl = ((0, 1')) φ2-((X, 0.1'-1)): Here, x represents 1 or 0.

φ == ((xD-1, 0, l l-D**) )
, 3≦p≦t-1 φ+ −((x'-', o, x)) φ+-1= ((x'-', l, o))
....α above sl, i=1.2. ...
, 2t and φ,.

v=0.1. ..., by substituting t+1 into the decoding method of this invention, the correction ability t in the Galois field GF (2''')
A decoding method using an error correcting RS code can be obtained. With this decoding method and FIG. 2, n
The code length in the symbol shift register buffer 110a is set to a scale of n=2'''-1, the check value output circuit 115 is configured with an m-bit ring counter, and the check confirmation circuit 116 is configured with an m-terminal input. It is preferable that the shift operation control circuit 117 is an AND gate with four terminal inputs, and the adder 118a on the Galois domain GF (2'''') is composed of m two-person ex-OR gates.

<Second embodiment of decoder related to second embodiment of decoding method> An embodiment of the RS code, code length n=15゜m=4
Here is a double error correcting R3 decoder.

From the above method, S, , i=1. 2. 3. 4, det (Nl')=SI, det (Nz)=
S, , Ss 0 (sz)' and det (Nt) = (Ss) 2 +
Si (S4)'' is calculated as follows: det (N+), det (N2), det (N
3), we can obtain the following correspondence decision bits and decision sets.

φ. =(1,1,1) φ+ = (0,1,1) φ! = (x, O, x) φ3 = (X, 1. o) This φ. , φ3. The shift control circuit 113 shown in FIG. 2 can be constructed from φ and φ. , φ1 and φ2, an error value position determining circuit 114 shown in FIG. 3 can be constructed.

The syndrome value calculation circuit 111 is almost the same as a known electronic circuit, except that it feeds back the obtained error value to correct the initial syndrome value. In other words, S '' (X) + 72', i = 1.2, 3.4...
The difference is that C4 is executed, and the syndrome value calculation circuit 111 thereof is shown in FIG. In this FIG. 4, circuit components 1111.1112, 1113.1114 are α
', p=1. 2. 3. These circuit components 1111°1112.1113.
1114 uses a 21.times.m bit read-only memory (ROM) to store input/output comparison relationships in advance in an index table. Circuit component 1a is a single stage code register buffer.

and det (N,), det (Ns), de
t (Nz) to the vector value comparison circuit 1 shown in FIG.
It is possible to compose 12. In FIG. 5, circuit component 1121 consists of two m=4 EX-OR gates to perform a three-way operation. Although the circuit component 1122 is composed of a combination of logic gates to perform a three-way operation, it can also be replaced with a ROM. The circuit component 1123 is a GF (2''') having two different elements.
). Each circuit component 1124 is composed of an m-terminal input gate for determining whether the determinant is zero. Each circuit component 11
25 has the configuration shown in FIG. 6 in order to save the initial determination bit. In this FIG. 6, the circuit component 11251 is a bit register for storing an initially determined bit value. Small step of step 7 above (
DI), when H0=H', the switch SW5 closes and the left decision bit value is read.

<Operation of the decoder according to the present invention> Next, the operation of the decoder according to the present invention shown in FIGS. 1 to 6 will be explained using an example.

First, the error pattern is e (x) = (Z' XI4 + (Z'
Assuming that X''...C5, the operating timing sequence of the decoder according to the present invention is as shown in FIG.

1 and 7, the shift register buffer 110a is controlled by the clock signal 1 (CLKl) and the output C1 of the shift operation control circuit 117, and is controlled by the m-bit ring counter that constitutes the check value output circuit 115. The counting operation is performed using clock signal 1 (CLKI).
When C1=1, it is reset to the initial value, that is, C0. And switch S
W1 and SW4 are controlled by clock signal 2 (CLK2), and the complementary signal of clock signal 2 (CLK2) controls switches SW2 and SW3, and switches SW2 and SW4 are controlled by clock signal 2 (CLK2).
W7 is controlled by clock signal 2 (CLK2). Switch SW5 receives clock signal 1 (CLKI) 6
and Ec, and switch SW5 is controlled by E. controlled by

In FIG. 5, since the vector value comparison circuit 112 is a relatively complicated electronic circuit, the calculation speed of this decoder also depends on the calculation speed of the vector value comparison circuit 112.
In the technique of the present invention, the vector value comparison circuit 112
Specifically, since one operation is completed in a few hundred nanoseconds, the decoder of the present invention has a processing speed of several megabits per second (Mbit/sec).
c) A larger amount of data can be decoded. In addition, when the code length becomes longer, that is, when m increases, it is only necessary to increase the number of circuits or the capacity of the ROM, and it does not affect the calculation speed of the decoder. The decoder of the invention is suitable for decoding a large amount of data with a long code length.

Next, based on the volley code of the decoder according to the present invention,
An example will be explained.

The syndrome value is Si = Mod (r (x)/g (x))X=a!
! I, i=1,5 . . . αG.

This g (x) is called the code generator polynomial,
α is the primitive light of GF (3').

First, if S, = o, then hl = = t; the opposite, =.

Or 31)'+23', then hz = 1; the opposite beam, = 0... Define at α, φ. = (1, 1), φ, = (0゜l
), φ1=(0,0)φ, (empty set) and substitute the results into steps 1 to 10 of the decoding method of this invention, it is possible to obtain a decoding method suitable for decoding volley codes. can. A decoder for the volley code can be manufactured using tristite logic gates, and the calculation of the syndrome value can be considerably simplified.

In the decoding method of this invention, check value β=αp(p
= Q, l, ..., q-2) are assumed to be checked one by one continuously, but in reality, the signs r, -
, q-1 values for , can be checked at the same time. Based on this idea, a volley code decoder using the decoding method of the present invention is shown in FIG.

<Third embodiment of decoder: Volley code decoder> In FIG. 8, since the volley code decoder using the decoding method of the present invention can check q-1 β values at the same time, ( 1-1 identical check circuits 212 are required.As shown in FIG. 9, this check circuit 212 is similar to the vector value comparison circuit 11 shown in FIG.
2 and the error value position determining circuit 114 shown in FIGS. 1 and 3. 213 is a total adder, and when the sign r, -1 is accurate, all the check circuits 212 send zero vectors to the total adder 213, and the output from the total adder 213 also becomes a zero vector. . When there is an error in the code r, -1, a certain check circuit 212 outputs an error value, but q-1 identical check circuits 212 output a zero vector, so the check circuit 212 The necessary error value will be present in the output, and the code -3 will be correctly decoded. A decoder for such a volley code requires q-1 check circuits 212, so the Galois field GF (
q' ) is suitable for the cyclic code. However, this q-1 check circuits 21
8 and 1O, which have the same content and can be easily manufactured as an integrated circuit by applying copying technology, show the control signals necessary for operating the volley code decoder. In the figure, clock signal 4 (CLK4) controls shift register buffer 110a at the rate of the input signal and switches 5
WII is controlled by clock signal 5 (CLK5) and switch 5W12.13 is controlled by clock signal 5 (CLK5).
The switches 5W12 and 13 in the check circuit 212 of FIG. 9 are controlled by the clock signal 5 (CLK5). Therefore, as can be seen from the above description, the volley code decoder according to the present invention can complete the decoding of the received word using only n clock signals 4 (CLK4).

<Third embodiment of decoding method: Decoding method of binary cyclic code> Now, for an error correcting binary cyclic code with correction capability t, there is only one possible error value,
In other words, since only β=1, the method can be simplified as follows compared to the above non-secondary postmortem method.

Step ■ Read the received word r (x) and obtain the syndrome value Si (x), i=m+.

Find m2+...2m and obtain the decision vector H0.

Step ■ Set j=1.

Step ■ Syndrome value St (x), t=m
I + m x...2m is cyclically shifted to obtain the syndrome value S, (1) (X) + i ``mt + mt ''' + mu.

Step ■ S l”' (X) + 1 + 1
=:m, 1mt+...+ml is calculated to obtain the decision vector H1.

Step ■ If H'Eφ1 and HIEφl−1 and 0 and 1≦t, (I) rt−+ = r, −4+ 1; (I[)Sl
”(x)+1.i=m+, mt.

..., m, ; (III) H' = H'; Execute.

Step ■ If j less than n, set j=j+1 and return to step ■.

Step ■ Otherwise, j=n and the decoding is completed.

<Fourth embodiment of decoder = binary code decoder> And,
The circuit configuration of a decoder based on the above simplified decoding method is shown in FIGS. 11 and 12.

11 and 12, a detailed explanation of the circuit configuration will be omitted since it has already been explained in FIGS. 1 and 8, but in particular, the circuit configuration of the decoder shown in FIG. , has the advantages of the two types of circuit configurations shown in Figures 1 and 8, and can be applied to codes with long code lengths and high data amounts, so that the received word can be decoded in only n clock cycles. can be completed. In FIG. 12, 110a is an n-code shift register buffer, 1
18a is an adder on a simple Galois field GF(2). As can be seen from Figures 11 and 12, 2
Ex-step-by-step decoders can be constructed much more simply than non-bi-post-decoder decoders.

<Fourth Example of Decoding Method: Binary BCH Code> Now, for an error correcting binary cyclic code with correction capability t, it is only necessary to find decision bits and decision sets.

For an error correcting binary BCH code with correction capability t in Galois domain GF (2'''), code length n = 2''''
−1, m=3, an integer.

First, from the received code r (x), the syndrome value Si =
Mod (r (x)/M+ (x)): x=
α' + 1=l, a,... Obtain the total of 2t-1.

Then, when expressed as a matrix, it becomes as follows.

v=1. 2. ...t...
...α barrel If the order de t (L,)=0 then hv=
1; Opposite beam, =0. y=l, 2. -, t.

Decision vector H=(h+,
hz,...,h,), and also φ. =(
(1')) φr = ((0, 1'-')) φ* = ((o, o, o, l'-")) φ, =
((x'-', o2, 1'-1)) ;3≦p≦t
-1 φ+=((x“-”, 0.0)) ・・・・・・α9
) sl, i=1.3. ..., 2t-1 and φ
v+y=Q, 1. By substituting .

<Fifth embodiment of decoder: binary BCH code> As a fifth embodiment of the BCH code, code length n=15. Let us consider a double error correcting BCH decoder with m=4.

From the above method we obtain Sl,i=1.3 and φ. = (1, 1, 1) φ+ = (0, 1, l) φ2 = (x, 0.x) φs = (x, 1.0) can be obtained.・・・・・・
- (a) A fifth embodiment of this BCH code is shown in FIGS. 13 to 15. 13 shows its syndrome value calculation circuit 111, 1b in the figure shows a single bit shift register, FIG. 13 shows its vector value comparison circuit 112, and FIG. 15 shows its error value position determining circuit 114. Therefore, it can be seen that the circuit configuration is extremely simple. In addition,
The configuration of this decoder is the same as that shown in FIGS. 8 and 9.

This code has triple error correcting ability, and its syndrome value is defined as Sl = Mod ((r (x)/g (x))x=a
”' + i=1+ : L 9. Here,
α is the primitive light of GF (2”).
・・・・・・(21) If S,=o
Then, = 1; its opposite is 20 or Sl)' + Ss = o, then ht = 1; its opposite is h2 = 0 or Sl)"C(T,)+T,]+(Ss)"
If (T2) = O, then hx = I; and vice versa, = 0... (22) Here, T2 = (St)" 10Ss, Ts" (Sl)
@+Ss ・・・・・・(23), so φ.

=(1,1,1), φI=(0,1°1), φ! =
(0, 0, 1), φ3 = (0, 0° 0) and substitute the results into the postmortem decoding method to obtain a decoding method suitable for decoding volley codes. This decoder will be similar to the third embodiment shown in FIGS. 8-10.

〔Effect of the invention〕

Since the present invention is constructed as described above, it achieves at least the following effects.

The cyclic code decoding method according to claim 1 can be applied to binary or non-binary cyclic codes and volley codes, so it has an extremely wide range of applications and is highly practical.

The cyclic code decoding method of claim 2 greatly simplifies the decoding method of claim 1.

The cyclic code decoder according to claims 3 to 6 is a VLSI
Since it has a simple circuit configuration that is compatible with the characteristics of the architecture of .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of a decoder based on a general cyclic code decoding method according to the present invention, and FIG. 2 is a block diagram of the decoder (first embodiment) shown in FIG. 3 is a circuit diagram showing an example of the configuration of the shift control circuit; FIG. 3 is a circuit diagram showing an example of the configuration of the decoder (first embodiment) shown in FIG. 1; and FIG. 1 is a circuit configuration diagram showing an example of the syndrome value calculation circuit of the decoder (first embodiment) shown in FIG.
A circuit configuration diagram showing an example of the configuration of the vector value comparison circuit of the decoder (first embodiment) shown in FIG. FIG. 7 is a circuit diagram showing the decoder (first stage) shown in FIG.
FIG. 8 is a block diagram showing a second embodiment of the decoder with simplified steps related to the present invention; FIG. 9 is a timing chart showing the operation of the decoder (
FIG. 10 is a timing chart showing the operation of the decoder (second embodiment) shown in FIG. FIG. 12 is a block diagram showing a third embodiment of the decoder with further simplified steps, FIG. 12 is a block diagram showing a fourth embodiment of the decoder with further simplified steps, and FIG. 14 is a circuit configuration diagram showing a configuration example (fifth embodiment) of the syndrome value calculation circuit shown in FIGS. 11 and 12. FIG. 14 is a configuration example of the vector value comparison circuit shown in FIGS. (Fifth Embodiment) FIG. 15 is a circuit diagram showing an example of the configuration of the error numerical value position determination circuit shown in FIGS. 11 and 12 (Fifth Embodiment). 110a...n symbol shift register buffer, 111...syndrome value calculation circuit, 112...
・Vector value comparison circuit, 113... Shift control circuit, 114... Error value position determination circuit, 11
5... Check value output circuit, 116... Check confirmation circuit, 117... Shift operation control circuit, 118a.
...Adder on Galois domain GF (q). ] Changne Hekanji San ■ Su Nagi Mu, a Kanko Daizu Kanro C Shini 4 o -1-〒m,,,,,, -- "1q--"
-〒LJ7L,, n + 2
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Claims (6)

[Claims] (1) A decoding method using a cyclic code, in which the received word r(x) is read and the syndrome value S_i(x
), i=m_1, m_2, . . . , m_p and obtain the decision vector H^0. Step 2: Set j=1. Syndrome value S_i(x), i=m_1, m_2, .
・, m_p is the cyclic shift syndrome value S_i
^(^j^)(x), i=m_1, m_2..., m_
Step 3 to obtain p; Step 4 to set p=0; S_i^(^j^)(x)+α^p, i=m_1, m_
2,..., step 5 of calculating m_p to obtain the decision vector H^j, and step 6 of moving to step 9 if H^0∈φ_1 and H^j∈φ_1_+_l and 0≦l≦t. and,
If H^0∈φ_1, H^j∈φ_1_-_l and C<l≦t, then (I) r_a_-_1=r_n_-_j+α^p; (
II) S_i^(^j^)(x)+α^p, i=m_1,
m_2,..., m_p; (III) H^0=H^j; (IV) Go to step 9; and if p<q'-1, step p=p+1. If j<n, set j=j+1 and return to step 3. Step 9. Otherwise, set j=n and complete the decoding. Step 10.
A step-by-step decoding method for a cyclic code having a correction ability t consisting of steps of and. (2) A decoding method using a binary cyclic code, in which the received word r(x) is read and the syndrome value S_i(x
), i=m_1, m_2, . , m_2...
・, m_p is cyclically shifted and the syndrome value S_
i^(^j^)(x), i=m_1, m_2,...
Step [3] to obtain m_p, S_i^(^j^)(x)+1, i=m_1, m_2,
..., step [4] of calculating m_p to obtain the decision vector H^j, and if H^0∈φ_1 and H^j∈φ_1_−_i and 0<1≦t, (I)r_n_ −_1=r_n_−_j+1; (II)
S_i^(^j^)(x)+1, i=m, m_2,...
・, m_p; (III) H^0=H^j; Step [5], and if j<n, set j=j+1 and step [3]
], and step [7] to complete the decoding with j=n otherwise.
A step-by-step decoding method for a binary cyclic code having a correction ability t consisting of the steps of ] and . (3) A decoder using a cyclic code, which includes an n-symbol shift register buffer that temporarily stores the received word, and calculates and determines S_i(x), i=m_1, m_2, ..., m_p. A syndrome value calculation circuit that obtains the vector H^0, and S_i^(^j^)(x)+α^p, i=m_1, m_
2, ..., a vector value comparison circuit that calculates m_p and obtains the decision vector H^j; and a vector value comparison circuit that is connected to the vector value comparison circuit, executes step 6 above, and executes a shift when its output becomes 1. an error value position determination circuit that is connected to the vector value comparison circuit to execute step 7 and detects the error position and number of errors when its output becomes 1; and the syndrome value a check value output circuit that outputs the check value β=α^p to the arithmetic circuit and the vector value comparison circuit; and a check value output circuit that is connected to the check value output circuit and outputs the check value β=α^p.
A check confirmation circuit that recognizes whether all α＾p, p=0, 1, ..., q-2 have been checked, and is connected to the shift control circuit, error numerical position determination circuit, and check confirmation circuit. Then, the shift operation of the n-symbol shift register buffer and the syndrome value calculation circuit is controlled, and when the output thereof becomes 1, all the shift registers shift the symbol by one digit to the right, and this symbol is A shift operation control circuit indicating that has already been checked or decoding has been completed is connected to the n-symbol shift register buffer and check value output circuit to generate an n-symbol shift register buffer and check value output circuit. 2. A step-by-step decoder for cyclic codes with correction capability t according to claim 1, comprising: an adder on Galois field GF(q) for adding output values of the circuits; (4) A decoder using a cyclic code, which is connected to an n-symbol shift register buffer for temporarily storing received words, and to the n-symbol shift register buffer. , the syndrome value S_j(x), i=
2 syndrome value calculation circuits that calculate m_1, m_2, ..., m_p to obtain the decision vector H^0; A plurality of check circuits to which the syndrome value S_i(x) is sent; and a plurality of check circuits connected to the check circuit to sum up the outputs of all the check circuits, and selectively input the summed result to one of the syndrome value calculation circuits. and a multiplier on Galois field GF(q) connected to the n-symbol shift register buffer and the total adder to add the outputs of these two. A step-by-step decoder for cyclic codes with the correction capability t described. (5) A decoder using a binary cyclic code, which includes an n-symbol shift register that temporarily stores the received word.
A buffer, a syndrome value calculation circuit that calculates S_i(x), i=m_1, m_2, ..., m_p and obtains the decision vector H^0, S_i^(^j^)(x)+1 and the decision vector H^j
, j=0, 1, 2, . . . , a vector value comparison circuit for calculating n;
] and an error value position determination circuit that feeds back the output to the syndrome value calculation circuit and the vector value comparison circuit;
3. A binary cyclic with correction capability t according to claim 2, comprising a register buffer and a multiplier on Galois field GF(q) connected to said total adder and adding the outputs of these two. Step-by-step code decoder. (6) A decoder using a binary cyclic code, which includes an n-symbol shift register that temporarily stores the received word.
a buffer, alternatively connected to the n-symbol shift register buffer, the syndrome value S_i(x), i= at the same time as any one receives a received code word;
2 syndrome value calculation circuits that calculate m_1, m_2, ..., m_p; and a vector that is connected to the 2 syndrome value calculation circuits and receives syndrome values calculated from only one syndrome value calculation circuit at a time. A value comparison circuit is connected to the vector value comparison circuit to perform step [5].
], an error value position determination circuit that feeds back an output to the vector value comparison circuit, and selects one of the two syndrome value calculation circuits and feeds back the output; a Galois field GF(q) connected to the buffer and the error value locating circuit to add the outputs of these two;
3. A step-by-step decoder for a binary cyclic code having correction capability t according to claim 2, comprising a multiplier as above.