JPS59124163A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPS59124163A
JPS59124163A JP57231521A JP23152182A JPS59124163A JP S59124163 A JPS59124163 A JP S59124163A JP 57231521 A JP57231521 A JP 57231521A JP 23152182 A JP23152182 A JP 23152182A JP S59124163 A JPS59124163 A JP S59124163A
Authority
JP
Japan
Prior art keywords
film
thin film
polycrystalline silicon
substrate
tpt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57231521A
Other languages
Japanese (ja)
Inventor
Takashi Nakagiri
孝志 中桐
Yutaka Hirai
裕 平井
Yoshiyuki Osada
芳幸 長田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP57231521A priority Critical patent/JPS59124163A/en
Priority to DE19833331601 priority patent/DE3331601A1/en
Publication of JPS59124163A publication Critical patent/JPS59124163A/en
Priority to US06/937,432 priority patent/US4740829A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Abstract

PURPOSE:To obtain a semiconductor element characterized by excellent electric characteristics and small aging value, with a good yield rate, by using a thin Si.Ge film, which includes H atoms of 3 atom % or less. CONSTITUTION:On a glass plate 101, e.g., SiH4 and GeH2 are dilluted by H2 or the like and reacted in a specified deivce, and a thin polycrystal Si.Ge film 102 is formed. Source and drain electrodes 103 and 104 are provided through insulating films 107 and 108. The surface is coated by an insulating film 105. A gate electrode 106 is attached. Thus a typical thin film FET is formed. In this case, the H atoms included in the thin film 102 are mainly pesent in the gain boundary of the polycrystal Si.Ge. When the quantity of the H is large, the H is included in the double or triple bond or in a free state. The characteristics of the element are deteriorated by said H in the unstable state. When the quantity of H inclusion in the thin film is restricted to 0.01-3 atom%, optimally to 0.1-1 atom %, ageing is reduced, the characteristics are excellent, dispersion is reduced, and the yield rate is improved.

Description

【発明の詳細な説明】 本発明は、電界効果トランジスタ等の半導体素子に関し
、更に詳しくは、多結晶シリコン・ゲルマニヴム薄膜半
導体層でその主要部を構成した半導体素子に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device such as a field effect transistor, and more particularly to a semiconductor device whose main portion is composed of a polycrystalline silicon germanium thin film semiconductor layer.

最近、画像読取用としての、長尺化された1次元フォト
センサーや大面積化された2次元フォトセンナ−等の画
像読取装置の走置回路部、或は液晶(以FLCと記す)
や電界発光(以下ff1Lと記す)やエレクトロクロミ
ー材料(以FJiliOと記す)を利用した画像表示デ
バイスの駆動回路部を、これ等の大型化に伴って、所定
の基板上に形成されたシリコン薄膜を素材とじて形成す
るという事が提案されている。そして、従来、シリコン
薄膜としては、水素化非晶質シリコン薄膜や多結晶シリ
コン薄膜の検討が試みられている。面乍ら高速、高機能
の読取装置の走査回路部や画像表示装置の駆動回路が要
請する実効キャリアー移動度(以Fμoffと記す)が
50〜100cz2/ V−sec程度なのに対して、
非晶質シリコン薄膜を用いた薄膜トランジスタ(TPT
)ではμeffが約0. I C”m2/ V;sec
程度と小さい為、上記回路部を構成するのには必ずしも
適当とは云えなかった。一方、多結晶シリコン薄膜は非
晶質シリコン薄膜に比べμ。ffは太きいが、前記要請
に応える為にはアニール工程を必要とする為、工程が複
雑になり、且つ大面積に亘って均一な膜が得られない場
合もある等の問題があった。
Recently, the scanning circuit section or liquid crystal (hereinafter referred to as FLC) of image reading devices such as elongated one-dimensional photosensors and large-area two-dimensional photosensors for image reading has been developed.
With the increase in the size of these devices, the drive circuits of image display devices that use ``FJiliO'', electroluminescence (hereinafter referred to as FF1L), and electrochromic materials (hereinafter referred to as FJiliO) are being made using silicon formed on a predetermined substrate. It has been proposed to form a thin film as a material. Conventionally, attempts have been made to use hydrogenated amorphous silicon thin films and polycrystalline silicon thin films as silicon thin films. Of course, the effective carrier mobility (hereinafter referred to as Fμoff) required by the scanning circuit section of a high-speed, high-performance reading device or the drive circuit of an image display device is about 50 to 100 cz2/V-sec.
Thin film transistor (TPT) using amorphous silicon thin film
), μeff is about 0. I C”m2/V;sec
Because of its small size, it could not necessarily be said to be suitable for constructing the above circuit section. On the other hand, polycrystalline silicon thin films have a smaller μ than amorphous silicon thin films. Although ff is large, an annealing process is required to meet the above requirements, which causes problems such as the process becomes complicated and a uniform film may not be obtained over a large area.

他方、多結晶ゲルマニウム薄膜の形成は従来真空蒸着法
で試みられ、該方法で得−られだ膜のホール移動度(以
下μ■と記す)は数百cm2/V・8θCと極めて大き
く、μeffも大きいことが期待されていた。併し、通
常多結晶ゲルマニウム薄膜は高濃度のアクセプター準位
が形成される為、n型或はp型半導体への制御性が悪く
、多結晶ゲルマニウム薄膜半導体素子は実用に供せられ
ていなかった。これは所謂真性半導体が形成されにくい
為に不純物添加によるゲルマニウム母体へのドーピング
効率が極めて悪い為であった。
On the other hand, the formation of polycrystalline germanium thin films has conventionally been attempted by vacuum evaporation, and the hole mobility (hereinafter referred to as μ■) of the film obtained by this method is extremely large, several hundred cm2/V・8θC, and μeff is also low. Big things were expected. However, because a polycrystalline germanium thin film normally forms a high concentration of acceptor levels, controllability to n-type or p-type semiconductors is poor, and polycrystalline germanium thin-film semiconductor devices have not been put to practical use. . This is because it is difficult to form a so-called intrinsic semiconductor, and the efficiency of doping the germanium matrix by adding impurities is extremely low.

又、ゲルマニウム薄膜には熱処理によってn型半導体か
らp型半導体へ変換するという熱的変換(Therma
l Conversion)と呼ばれる現象が見られる
為、熱処理工程を含むデバイス作成には不適であった。
In addition, the germanium thin film undergoes thermal conversion (thermal conversion, which converts an n-type semiconductor into a p-type semiconductor by heat treatment).
Since a phenomenon called 1 Conversion was observed, it was unsuitable for device fabrication involving a heat treatment process.

この様に、従来作成された多結晶ゲルマニウム薄膜を素
材とした素子或はデバイスが所望の特性及び信頼性を充
分発揮できなかったのが現状である。
As described above, the current situation is that conventionally produced elements or devices made of polycrystalline germanium thin films have not been able to sufficiently exhibit desired characteristics and reliability.

また、ゲルマニウムはシリコンに比ベエネルギーギャッ
プが小さいため、例えば半導体素子において多く用いら
れるpn接合の逆方向飽和電流が大きく笑用土問題にな
る場合が生ずるときもありかつエネルギーギャップが小
さいと価電子帯から伝導体に熱エネルギーで上げられる
キャリアー濃度が不純物が与えているキャリアー濃度に
低い温度で近づき、デバイスの温度許容範囲が狭いとい
った欠点を有していた。
In addition, germanium has a smaller energy gap than silicon, so for example, the reverse saturation current of pn junctions, which are often used in semiconductor devices, may be large and cause problems, and if the energy gap is small, the valence band However, the carrier concentration raised by thermal energy in the conductor approaches the carrier concentration provided by impurities at low temperatures, resulting in a narrow temperature tolerance range for devices.

本発明は上記諸点に鑑み成されたもので、素子性能の高
い又、信頼性に富んだ半導体素子を提供する事を目的と
する。又、半導体の禁制帯中に不純物準位の極めて少な
い、即ち制御すべき不純物添加のドーピング効率の極め
て良好かつエネルギーギャップがゲルマニウムよシ犬き
な値を有する多結晶シリコン・ゲルマニウム薄膜を用い
た半導体素子を提供する事を目的とする。更には基板上
に形成される多結晶シリコン     ゛・ゲルマニウ
ム薄膜中導体層を用いて、高性能で信頼性が高く安定性
の良い電界効果型の薄膜トランジスターを提供する事を
目的とする。又、別には、優れた多結晶シリコン・ゲル
マニウム半導体層を用いた電界効果型の薄膜トランジス
ターを構成素子とする大面積化半導体デバイスを提供す
る事を目的とする。
The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device with high device performance and high reliability. In addition, a semiconductor using a polycrystalline silicon/germanium thin film has extremely few impurity levels in the forbidden band of the semiconductor, that is, the doping efficiency of the impurity addition to be controlled is extremely good, and the energy gap is comparable to that of germanium. The purpose is to provide devices. Furthermore, it is an object of the present invention to provide a field-effect thin film transistor with high performance, high reliability, and good stability by using a polycrystalline silicon germanium thin film medium conductor layer formed on a substrate. Another object of the present invention is to provide a large-area semiconductor device whose constituent elements are field-effect thin film transistors using an excellent polycrystalline silicon germanium semiconductor layer.

斯かる目的を達成する為の本発明の半導体素子は3 a
tomic %以丁の水素原子を含有する多結晶シリコ
ン・ゲルマニウム半導体層でその主要部が構成されてい
る事を特徴とする。
The semiconductor device of the present invention for achieving this purpose is 3a.
It is characterized in that its main portion is composed of a polycrystalline silicon germanium semiconductor layer containing more than 10% of hydrogen atoms.

上記の様な量の水素原子を含有する多結晶シリコン・ゲ
ルマニウム薄膜を素材として作製される半導体素子はそ
の電気的特性が良く、経時変化もなく、且つ素子の歩留
り及びバラツキも著しく向上させる事ができる。その為
、LC。
Semiconductor devices manufactured using polycrystalline silicon/germanium thin films containing the above-mentioned amount of hydrogen atoms have good electrical characteristics, do not change over time, and can significantly improve device yield and variation. can. For that reason, LC.

EL或はgc等を利用した表示、或は画像デバイス等の
走査回路や駆動回路等を安定して提供することが出来る
It is possible to stably provide a display using EL or GC, or a scanning circuit, a driving circuit, etc. of an image device, etc.

本発明の多結晶シリコン・ゲルマニウム薄膜を素材とし
て作成される半導体素子の一例としての電界効果型の薄
膜トランジスタ(TPT)//i、半導体層、電極層、
絶縁層を用いたトランジスタとして知られている。即ち
1.半導体層に隣接したオーミンクなコンタクトを持っ
たソース電極・ドレイン電極間に電圧を印加し、そこを
流れるチャンネル電流を絶縁層を介して設けたゲート電
極にかけるバイアス電圧により変調される。
A field effect thin film transistor (TPT) as an example of a semiconductor device made using the polycrystalline silicon germanium thin film of the present invention as a material, a semiconductor layer, an electrode layer,
It is known as a transistor using an insulating layer. Namely 1. A voltage is applied between the source and drain electrodes that have ohmic contacts adjacent to the semiconductor layer, and the channel current flowing there is modulated by the bias voltage applied to the gate electrode provided through the insulating layer.

第1図にはこのようなTPTの典を的な基本構造の一例
が示される。絶縁性基板101上に設けら′れた半導体
層102上にソース電極103、ドレイン電極104が
接して設けてあり、これ等を被覆する様に絶縁層105
が設けられ、該絶縁層105上にゲート電極106があ
る。
FIG. 1 shows an example of the typical basic structure of such a TPT. A source electrode 103 and a drain electrode 104 are provided on and in contact with a semiconductor layer 102 provided on an insulating substrate 101, and an insulating layer 105 is formed to cover these.
is provided, and a gate electrode 106 is provided on the insulating layer 105.

本発明に於ける第1図に示される構造を有するTIi′
Tに於いては、半導体層102は、前述した特性を有す
る多結晶ゲルマニウム薄膜で構成され、半導体層102
と2つの電極、即ち、ソース電極103、ドレイン電極
104の各々との間には、第1のn+層107、第2の
1層108が設けられ、オーミックコンタクトを形成し
ている。
TIi′ having the structure shown in FIG. 1 according to the present invention
In T, the semiconductor layer 102 is composed of a polycrystalline germanium thin film having the above-mentioned characteristics.
A first n+ layer 107 and a second 1 layer 108 are provided between each of the two electrodes, ie, the source electrode 103 and the drain electrode 104, to form an ohmic contact.

絶縁層105はCVD (ChemicaIVapou
rDeposition )、LPOVD (Lovr
 Presure C!hemicalVapour 
Deposition) %又はPC!VD (Pla
scoaC!hemical Vapour Depo
sition)等で形成されるシリコンナイト2イド、
S10□、Al2O3等の材料で構成される。
The insulating layer 105 is formed by CVD (Chemical Vapor
rDeposition), LPOVD (Lovr
Presure C! chemical vapor
Deposition) % or PC! VD (Pla
scoaC! chemical vapor depot
siliconite 2-ide formed by
It is made of materials such as S10□ and Al2O3.

半導体層102を構成する多結晶シリコン・ゲルマニウ
ム薄膜の作成に用いる反応性気体としてはシリコンを構
成原子とする物質、例えばモノシラン(s1n4) 、
ジシラン(Si2H6)などのシランガス及びゲルマニ
ウムを構成原子とする物質、例えばモノゲルマン(G 
eH4) 、ジゲルマ/ (Ge2 Hb )、トリゲ
ルマン(ie、H8)等のゲルマンガスがあげられ、こ
れら反応性気体はH2+ Ar + H8等のガスで稀
釈して用いることも出来る。
The reactive gas used to create the polycrystalline silicon germanium thin film constituting the semiconductor layer 102 is a substance whose constituent atoms are silicon, such as monosilane (s1n4),
Silane gas such as disilane (Si2H6) and substances containing germanium as constituent atoms, such as monogermane (G
Examples include germane gases such as eH4), digelma/(Ge2Hb), and trigermane (ie, H8), and these reactive gases can also be used after being diluted with a gas such as H2+Ar+H8.

電界効果型TPTはゲート電極上にゲート絶縁層がある
型(丁ゲート型)とゲート絶縁ノω上にゲート電極があ
る型(上ゲート型)に分類され、他方、ソース、ドレイ
ン電極が絶縁層と半導体層の界面にある型(Copla
nar型)とソースドレイン電極が絶縁層と半導体層の
界面と対向した半導体面上にある型(stagger型
)に分類され、各々の組合せで4つの型があることがよ
く知られている。第1図で示された構造は上ゲート0o
p1anar 9電界効果型’I’FTと昧ばれる例を
示したが、本発明に係る電界効果型TPTはこのいずれ
でもよいことは勿論である。
Field-effect TPTs are classified into types with a gate insulating layer on the gate electrode (upper gate type) and types with a gate electrode on the gate insulator (upper gate type).On the other hand, the source and drain electrodes have an insulating layer. The type (Copla) at the interface between the semiconductor layer and the semiconductor layer
It is well known that there are four types for each combination. The structure shown in Figure 1 is the upper gate 0o
Although an example that is classified as p1ar 9 field effect type 'I'FT has been shown, it goes without saying that the field effect type TPT according to the present invention may be any of these.

本発明に於ては、半導体素子の主要部である半導体層を
構成する多結晶シリコン・ゲルマニウム薄膜に含有する
水素原子量の下限を好ましくは0.01 atomic
チ(以下1−at、チ」と記す)にすることによって種
々のトランジスター特性を向上させることができる。他
方、多結晶シリコン・ゲルマニウム薄膜に含有される水
素原子は主に多結晶シリコン・ゲルマニウムの結晶粒界
に存在し、81−R,Ge−Hの形で結合しているが、
含有される水素原子の量が多いと5i=−H2,Siミ
ヘ。
In the present invention, the lower limit of the amount of hydrogen atoms contained in the polycrystalline silicon germanium thin film constituting the semiconductor layer, which is the main part of the semiconductor element, is preferably 0.01 atomic.
Various transistor characteristics can be improved by using a 1-at (hereinafter referred to as 1-at). On the other hand, the hydrogen atoms contained in the polycrystalline silicon/germanium thin film mainly exist at the grain boundaries of the polycrystalline silicon/germanium and are bonded in the form of 81-R, Ge-H.
If the amount of hydrogen atoms contained is large, 5i = -H2, Si Mihe.

Ge−H2,GeミH3の如き結合形態や遊離の状態で
水素が含まれていることが予想され、これ等の不安定な
状態で含有されている水素に起因するものと思われるト
ランジスター特性の劣化が生ずる場合が少なくない。
It is expected that hydrogen is contained in bonded forms such as Ge-H2, Ge-H3, or in a free state, and the transistor characteristics that are thought to be caused by hydrogen contained in these unstable states. Deterioration often occurs.

本発明者等の多くの実験事実から多結晶シリコン・ゲル
マニウム薄膜に含有する水素量が5at、 %以下の場
合に於てはトランジスター特性の劣化は殆んどなく、安
定してその特性を維持し得ることが判明した。
The inventors have found from many experiments that when the amount of hydrogen contained in the polycrystalline silicon germanium thin film is 5at.% or less, there is almost no deterioration of the transistor characteristics, and the characteristics are stably maintained. It turns out that you can get it.

又、該薄膜に含有される水素原子の量が5at。Further, the amount of hydrogen atoms contained in the thin film is 5 at.

チを越えてよシ多くなった場合に於ては作成したトラン
ジスタを連続的に動作させた場合、μθffの減少が見
られ且つ出力ドレイン電流力;時間とともに減少し、ス
レツショホールド・電圧VTHが変化するというような
経時変化が観察されている。従って本発明に於ては半導
体素子の主要部を構成する多結晶シリコン・ゲルマニウ
ム薄膜に含有する水素原子の量は好ましくは0.01〜
3 at、チとされ、より好適には0.05〜2at。
When the transistor is continuously operated in the case where the voltage exceeds 1, a decrease in μθff is observed, and the output drain current decreases with time, and the threshold voltage VTH decreases. Changes over time have been observed. Therefore, in the present invention, the amount of hydrogen atoms contained in the polycrystalline silicon germanium thin film that constitutes the main part of the semiconductor device is preferably 0.01 to
3 at, more preferably 0.05 to 2 at.

チ、最適には0.1〜1 at、%とするのが望ましい
The optimum range is 0.1 to 1 at.%.

本発明において規定する多結晶シリコン・ゲルマニウム
薄膜中に含まれている水素原子量の測定は0.1 at
、 4以上は通常化学分析で用いられテイル水素分析計
(Perkin E1mer社製Mode1素重量を測
定し、膜中に含まれる水素原子量をatomic係で算
出した。
The measurement of the amount of hydrogen atoms contained in the polycrystalline silicon germanium thin film specified in the present invention is 0.1 at
, 4 or more is usually used in chemical analysis, and the elementary weight was measured using a tail hydrogen analyzer (Model 1 manufactured by Perkin Elmer), and the amount of hydrogen atoms contained in the film was calculated using an atomic coefficient.

0.1 at、%以下の微小量分析は二次イオン質量分
析計−8工MS−(Oameca社製Model工MS
 −6f)(でより行った。その分析法に於ては通常の
方法を踏襲した。即ち、チャージアップ防止のため薄膜
上に200X厚の金を蒸着し、−次イオンビームのイオ
ンエネルギーを5 KeVとし、サンプル電流s x 
10−” A %スポットサイズ50μm径とし、エツ
チング面積は250X250μmとしてS1+及び()
e+に対するrイオンの検出強度比を求め水素原子含有
量をat;omic−%で算出した。
Micro-quantity analysis of 0.1 at, % or less is performed using a secondary ion mass spectrometer - 8-MS
-6f) KeV, sample current s x
10-” A % spot size is 50 μm in diameter, etching area is 250×250 μm, S1+ and ()
The detection intensity ratio of r ions to e+ was determined, and the hydrogen atom content was calculated in at;omic-%.

又、本発明の効果を示す為の多結晶シリコン・ゲルマニ
ウム薄膜トランジスターの経時変化の測定に関しては以
下の様な方法によった。
In order to demonstrate the effects of the present invention, the following method was used to measure changes over time in polycrystalline silicon germanium thin film transistors.

先ず、第2図に示す構造のTPTを作製し、ゲ−)20
1にゲート電圧V、として40V1ソース203とドレ
イン202の間にドレイン電圧VDとして40Vを印加
し、ソース203とドレイン202の間に流れるドレイ
ン電流よりをエレクトロメーター(Keithley 
6100 エレクトロメーター)により測定した。経時
変化率は、500時間の連続動作後のドレイン電流の変
動量を初期ドレイン電流で割ったものを100倍してヂ
表示で表わした。
First, a TPT having the structure shown in FIG.
1, a gate voltage V of 40V1 and a drain voltage VD of 40V is applied between the source 203 and the drain 202, and the drain current flowing between the source 203 and the drain 202 is measured using an electrometer (Keithley).
6100 electrometer). The rate of change over time was expressed by dividing the amount of variation in drain current after 500 hours of continuous operation by the initial drain current and multiplying it by 100.

TFTの閾値電圧(VTH)はMOS−FjET (M
etal −oxlae−8emiconauctor
形電界効果トランジスタ)で通常行なわれているvDv
”;曲線における直線部分を外挿し横軸である■D−軸
と交差した点によって定義した。経時変化の前と後のV
THの値も同時に調べ、その変化量(ΔVTH)を電圧
で表示した。
The threshold voltage (VTH) of TFT is MOS-FjET (M
etal-oxlae-8emiconauctor
vDv, which is normally carried out in
”; Defined by the point where the straight line part of the curve is extrapolated and intersects the horizontal axis ■D-axis. V before and after the change over time
The value of TH was also checked at the same time, and the amount of change (ΔVTH) was expressed as a voltage.

形成する多結晶シリコン・ゲルマニウム薄膜半導体層に
含有される水素量を前記した様な量に制御するには種々
の方法によって行なわれる。
Various methods can be used to control the amount of hydrogen contained in the formed polycrystalline silicon germanium thin film semiconductor layer to the above-mentioned amount.

例えば、SiH4+ S i2 H6等の水素化シリコ
ン及びGeH4,Ge2H6等の水素化ゲルマニウムを
グロー放電分解法(()D法)によって析出させる方法
、Gθメタ−ットを用いH2又はGeH4を含むガス中
でスハツターする方法(SP法)、H2プラズマ雰囲気
で−を電子ビーム等を用いて蒸着する方法(工F法)、
超高真空度のH2雰囲気下で蒸着する方法(H’7D法
)を始め、OVD ヤLPOVD等で形成された多結晶
シリコン・ゲルマニウム薄膜をH2プラズマ処理する方
法等々によって行なうことが出来る。
For example, silicon hydride such as SiH4+ Si2 H6 and germanium hydride such as GeH4, Ge2H6 are precipitated by glow discharge decomposition method (()D method), or in a gas containing H2 or GeH4 using Gθ met. A method of evaporating - using an electron beam or the like in an H2 plasma atmosphere (F method),
This can be performed by a method of vapor deposition in an H2 atmosphere at an ultra-high vacuum (H'7D method), a method of treating a polycrystalline silicon germanium thin film formed by OVD or LPOVD with H2 plasma, and the like.

本発明に於て開示される様に、GD法、sp法、■p法
、HVD法では基板表面温度が500薄膜が形成出来る
。このことは、大面積デバイス用の大面積に亘る駆動回
路や走査回路の作成に於て、基板を均一に加熱するとい
う点や安価な大面積基板材料を用いることが出来るとい
う点で有利である。更に、透過型の板爪素子用の基板や
基板側入射型の光電変換素子用の基板等の画像デバイス
の応用において望まれている透光性のガラス基板の使用
という要求に答えるものとして重要である。
As disclosed in the present invention, a thin film with a substrate surface temperature of 500 can be formed by the GD method, sp method, p method, and HVD method. This is advantageous in that the substrate can be heated uniformly and inexpensive large-area substrate materials can be used when creating large-area drive circuits and scanning circuits for large-area devices. . Furthermore, it is important as it meets the demand for the use of translucent glass substrates in applications of image devices such as substrates for transmissive plate-claw elements and substrates for substrate-side incident photoelectric conversion elements. be.

即ち5本発明によれば所望の多結晶シリコン・ゲルマニ
ウム薄膜を得るのに低温度領域を用いる事が出来る為、
高融点ガラス、硬ガラス等の耐熱性ガラス、及び耐熱性
セラミックス、サファイヤ、スピーネル、シリコンウエ
ノ1−等の他に、一般の低融点ガラス、耐熱性プラスチ
ック等も使用され得るものである。一般の低融点ガラス
を用いたガラス基板としては、軟化点温度が630Cの
並ガラス、軟化点が78DCの普通硬質ガラス、軟化点
温度が820t″の超硬質ガラス(5181級超硬質ガ
ラス)等を用いることが考えられる。
That is, according to the present invention, a low temperature region can be used to obtain a desired polycrystalline silicon germanium thin film.
In addition to heat-resistant glasses such as high-melting point glass and hard glass, heat-resistant ceramics, sapphire, spinel, silicone urethane, etc., general low-melting point glasses, heat-resistant plastics, etc. may also be used. Glass substrates using general low-melting point glass include ordinary glass with a softening point of 630C, ordinary hard glass with a softening point of 78DC, and ultra-hard glass (5181 class ultra-hard glass) with a softening point of 820t''. It is possible to use it.

本発明の製法に於てはいずれの基板を用いても基板温度
が軟化点より低く押えられるため、基板をそこなうこと
なく、膜を作成できる利点がある。
In the manufacturing method of the present invention, the temperature of the substrate can be kept below the softening point no matter which substrate is used, so there is an advantage that the film can be formed without damaging the substrate.

本発明の実施例に於ては基板ガラスとして軟化点の低い
並ガラス(ソーダガラス)のうち主トシてコーニング+
7059ガラス(コーニング社製)を用いたが、軟化点
が1500′cの石英ガラス等を基板としても可能であ
る。しかし、実用上からは並ガラスを用いることは安価
で大面積にわたって薄膜トランビスター(TPT )を
作製する上で有利である。
In the embodiments of the present invention, Corning +
Although 7059 glass (manufactured by Corning Inc.) was used, quartz glass or the like having a softening point of 1500'c can also be used as the substrate. However, from a practical point of view, it is advantageous to use ordinary glass at low cost and to produce thin film transistors (TPT) over a large area.

以Fに、本発明を更に詳細に説明するために多結晶シリ
コン・ゲルマニウム薄膜の形成からTPTの作製プロセ
スとTPT動作結果について実施例によって具体的に説
明する。
Hereinafter, in order to explain the present invention in more detail, the process from forming a polycrystalline silicon germanium thin film to the fabrication process of TPT and the results of TPT operation will be specifically explained using examples.

実施例 1 本実施例は多結晶シリコン・ゲルマニウム薄膜を基板上
に形成し、TPTを作成したもので、第3図に示される
様な装置を月いたものである。
Example 1 In this example, a polycrystalline silicon germanium thin film was formed on a substrate to create a TPT, and an apparatus as shown in FIG. 3 was used.

基板300としては、コーニング+7059ガラスを用
いた。
As the substrate 300, Corning +7059 glass was used.

先ず基板300を洗浄した後HFIH1(0,10H3
000Hの混合液でその表面を軽くエツチングし、乾燥
した後ペルジャー真空堆積室(以下ペルジャーと記す)
601内のアノード側に置いた基板加熱ホルタ−302
に装着した。その後、ペルジャー301を拡散ポンプ3
09でバックグラウンド圧力1 X i O’Torr
以丁まで排気を行った。もし、このときの圧力が高いと
反応性ガスが有効に膜析出に寄与しないばかりか、膜中
に酸素、窒素が混入し、著しく膜の抵抗を変化させるの
で望ましくない。次に基板温度TSを上げて基板600
の温度を500Cに保持した。又、基板温度は熱電対6
06で監視した。
First, after cleaning the substrate 300, HFIH1 (0,10H3
After lightly etching the surface with a mixed solution of 000H and drying it, it was placed in a Pelger vacuum deposition chamber (hereinafter referred to as Pelger).
Substrate heating holter 302 placed on the anode side in 601
It was installed on. Then, attach the Pelger 301 to the diffusion pump 3.
09 and background pressure 1 X i O'Torr
Exhaust was carried out to the end. If the pressure at this time is high, not only will the reactive gas not contribute effectively to film deposition, but also oxygen and nitrogen will be mixed into the film, which will significantly change the resistance of the film, which is not desirable. Next, raise the substrate temperature TS and heat the substrate 600.
The temperature was maintained at 500C. Also, the substrate temperature is measured by thermocouple 6.
It was monitored on 06.

本実施例において導入する反応性気体としては、H2ガ
スで1’ VO’lumeチ(以下vo/l−%と記す
)に稀釈されたSiH4ガス(以下5in4(1)/H
2と記す)とGeH4ガス(以下G8H4(1)/′H
2と記す)とH2ガスで100 volume ppm
(以下vojl!、 ppmと記す)に稀釈されたB2
H6ガス(以下B2H6(100)/H2と記す)を用
い、51a4(1)/ ”2をマスフローコントローラ
ー310を用いて40 BCCM 、 ’GeI(4(
1)/ H2をマスフローコントローラー604ヲ用い
テ20800Mの流量、更にB2H6(100)/H2
をマスフローコントローラー307を用いて3 、OS
OCMの流量で合せてリング状ガス吹出し口615から
ペルジャー301内に導入し、メインパルプ617を調
整し、絶対圧力計316を用いてペルジャー301内を
0.01 Torrの圧力に設定した。
The reactive gas introduced in this example was SiH4 gas (hereinafter referred to as 5in4(1)/H
2) and GeH4 gas (hereinafter referred to as G8H4(1)/'H
2) and H2 gas at 100 volume ppm
B2 diluted to (hereinafter referred to as vojl!, ppm)
Using H6 gas (hereinafter referred to as B2H6(100)/H2), 51a4(1)/''2 was converted to 40 BCCM using a mass flow controller 310, 'GeI(4(
1)/H2 using a mass flow controller 604 with a flow rate of 20800M, and further B2H6 (100)/H2
3 using mass flow controller 307, OS
The OCM was combined with the flow rate and introduced into the Pel jar 301 from the ring-shaped gas outlet 615, the main pulp 617 was adjusted, and the pressure inside the Pel jar 301 was set to 0.01 Torr using the absolute pressure gauge 316.

ペルジャー301内の圧力が安定した後、カソード電極
314に1 !+、56 MH,の高周波電界を電源6
15によって加え、グロー放電を開始させた。
After the pressure inside the Pelger 301 stabilizes, 1! is applied to the cathode electrode 314. +, 56 MH, high frequency electric field from power supply 6
15 to start glow discharge.

この時の電圧は0.6に■、電流は55 mA 、 R
F(Radis Frequency)パワーは20W
であった。
At this time, the voltage was 0.6, the current was 55 mA, R
F (Radis Frequency) power is 20W
Met.

形成された膜の膜厚は0.5μでその均一性は円形リン
グ型吹き出し口を用いた場合には120中に含有する水
素原子量は0.2at、%であった。
The thickness of the formed film was 0.5 μm, and its uniformity was 0.2 at.% when a circular ring-shaped outlet was used.

次に、この膜を素材として第4図に概略で示される工程
に従ってTPTを作成した。工程(a)に示す様に、ガ
ラス基板300上に上記の様に形成した多結晶シリコン
・ゲルマニウム薄膜4月を析出した後、水素ガスで10
0 voJ、ppmに稀釈されたpH,ガス(以下p、
H,(100)/H2と記す)をGea4及びEliH
4ガスの総量に対してpH,ガスを5x i o−3の
モル比の割合となる様にペルジャー301内に流入させ
、ペルジャー301内の圧力を0.12 Torrに調
整してグロー放電を行い燐のドープされた1層402を
0.05μの厚さに形成した(工程(b))。
Next, using this film as a material, TPT was fabricated according to the steps outlined in FIG. 4. As shown in step (a), after depositing the polycrystalline silicon germanium thin film formed as described above on the glass substrate 300, it was heated with hydrogen gas for 10 minutes.
pH, gas diluted to 0 voJ, ppm (hereinafter p,
H, (100)/H2) is Gea4 and EliH
The gases were flowed into the Pel Jar 301 at a molar ratio of 5 x io-3 to the total amount of the four gases, and the pressure inside the Pel Jar 301 was adjusted to 0.12 Torr to perform glow discharge. A single layer 402 doped with phosphorus was formed to a thickness of 0.05μ (step (b)).

次に工程(C)の様にフォトエツチング(でより2層4
02をソース電極406の領域及びドレイン電極404
の領域を除いて除去した。次にゲート絶縁膜を形成すべ
く、ペルジャー501内に再び上記の基板がアノード側
の加熱ホルダー302に装着された。多結晶シリコン・
ゲルマニウム薄膜を作製する場合と同様にペルジャー6
01が排気され、基板温度Tsを250Cとして純度約
100チのNH3ガスをマスフローコントローフ −3
05で20 SOCM 、 H2で10 vol、 %
に稀釈されだS:LH4(以下S:LH4(1o )/
 H2と記す)をマスンローコントロ−7−308で5
800Mに各々コントロールして導入し、グロー放電を
生起させて5iNH膜405を0.25μの厚さに堆積
させた(工程(d))。
Next, as shown in step (C), photo-etching (with 2 layers 4
02 in the region of the source electrode 406 and the drain electrode 404
removed except for the area. Next, in order to form a gate insulating film, the above-mentioned substrate was again mounted on the heating holder 302 on the anode side inside the Pelger 501. Polycrystalline silicon・
Pelger 6 as in the case of producing a germanium thin film.
01 is exhausted, the substrate temperature Ts is set to 250C, and NH3 gas with a purity of about 100% is mass flow controlled -3
20 SOCM in 05, 10 vol, % in H2
S:LH4 (hereinafter S:LH4(1o)/
(denoted as H2) was set to 5 with Massonro control 7-308.
The 5iNH film 405 was deposited to a thickness of 0.25 μm by introducing the 5iNH film 405 to a thickness of 0.25 μm by introducing the 5iNH film 405 to a thickness of 0.25 μm by controlling the introduction of the 5iNH film 405 to a thickness of 800M and generating a glow discharge (step (d)).

次にフォトエツチング工程によりソース電極406及び
ドレイン電極404゛用のコンタクトホール406−1
 、406−2をあけ(工程(e))、その後、5iN
H膜405全面にAJ?を蒸着して電極膜407を形成
(工程(f) ) した後、フォトエツチング工程によ
シミ極膜407を加工してソース電極用取り出し電極4
08、ドレイン電極用取り出し電極409及びゲート電
極410を形成した(工程(g))。この後、I12雰
囲気中で250Cの熱処理を行なった。
Next, a contact hole 406-1 for the source electrode 406 and drain electrode 404' is formed by a photo-etching process.
, 406-2 (step (e)), then 5iN
AJ on the entire surface of H film 405? After forming the electrode film 407 by vapor deposition (step (f)), the stain electrode film 407 is processed by a photo-etching process to form the source electrode extraction electrode 4.
08, a drain electrode extraction electrode 409 and a gate electrode 410 were formed (step (g)). After that, heat treatment was performed at 250C in an I12 atmosphere.

以上の条件と工程に従って形成されたTPT(チャンネ
ル長L:20μ、チャンネル幅W=650μ)は安定で
良好な特性を示した。
The TPT (channel length L: 20μ, channel width W=650μ) formed according to the above conditions and steps showed stable and good characteristics.

この様に試作されたTFTのVD−より特性曲線の例を
第8図に示した。第8図かられかる様にvG=10V(
7)、!:きIv =6.8 X 10 ’Aテ、Sす
、vG=Q7のとき、都=4X10−8Aであp、かつ
閾値電圧は5.7vであった。又、通常MO8、TPT
デバイスで行なわれているvG−凸曲線の直線部から求
めたμeffは55L1rL2/V、Becと移動度の
大きな種々の駆動回路が形成できる良好なトランジスタ
ー特性を有するTPTが得られた。
FIG. 8 shows an example of the VD- characteristic curve of the TFT prototyped in this manner. As shown in Figure 8, vG=10V (
7),! : When Iv = 6.8 x 10'A, S, and vG = Q7, the voltage was 4 x 10-8A, and the threshold voltage was 5.7V. Also, usually MO8, TPT
The μeff determined from the straight line portion of the vG-convex curve used in the device was 55L1rL2/V, Bec, and a TPT with good transistor characteristics capable of forming various drive circuits with high mobility was obtained.

このTPTの安定性を調べるため、ゲートにDC′成圧
で%o”40Vを印加し続けてよりの変化を1000時
間に亘って連続測定を行ったところ、よりの変化はなく
、かつT’FTの経時変化前後の閾値電圧の変化ΔVT
Hもなく、TPTの安定性は極めて良好だった。又、経
時変化後のTFT特性VD−より + vG−より等も
経時変化測定前と測定結果は変らず1μeffも55 
Cm2/■、8eCと同一であった。
In order to investigate the stability of this TPT, we continuously applied 40V of DC' pressure to the gate and measured the change in torque over a period of 1000 hours.There was no change in twist, and T' Change in threshold voltage before and after FT change over time ΔVT
There was no H, and the stability of TPT was extremely good. In addition, the TFT characteristics after aging change from VD- + vG-, etc., the measurement results are unchanged from before the aging change measurement, and 1 μeff is 55.
It was the same as Cm2/■, 8eC.

本実施例で示された様に0.2 at、 %の量の水素
原子を含む多結晶シリコン・ゲルマニウム薄膜でその主
要部を構成したTPTは極めて高性能なトランジスター
であることがわかった。
As shown in this example, the TPT whose main part was composed of a polycrystalline silicon germanium thin film containing 0.2 at.% hydrogen atoms was found to be an extremely high performance transistor.

実施例 2 実施例1と同様の手順によってRF /<ワー40y 
、 5i−H4(1)/H2の流量40 Sec!M 
、 GeH4(1)/H2の流量201EOc!M 、
 B2H6(1oo)/H2の流量30SOOM 、圧
力Q、Q 2 Torrの条件でバイコールガラス基板
上に多結晶シリコン・ゲルマニウム膜を作成した。基板
温度は200〜700υに亘って50cおきに設定し膜
厚は0.5μ厚となる様に作成した。そして、各々の多
結晶シリコン・ゲルマニウム膜の水素原子量を測定し、
又これら作成した膜を用いて実施例1と同様の方法によ
って作成したTPT (試料層1−1〜1−11)の各
々のμ。ffを第1表に示す。
Example 2 RF/<war 40y
, 5i-H4(1)/H2 flow rate 40 Sec! M
, GeH4(1)/H2 flow rate 201EOc! M,
A polycrystalline silicon germanium film was formed on a Vycor glass substrate under conditions of a flow rate of B2H6(1oo)/H2 of 30 SOOM, a pressure of Q, and Q 2 Torr. The substrate temperature was set at intervals of 50c over a range of 200 to 700υ, and the film thickness was 0.5μ. Then, the amount of hydrogen atoms in each polycrystalline silicon germanium film was measured,
Also, μ of each of TPT (sample layers 1-1 to 1-11) prepared by the same method as in Example 1 using these prepared films. ff is shown in Table 1.

第1表から判る様に水素原子量が3at、%を越えるも
の又はCLO1at、 %未満のものはμeffが10
0 cm2/V、eec以下であり、■Dの経時変化及
びΔVTHが比較的大きく又特性の安定も劣っている。
As can be seen from Table 1, those with a hydrogen atomic weight of more than 3at.% or less than CLO1at.% have a μeff of 10.
0 cm2/V, eec or less, ■D change over time and ΔVTH are relatively large, and the stability of characteristics is also poor.

実施例 3 次に実施例3を第5図によって詳細に説明する。Example 3 Next, Example 3 will be explained in detail with reference to FIG.

先ず本実施例1と同様に準備されたコーニング47os
qガラス基板500を2 X 10 ”Torrまで減
圧することができる真空槽501内の基板ホルダー50
2に装着し、真空槽501内の圧力が4 X 10 ”
jorr以下の圧力になるまで減圧した後ヒーター50
6により基板温度を500υに設定した。続いて電子銃
504を10にVの加速電圧で動作させ、発射される電
子ビームをシリコン蒸発体505に照射させ、更に電子
銃504′を10にVの加速′電圧で動作させ、発射さ
れる電子ビームをゲルマニウム蒸発体505′に照射さ
せ、引続いてクヌードセンセル509を加熱ヒーター 
511によって加熱し、硼素510をクヌードセンセル
509から蒸発させ、シャッター512及びシャッター
507 、507’を開き基板500に0.5μ厚の膜
厚が形成されるよう水晶振動子膜厚計506でコントロ
ールして多結晶シリコン・ゲルマニウム膜を形成した。
First, Corning 47os prepared in the same manner as in Example 1
q Substrate holder 50 in a vacuum chamber 501 that can reduce the pressure of the glass substrate 500 to 2×10” Torr
2, the pressure inside the vacuum chamber 501 is 4 x 10''
After reducing the pressure until the pressure is below jorr, the heater 50
6, the substrate temperature was set at 500υ. Next, the electron gun 504 is operated at an accelerating voltage of 10 V to irradiate the silicon evaporator 505 with the emitted electron beam, and the electron gun 504' is further operated at an accelerating voltage of 10 V to emit the electron beam. The germanium evaporator 505' is irradiated with an electron beam, and then the Knudsen cell 509 is heated with a heater.
511 to evaporate boron 510 from the Knudsen cell 509, and open the shutters 512, 507 and 507' to form a film thickness of 0.5μ on the substrate 500 using a crystal resonator film thickness gauge 506. A polycrystalline silicon germanium film was formed under controlled conditions.

このときの蒸着中の圧力は1.5×10  Torr 
s蒸着速度は1.4 A/seaであった。
The pressure during vapor deposition at this time was 1.5×10 Torr
s deposition rate was 1.4 A/sea.

こうして得られた試料を試料3−1とする。The sample thus obtained is designated as sample 3-1.

次に、同様に準備されたコーニング+7059ガラス基
板500を基板ホルダー502に固定し、真を槽501
内の圧力が4 X 10 ” TorrJ2J、’fの
圧力になるまで減圧した後、高純度水素ガス(99,9
99%)ヲバリアブルリークバルプ508により真空槽
501内に導入し、槽内圧力を2 X 10 ’Tor
rにした後基板温度を500むに設定し、シリコンゲル
マニウム及び硼素を試料3−1作成の場合と同様に蒸発
させ膜形成を行った。そのときの膜形成速度は1 、4
 X/sθCになる様コントロールし、0.5μ厚の多
結晶シリコン・ゲルマニウム膜を形成した。これで得ら
れた試料を試料3−2とする。
Next, a similarly prepared Corning +7059 glass substrate 500 is fixed to the substrate holder 502, and the stem is placed in the bath 501.
After reducing the pressure inside the tank to a pressure of 4 x 10” TorrJ2J,'f, high-purity hydrogen gas (99,9
99%) was introduced into the vacuum chamber 501 by the variable leak valve 508, and the pressure inside the chamber was increased to 2 x 10' Torr.
After setting the temperature to r, the substrate temperature was set to 500 μm, and silicon germanium and boron were evaporated to form a film in the same manner as in the case of creating sample 3-1. At that time, the film formation rate was 1,4
A polycrystalline silicon/germanium film with a thickness of 0.5 μm was formed by controlling the temperature to be X/sθC. The sample thus obtained is designated as sample 3-2.

試料6−1.3−2について各々多結晶シリコン・ゲル
マニウム薄膜に含有する水素量を測定し、又各々の試料
を用いて実施例1と同様の方法によって作成したTPT
の各々について測定したμeff * IDの経時変化
、閾値電圧の変化量AvTHの結果を第2表に示した。
The amount of hydrogen contained in the polycrystalline silicon germanium thin film was measured for each of Samples 6-1 and 3-2, and TPT was prepared using the same method as in Example 1 using each sample.
Table 2 shows the results of the change over time in μeff*ID and the amount of change in threshold voltage AvTH measured for each of the above.

第2表かられかるように多結晶シリコン・ゲルマニウム
薄膜に含有する水素量が試料6−1は(Lo、1.at
、チ未満と少なく、試料3−2では0.3at、裂含有
していた。
As shown in Table 2, the amount of hydrogen contained in the polycrystalline silicon germanium thin film is (Lo, 1.at
, less than 1, and sample 3-2 contained 0.3 at.

この為、作製されたTPTの実効キャリアー移動度μθ
ffは試料3−2が試料3−1に比べて大きく、TPT
の安定性も試料3−2の方が良好で、TFT用の千尋体
層として好ましいことが判った。
For this reason, the effective carrier mobility μθ of the fabricated TPT is
ff is larger in sample 3-2 than in sample 3-1, and TPT
Sample 3-2 also had better stability, and was found to be preferable as a chihiromorphic layer for TFT.

第  2  表 実施例 4 本発明を第6図に示すイオンブレーティング堆積装置を
用いて作製した多結晶シリコン・ゲルマニウム薄膜を用
いて作製したTPTについて詳述する。
Table 2 Example 4 A TPT fabricated using a polycrystalline silicon germanium thin film fabricated using the ion blasting deposition apparatus according to the present invention shown in FIG. 6 will be described in detail.

先ず減圧可能な堆積室603内に多結晶シリコンゲルマ
ニウムのシリコン蒸発体406をボート607内に置き
、ゲルマニウム蒸発体606′をボー) 607’内に
置き、コーニング+7059ガラス基板を支持体611
−1,611−2に設置し堆積室603内の圧力を約I
 X 10−’ Torrになるまで排気した後、ガス
導入管605を通じて純度99.999チのH2ガスを
水素分圧pHが1’X 10 ’Torrになる様にし
て堆積室603内に導入した。使用したガス導入管60
5は内径2關の先のループ状の部分にガス吹出し口が直
径0.5關の孔が2(m間隔で開いているものを用いた
First, a polycrystalline silicon germanium silicon evaporator 406 is placed in a boat 607 in a deposition chamber 603 that can be depressurized, a germanium evaporator 606' is placed in a boat 607', and a Corning +7059 glass substrate is placed in a support 611.
-1,611-2, and the pressure inside the deposition chamber 603 is approximately I
After exhausting until the pressure reached X 10-' Torr, H2 gas with a purity of 99.999 cm was introduced into the deposition chamber 603 through the gas introduction pipe 605 so that the hydrogen partial pressure pH became 1'X 10' Torr. Gas introduction pipe used 60
No. 5 used a gas outlet in which two holes with a diameter of 0.5 mm were opened at an interval of 2 meters in a loop-shaped portion at the end of the inner diameter.

次に高周波コイル610(直径5關)に1!1.51s
MH2の高周波を出力200Wになる様印加し、高周波
コイル610内部分に高岡波グ2ズマ雰囲気を形成した
Next, apply 1!1.51s to the high frequency coil 610 (diameter 5 degrees).
A high frequency MH2 wave was applied with an output of 200 W to form a Takaoka Hagusma atmosphere inside the high frequency coil 610.

又、支持体611−1,611−2は回転させ乍ら加熱
装置612を動作状態にしてガジス基板を450Cに加
熱しておいた。
Further, while the supports 611-1 and 611-2 were being rotated, the heating device 612 was activated to heat the Gazis substrate to 450C.

次にシリコン蒸発体606、ゲルマニウム蒸発体606
′にそれぞれエレクトロガン608,60B’よりエレ
クトロンビームを照射シシリコン、ゲルマニウムを夫々
加熱し、シリコン粒子、ゲルマニウム粒子を飛翔させた
。この様にして多結晶シリコン・ゲルマニウムの膜厚を
約0.5μ形成しこれを用いて実施例1と同様な工程で
TPTを作製した(試料4−1)。又、多結晶シリコン
・ゲルマニウム薄膜の形成過程において水素を導入しな
いで膜を形成したものから試料5〜1と同様な方法でT
PTを作製した(試料4〜2)。
Next, silicon evaporator 606 and germanium evaporator 606
The silicon and germanium were heated by irradiating electron beams from electroguns 608 and 60B', respectively, and the silicon particles and germanium particles were made to fly. In this way, a film of polycrystalline silicon germanium was formed to a thickness of about 0.5 μm, and using this film, a TPT was fabricated in the same steps as in Example 1 (Sample 4-1). In addition, in the process of forming a polycrystalline silicon/germanium thin film, the film was formed without introducing hydrogen, and T
PT was produced (Samples 4-2).

この様に作製した試料の各々について測定したμf3 
ff + IDの経時変化、閾値電圧の変化量ΔVTH
の結果を第3表に示す。
μf3 measured for each of the samples prepared in this way
ff + ID change over time, threshold voltage change amount ΔVTH
The results are shown in Table 3.

第3表から判るように試料5−1は恥の経時変化が全く
なく〈μeffも32 crIL2/V−8と大きく良
好なトランジスター特性を示した。
As can be seen from Table 3, sample 5-1 showed no change in temperature over time, and exhibited good transistor characteristics with μeff of 32 crIL2/V-8.

第  3  表 実施例 5 次に第7図を用いてスパッター法で多結晶シリコン・ゲ
ルマニウム薄膜を形成した実施例について詳述する。
Table 3 Example 5 Next, an example in which a polycrystalline silicon germanium thin film was formed by sputtering will be described in detail with reference to FIG.

実施例1と同様に準備されたコーニング≠7059ガラ
ス基板700をペルジャー701内の上部アノード側の
基板加熱ホルダー702に密着して固定し、f部カソー
ド706の電極板上に基板と対向する様に多結晶シリコ
ン板(図示されていない;純度99.999%)及び下
部カソード707の電極板上に基板と対向する様に多結
晶ゲルマニウム板(図示されていない99.999チ)
を設置した。ペルジャー701内圧力が1×10’To
rrになるまで拡散ポンプ709で排気し、基板加熱ホ
ルダー702を加熱して基板700の表面温度を400
υに保った。
A Corning≠7059 glass substrate 700 prepared in the same manner as in Example 1 was fixed in close contact with the substrate heating holder 702 on the upper anode side in the Pelger 701, and placed on the electrode plate of the f section cathode 706 so as to face the substrate. A polycrystalline silicon plate (not shown; purity 99.999%) and a polycrystalline germanium plate (not shown, 99.999%) are placed on the electrode plate of the lower cathode 707 to face the substrate.
was installed. The internal pressure of Pelger 701 is 1×10'To
Evacuate with the diffusion pump 709 until the temperature reaches rr, and heat the substrate heating holder 702 to raise the surface temperature of the substrate 700 to
I kept it at υ.

B2H6(100)/[(2ガスをマスフローコントロ
ーラー716によってs 5canの流量で、更にH2
ガスをマスフローコントローフ −714によっテロ0
SC(!Mの流量でペルジャー701内に環状ガス導入
管712によって導入し、メインバルブ711を絞って
ペルジャー701の内圧を隔膜式圧力計705により0
.01 Tourに設定した。
B2H6(100)/[(2 gas is supplied by mass flow controller 716 at a flow rate of 5 can, and H
Mass flow control of gas - 0 terrorist attacks due to 714
The gas is introduced into the Pel jar 701 through the annular gas introduction pipe 712 at a flow rate of SC (!
.. 01 Tour.

ペルジャー内圧が安定してから、下部カソード電極70
6に1156 MH2の高周波電界を電源708によっ
て電圧5.5KVを印加し、かつ下部カソード電極70
7に15.56 MH2の高周波電界を電源709によ
って・電圧2.5に■を印加してカン−、ド電極706
,707上の多結晶シリコン板及び多結晶ゲルマニウム
板とアノード(基板加熱ホルダー ) 702間にグロ
ー放電を生起させ、ガラス基板700にp型多結晶シリ
コン・ゲルマニウム薄膜を載積させた。このとき形成さ
れた膜の膜厚は0.55μであった。又、このとき形成
された多結晶シリコン・ゲルマニウム薄膜に含有された
水素原子量は1.6at、チであった。
After the Pelger internal pressure stabilizes, the lower cathode electrode 70
A high frequency electric field of 1156 MH2 was applied to the lower cathode electrode 70 at a voltage of 5.5 KV by the power source 708.
A high frequency electric field of 15.56 MH2 is applied to the can and do electrodes 706 by applying a voltage of 2.5 to the power source 709.
, 707 and the anode (substrate heating holder) 702, a p-type polycrystalline silicon/germanium thin film was deposited on the glass substrate 700. The thickness of the film formed at this time was 0.55μ. Further, the amount of hydrogen atoms contained in the polycrystalline silicon germanium thin film formed at this time was 1.6 at.

得られた試料を用いて実施例1と同様の方法によって作
製したTPTのμ。ffは35c11L2/V、6θ。
μ of TPT produced by the same method as in Example 1 using the obtained sample. ff is 35c11L2/V, 6θ.

で恥の経時変化は0.1%未満、閾値電圧の変化量ΔV
THがOvと安定で良好なトランジスター特性を示すT
PTが得られた。
The change in shame over time is less than 0.1%, and the change in threshold voltage is ΔV.
T exhibits stable and good transistor characteristics with TH of Ov.
PT was obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の半導体素子の構造を説明する為の模式
的説明図、第2図ぽ本発明の半導体素子の特性を測定す
る為の回路を模式的に示した説明図、第6図、第5図、
第6図、第7図は各々本発明に係わる半導体膜作製装置
の例を説明する為の模式的説明図、第4図は本発明の半
導体素子を作製する為の工程を模式的に説明する為の工
程図、第8図は本発明の半導体素子のVD−より特性の
一例を示す説明図である。 101・・・基板 102・・・薄膜半導体層 106・・・ソース電極 10グ・・・ドレイン電極 105・・・絶縁層 106・・・ゲート電極 107.108・・・♂層
Fig. 1 is a schematic explanatory diagram for explaining the structure of the semiconductor device of the present invention, Fig. 2 is an explanatory diagram schematically showing a circuit for measuring the characteristics of the semiconductor device of the present invention, and Fig. 6 , Figure 5,
6 and 7 are schematic explanatory diagrams for explaining examples of semiconductor film manufacturing apparatuses according to the present invention, respectively, and FIG. 4 is a schematic explanatory diagram for explaining steps for manufacturing a semiconductor element of the present invention. FIG. 8 is an explanatory diagram showing an example of the VD- characteristics of the semiconductor device of the present invention. 101...Substrate 102...Thin film semiconductor layer 106...Source electrode 10G...Drain electrode 105...Insulating layer 106...Gate electrode 107.108...♂ layer

Claims (1)

【特許請求の範囲】[Claims] 5 atomic %以下の水素原子を含有する多結晶
シリコン・ゲルマニウム薄膜中導体層でその主要部が構
成されている事を特徴とする半導体素子。
1. A semiconductor device characterized in that its main portion is constituted by a conductor layer in a polycrystalline silicon germanium thin film containing 5 atomic % or less of hydrogen atoms.
JP57231521A 1982-09-02 1982-12-29 Semiconductor element Pending JPS59124163A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP57231521A JPS59124163A (en) 1982-12-29 1982-12-29 Semiconductor element
DE19833331601 DE3331601A1 (en) 1982-09-02 1983-09-01 SEMICONDUCTOR DEVICE
US06/937,432 US4740829A (en) 1982-09-02 1986-12-03 Semiconductor device having a thin layer comprising germanium atoms as a matrix with a restricted range of hydrogen atom concentration

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57231521A JPS59124163A (en) 1982-12-29 1982-12-29 Semiconductor element

Publications (1)

Publication Number Publication Date
JPS59124163A true JPS59124163A (en) 1984-07-18

Family

ID=16924782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57231521A Pending JPS59124163A (en) 1982-09-02 1982-12-29 Semiconductor element

Country Status (1)

Country Link
JP (1) JPS59124163A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60254661A (en) * 1984-05-14 1985-12-16 エナージー・コンバーシヨン・デバイセス・インコーポレーテツド Improved thin film field effect transistor compatible with integrated circuit and method of producing same
JPH0823099A (en) * 1994-03-14 1996-01-23 Natl Science Council Of Roc Polycrystalline quality thin film transistor and its preparation
US6566175B2 (en) 1990-11-09 2003-05-20 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing gate insulated field effect transistors

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5550663A (en) * 1978-10-07 1980-04-12 Shunpei Yamazaki Semiconductor device and method of fabricating the same
JPS55154726A (en) * 1979-05-22 1980-12-02 Shunpei Yamazaki Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5550663A (en) * 1978-10-07 1980-04-12 Shunpei Yamazaki Semiconductor device and method of fabricating the same
JPS55154726A (en) * 1979-05-22 1980-12-02 Shunpei Yamazaki Manufacture of semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60254661A (en) * 1984-05-14 1985-12-16 エナージー・コンバーシヨン・デバイセス・インコーポレーテツド Improved thin film field effect transistor compatible with integrated circuit and method of producing same
JPS60254660A (en) * 1984-05-14 1985-12-16 エナージー・コンバーシヨン・デバイセス・インコーポレーテツド Thin film field effect transistor and method of producing same
US6566175B2 (en) 1990-11-09 2003-05-20 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing gate insulated field effect transistors
US7507615B2 (en) 1990-11-09 2009-03-24 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing gate insulated field effect transistors
JPH0823099A (en) * 1994-03-14 1996-01-23 Natl Science Council Of Roc Polycrystalline quality thin film transistor and its preparation

Similar Documents

Publication Publication Date Title
JP2880322B2 (en) Method of forming deposited film
KR100469134B1 (en) Inductive plasma chemical vapor deposition method and amorphous silicon thin film transistor produced using the same
US4740829A (en) Semiconductor device having a thin layer comprising germanium atoms as a matrix with a restricted range of hydrogen atom concentration
US5132754A (en) Thin film silicon semiconductor device and process for producing thereof
US5236850A (en) Method of manufacturing a semiconductor film and a semiconductor device by sputtering in a hydrogen atmosphere and crystallizing
KR100797018B1 (en) Semiconductor thin film, semiconductor device employing the same, methods for manufacturing the same and device for manufacturing a semiconductor thin film
US5965904A (en) Semiconductor device comprising silicon semiconductor layer
US6905920B2 (en) Method for fabrication of field-effect transistor to reduce defects at MOS interfaces formed at low temperature
WO1992014268A1 (en) Polysilicon thin film transistor
JPH0620122B2 (en) Semiconductor element
Kondo et al. Novel aspects in thin film silicon solar cells–amorphous, microcrystalline and nanocrystalline silicon
JPH04225571A (en) Thin-film transistor
CN107104151A (en) A kind of double grid electrode metal oxide thin-film transistor and preparation method thereof
US20070077735A1 (en) Element of low temperature poly-silicon thin film and method of making poly-silicon thin film by direct deposition at low temperature and inductively-coupled plasma chemical vapor deposition equipment therefor
JPH06224431A (en) Thin-film transistor and liquid crystal display panel
JPH0465120A (en) Formation of deposition film
JPS59124163A (en) Semiconductor element
KR19990013304A (en) How to crystallize amorphous membrane
JPH021367B2 (en)
Oda et al. High quality a-Si: H films and interfaces prepared by VHF plasma CVD
JPS58123772A (en) Semiconductor element
He et al. Structural and Electrical Properties of n-Type Poly-Si Films Prepared by Layer-by-Layer Technique
JP3130661B2 (en) Thin film transistor and method of manufacturing the same
JP3130660B2 (en) Thin film transistor and method of manufacturing the same
KR19990023052A (en) How to crystallize amorphous membrane