JPS59124123A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS59124123A
JPS59124123A JP57234283A JP23428382A JPS59124123A JP S59124123 A JPS59124123 A JP S59124123A JP 57234283 A JP57234283 A JP 57234283A JP 23428382 A JP23428382 A JP 23428382A JP S59124123 A JPS59124123 A JP S59124123A
Authority
JP
Japan
Prior art keywords
recess part
layer
semiconductor film
substrate
annealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57234283A
Other languages
Japanese (ja)
Inventor
Nobuhiro Shimizu
信宏 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP57234283A priority Critical patent/JPS59124123A/en
Publication of JPS59124123A publication Critical patent/JPS59124123A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Optics & Photonics (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To improve crystallinity, and to obtain an FET having the favorable characteristic by a method wherein a recess part is formed on the surface of a substrate consisting of an insulating material, a semiconductor film is grown on the whole surface containing the recess part thereof, annealing is performed to bury a part of the semiconductor film in the recess part, and a thin film transistor is formed in the place thereof. CONSTITUTION:A recess part 10 is provided according to etching, etc., in an insulating substrate 1 consisting of quartz, Pyrex glass, etc., and a semiconductor layer 2 of amorphous Si or polycrystalline Si is grown on the whole surface containing the recess part thereof. Then the layer 2 is selectively etched to leave the layer 2 only on the recess part 10, while at this time, the surface of the layer 2 burying the recess part 10 is not flattened, and protrusion parts 2a, 2b are generated at the edge parts. Therefore, the protrusion parts are molten according to the annealing of a beam to remove the protrusion parts 2a, 2b, and at the same time, the layer 2 is buried satisfactorily in the recess part 10 to enhance crystallinity. After then, a thin film transistor is formed in the layer 2 thereof, and a gate electrode 4, and a drain electrode 5 and a source electrode 6 interposing the gate electrode between them are provided on the surface of the layer thereof interposing an insulating film 3 between them.

Description

【発明の詳細な説明】 不発明は、絶縁材料から成る基板上に段差の小さい半導
体Ｎ膜トランジスタ（ＴＰＴ）を形成する製造方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a manufacturing method for forming a semiconductor N-film transistor (TPT) with small steps on a substrate made of an insulating material.

従来、この種のＴＰＴは、表面が平坦な基板を使用して
いた。第１図に従来の平面基板上に作成したＴＰＴの一
例を断面図で示す。１は絶縁基板、２はビームアニール
した半導体膜、３は絶縁膜、４．５および６はそれぞれ
ゲート、ソーヌ、ドレイン邂極である。第１図に示すよ
うに１°ＦＴに対する表面の段差が犬さく、荷にゲート
電極４においては、基板１からの段差が太さいため断線
を起こしやすく、ま′ｆＣ牛導体模２はビームアニール
しても基板１が平坦であるため十分結晶性を同上させる
ことが困難であった。Conventionally, this type of TPT has used a substrate with a flat surface. FIG. 1 shows a cross-sectional view of an example of TPT fabricated on a conventional flat substrate. 1 is an insulating substrate, 2 is a semiconductor film subjected to beam annealing, 3 is an insulating film, and 4.5 and 6 are gate, sone, and drain electrodes, respectively. As shown in Fig. 1, the surface level difference for 1°FT is quite large, and the gate electrode 4 on the load is easy to break because the level difference from the substrate 1 is large, and the conductor pattern 2 is beam annealed. However, since the substrate 1 is flat, it is difficult to achieve sufficient crystallinity.

本発明は、上記のような従来の欠点を除去するためにな
されたものであり、基板上に凹部を設ける事でＴＰＴの
歩留シを上げ、結晶性を上げてＴＦ’Ｔの特性を向上さ
せる製造方法を提供することを目的としたものである。The present invention was made to eliminate the above-mentioned drawbacks of the conventional technology, and by providing recesses on the substrate, the yield of TPT is increased, and the crystallinity is increased to improve the characteristics of TF'T. The purpose of this invention is to provide a manufacturing method that allows

以下図面によって本発明の半導体装置の製造方法を詳述
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to the present invention will be explained in detail below with reference to the drawings.

第２図（ａ）は、絶縁基板またとえば石英やパイレツク
ス等のガラス基板に、四部１０を設ける工程であシ、フ
ォトリングラフィによるウエントエッチングおよびグラ
ズマまたはイオン等によるドライエンチングによって形
成することができ、その寸法と個数は、目標とする設計
値に合わせて自由に変えることができる。FIG. 2(a) shows a step of providing the four parts 10 on an insulating substrate, such as a glass substrate made of quartz or pyrex, and may be formed by wet etching using photolithography and dry etching using glazma or ions. The dimensions and number can be changed freely according to the target design values.

第２図（１））は、基板１上に均一に半導体膜２を成長
させる工程である。たとえば、アモルファスシリコン（
ａ８１）や多結晶シリコン等を形成することが考えられ
る。ここではアモルファスシリコンをプラズマＣＶＤ法
を用いて成長させる場合を説明する。原料はおもにシラ
ン（ＳｉＨ４）を使い、成長温度は室温から約５００℃
の間で行う。FIG. 2(1)) is a step in which the semiconductor film 2 is grown uniformly on the substrate 1. For example, amorphous silicon (
A81), polycrystalline silicon, or the like may be formed. Here, a case will be described in which amorphous silicon is grown using a plasma CVD method. The raw material is mainly silane (SiH4), and the growth temperature is from room temperature to about 500℃.
Do it between.

次の工程は、凹部の牛導体膜會ビームアニールし、結晶
性を上げて表面を平坦にする工程である。The next step is beam annealing of the conductor film in the recesses to improve crystallinity and flatten the surface.

この工程には、半導体膜を凹部のみ残して他を除去し、
ビームアニールする場合（前者）と、半導体膜はそのま
までビームアニールする場合（後者）とが考えられる。This process involves removing the rest of the semiconductor film, leaving only the recessed parts.
There are two possible cases: beam annealing (the former) and beam annealing with the semiconductor film as it is (the latter).

始めに前者について説明する。この場合は、第２図（ｂ
）に続く工程として第２図（ｂ）に示す半導体膜２と基
板１の凹部１０の大きさ及び深さとの関係によシ次の３
つの工程ＡとＢとＣがある。The former will be explained first. In this case, Figure 2 (b
), the following three steps are performed depending on the relationship between the size and depth of the semiconductor film 2 and the recess 10 of the substrate 1 shown in FIG. 2(b).
There are three processes A, B, and C.

次にＡの工程を第２図（Ｃ）と（ｄ）に示す。この場合
半導体膜２の厚さと、四部の深さとはほぼ等しい。Next, the step A is shown in FIGS. 2(C) and 2(d). In this case, the thickness of the semiconductor film 2 and the depth of the four parts are approximately equal.

（第２＠ｏ）参照）聾ず、第２図（ｃ）に示すように、
均一に形成した半導体膜の凹部以外を選択エツチングす
る。すなわち、アモルファスシリコン２をエンチングす
−る場合、基板１の四部１ｏのみレジストを残しその後
ＣＦ４　などのガスを使うズラズマドライエッチンググ
ロセスを用いて＃−１ｓａの凹部以外を選択エンチング
する。この時、レジストのマスクの多少のずれは間鴇す
い。その後アモルファスシリコン２の上のレジストをエ
ツチングし、アモルファスシリコン２のみ残す。この段
階では８２図（ｃ）　７）−られかるように半導体膜２
（アモルファスシリコン）は、基板１の凹部１ｏの端に
凸部２ａと２ｂをもち、基板１０表面は平坦にはならな
い。(See 2nd @o)) Deaf, as shown in Figure 2(c),
Selective etching is performed on areas other than the concave portions of the uniformly formed semiconductor film. That is, when etching the amorphous silicon 2, the resist is left only on the four parts 1o of the substrate 1, and then the parts other than the recess #-1sa are selectively etched using a plasma dry etching process using a gas such as CF4. At this time, slight deviations of the resist mask may occur. Thereafter, the resist on the amorphous silicon 2 is etched, leaving only the amorphous silicon 2. At this stage, as shown in Figure 82(c) 7), the semiconductor film 2
(Amorphous silicon) has convex portions 2a and 2b at the ends of the concave portion 1o of the substrate 1, and the surface of the substrate 10 is not flat.

第２図（ｄ）は、第２図＜ｃ＞に示すように選択エンチ
ングによって残った半導体膜２をビームアニールして溶
融して半導体膜２の端の凸部２ａと２ｂをなくして基に
１の表面を平坦にしたものである。In FIG. 2(d), as shown in FIG. 2<c>, the semiconductor film 2 remaining by selective etching is beam-annealed and melted to eliminate the protrusions 2a and 2b at the ends of the semiconductor film 2, and to form a base. 1 with a flat surface.

この場合、基板１の凹部１０の端によるグラフオエピタ
キシーの効果にニジ、ビームアニールした半導体２は、
第１図に示す平面基板１の上の半導体膜２をビームアニ
ールしたものに比べ結晶性が良く、単結晶に近くなる。In this case, due to the effect of graphoepitaxy caused by the edge of the recess 10 of the substrate 1, the beam annealed semiconductor 2 is
The crystallinity is better than that obtained by beam annealing the semiconductor film 2 on the flat substrate 1 shown in FIG. 1, and it becomes close to a single crystal.

上述の効果により半導体膜２は第５図に示すように基板
１の四部を完全に埋めており、基板１の表面は完全に平
坦になっている。その後第６図に示すように半導体膜２
にＴＰＴが形成される。Due to the above-mentioned effect, the semiconductor film 2 completely fills all four parts of the substrate 1, as shown in FIG. 5, and the surface of the substrate 1 becomes completely flat. After that, as shown in FIG.
TPT is formed.

次にＢの工程を第３図（ａ）と（ｂ）に示す。この場合
半導体膜２の厚さｄ：凹部の深さより小さい。（第５図
（ａ）参照ｊ）Ｉノ 第５図（ａ）でアニールを行って第５１凶（ｂ）が得ら
れる。このとき第３図（ｂ）に示すように基板１の凹部
１０を半導体膜２が完全に埋めておらず凹部が少し残る
。その後第６図に示すように半導体膜２にＴＰＴが作ら
れる。更ｖｃＣの工程を第４図（ａ）と（ｂ）に示す。Next, step B is shown in FIGS. 3(a) and 3(b). In this case, the thickness d of the semiconductor film 2 is smaller than the depth of the recess. (Refer to FIG. 5(a)) I No. 51(b) is obtained by performing annealing in FIG. 5(a). At this time, as shown in FIG. 3(b), the semiconductor film 2 does not completely fill the recess 10 of the substrate 1, and a small recess remains. Thereafter, a TPT is formed on the semiconductor film 2 as shown in FIG. The process of further vcC is shown in FIGS. 4(a) and 4(b).

この場合半導体膜２の厚さは凹部の深さより太きい。（
第４１Ｊ（ａ）参照）第４図（ａ）でアニールを行って
第４　ｊ！ＺＪ（ｂ）が得られる。このとき第４図（ｂ
）に示すように基板１の凹部１０以上に半導体膜２があ
り、やや凸状になっている。ビームアニールの方法とし
て（ハ、たとえば局所加熱方式のＡｒ。In this case, the thickness of the semiconductor film 2 is greater than the depth of the recess. (
(See Section 41J(a)) Perform annealing as shown in FIG. 4(a) and proceed to Section 4j! ZJ(b) is obtained. At this time, Fig. 4 (b
), the semiconductor film 2 is located above the recess 10 of the substrate 1 and has a slightly convex shape. As a beam annealing method (e.g. local heating Ar).

ＹＡＧレーザｌどを用いたアニール、１）辻は電子ビー
ムアニールなどがある。全木刀ｎ熱方式としては、ヒー
タアニール、ラングアニールなどがある。Annealing using a YAG laser, etc., and 1) electron beam annealing are available. Examples of the all-wooden heat method include heater annealing and rung annealing.

このあと第６図に示すように半導体膜２にＴＴＩ’Ｔが
作られる。Thereafter, TTI'T is formed in the semiconductor film 2 as shown in FIG.

次に後者の場合、すなわち第２図（ｂ）の半導体膜２を
選択エンチングせずビームアニールする工程を説明する
。第５図（ａ）は絹２図（１））において凹部１ａが深
い場合で、全体加熱方式のビームアニールを行った場合
、半導体＠２全体を浴融し、第５図（ｂ）に示すように
基板１の凹部１０を完全に埋め、表面を平坦にし、結晶
性を良くすることができる。Next, a description will be given of the latter case, that is, the step of beam annealing the semiconductor film 2 shown in FIG. 2(b) without selectively etching it. Figure 5 (a) shows the case where the recess 1a is deep in silk 2 (1)), and when beam annealing using the whole heating method is performed, the entire semiconductor @ 2 is bath melted, as shown in Figure 5 (b). In this way, the recess 10 of the substrate 1 can be completely filled, the surface can be flattened, and the crystallinity can be improved.

なお、アニール後の状態は凹部１０の深さによっては第
５図＜ｂ）の鶏舎以外に前記の掘６図（ｂ）と第４図（
’ｂ）の状態も考えられる。また、第５図（ａ）と第５
図（ｂ）とに示す方式は、前者の方式に比べて、基板１
の凹部１０が深く、数が多く、全体加熱方式のビームア
ニールを行う場合に適する。Note that depending on the depth of the recess 10, the state after annealing may be different from the poultry house shown in Fig. 5<b) to the above-mentioned poultry house shown in Fig. 6(b) and Fig. 4(b).
The situation 'b) is also possible. Also, Figure 5(a) and Figure 5
Compared to the former method, the method shown in FIG.
The recesses 10 are deep and large in number, making it suitable for performing beam annealing using the entire heating method.

第６図は、ビームアニール後平坦になった半導体膜２の
上に作成したＴＰＴを示す。第６図に於いてたとえば半
導体膜２がビームアニールされたアモルファスシリコン
である場合、半導体膜２の中央部に絶縁膜６（たとえば
二酸化ケイ素−１９ｉ−０２）をプラズマＤＶＤ法を用
いて形成する。この場合絶縁膜６の原料としてシラン（
ＳｉＨ２）と酸素ガス（０２）が使用され、また成長温
度としては室温から約５００℃の間の温度が用いられる
。その後生導体１摸２の両端にドレイン電極５とソース
電極６を、絶縁膜３上にゲート電極４をマグネットロン
スパンタ法ヲ用い、アルミニウムとシリコンの合金（Ａ
Ａ−Ｂｉ）で形成する。FIG. 6 shows the TPT formed on the semiconductor film 2 which has become flat after beam annealing. In FIG. 6, for example, when the semiconductor film 2 is made of beam-annealed amorphous silicon, an insulating film 6 (for example, silicon dioxide-19i-02) is formed in the center of the semiconductor film 2 using the plasma DVD method. In this case, silane (
SiH2) and oxygen gas (02) are used, and the growth temperature is between room temperature and about 500°C. Thereafter, a drain electrode 5 and a source electrode 6 were placed on both ends of the raw conductor 1 and 2, and a gate electrode 4 was placed on the insulating film 3 using the magnetron spunter method.
A-Bi).

以上、ここでは単一のＴＰＴについて説明したが、ＴＰ
Ｔは基板上に複数あっても良い。Above, we have explained a single TPT, but the TP
There may be a plurality of T's on the substrate.

本発明は、上記のように絶縁基板上に凹部をもうけて、
半導体膜をビームアニールし、ＴＰＴを作成するため、 ■　ＴＰＴ表面の段差を小さくすることができ、電極の
断線を減少させ、歩留シを上げることができる。The present invention provides a recessed portion on an insulating substrate as described above,
Since the semiconductor film is beam-annealed to create the TPT, (1) the level difference on the TPT surface can be reduced, electrode disconnection can be reduced, and the yield can be increased;

■　基板の凹部によるグラフオエピタキシーの効果によ
シビームアニール時に、結晶性を単結晶に近づけること
ができ、ＴＰＴの電気的特性を向上できる。(2) Due to the effect of graphoepitaxy caused by the concave portions of the substrate, the crystallinity can be made close to that of a single crystal during Sibeam annealing, and the electrical characteristics of TPT can be improved.

■　半導体膜と基板との接触面積が太きいため、ビーム
アニール時に十分なエネルギーを供給でき、結晶性を１
９良くできる。■ Because the contact area between the semiconductor film and the substrate is large, sufficient energy can be supplied during beam annealing, reducing crystallinity to 1.
9 I can do it well.

等の諸効果がある。There are various effects such as.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のＴＰＴの断面図、 第２図（ａ）から第２図（ｄ）及び第６図は本発明の半
導体装置の製造方法の工程順を説明するための断面図で
ある。 第５図（ａ）と（ｂ）及び第４図（ａ）と（ｂ）は、そ
れぞれ第２図（ｂ）から続き第６図に終る鵠÷他の工程
を、示す断面図、 第５図（ａ）と（ｂ）は第２図（ａ）から続き、第６図
に終る他の工程を示す断面図である。 １・・・絶縁基板　　　２・・・半導体膜６・・・絶縁
膜　　　　２ａ、２ｂ・・・凸部４・・・ゲート電極　
　５・・・ドレイン電極６・・・ソース電極　　１０・
・・凹部以　　上 出願人　株式会社　第二精工合 ￥１０ 第２図（の 第３倣α）　　　　　　第３山し）FIG. 1 is a sectional view of a conventional TPT, and FIGS. 2(a) to 2(d) and 6 are sectional views for explaining the process order of the method of manufacturing a semiconductor device of the present invention. FIGS. 5(a) and (b) and FIGS. 4(a) and (b) are sectional views showing the other steps continuing from FIG. 2(b) and ending in FIG. 6, respectively. Figures (a) and (b) are cross-sectional views showing other steps continuing from Figure 2 (a) and ending in Figure 6. 1... Insulating substrate 2... Semiconductor film 6... Insulating film 2a, 2b... Convex portion 4... Gate electrode
5...Drain electrode 6...Source electrode 10.
...Recessed part and above Applicant Daini Seiko Co., Ltd. ¥10 Figure 2 (3rd copy α) 3rd peak)

Claims (1)

【特許請求の範囲】[Claims] 絶縁材料から成る基板の表面に凹部を設ける工程と、前
記凹部上に半導体膜を成長させる工程と、アニールによ
って前記半導体物を溶融して前記四部に前記半導体膜の
一部を埋め込む工程と、前記埋め込−４、ｆｔた半導体
膜に薄膜トランジスタを形成する工程とからなる半導体
装置の製造方法。a step of providing a recess in the surface of a substrate made of an insulating material, a step of growing a semiconductor film on the recess, a step of melting the semiconductor material by annealing and embedding a part of the semiconductor film in the four parts; A method for manufacturing a semiconductor device comprising the step of forming a thin film transistor in a buried semiconductor film.
JP57234283A 1982-12-28 1982-12-28 Manufacture of semiconductor device Pending JPS59124123A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57234283A JPS59124123A (en) 1982-12-28 1982-12-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57234283A JPS59124123A (en) 1982-12-28 1982-12-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59124123A true JPS59124123A (en) 1984-07-18

Family

ID=16968546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57234283A Pending JPS59124123A (en) 1982-12-28 1982-12-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59124123A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01128420A (en) * 1987-11-13 1989-05-22 Agency Of Ind Science & Technol Glass substrate for semiconductor element and manufacture thereof
CN106653861A (en) * 2017-01-03 2017-05-10 京东方科技集团股份有限公司 Thin film transistor, fabrication method of thin film transistor, array substrate and fabrication method of array substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5658269A (en) * 1979-10-17 1981-05-21 Seiko Epson Corp Mos type semiconductor device
JPS5678495A (en) * 1979-11-29 1981-06-27 Toshiba Corp Preparation of base

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5658269A (en) * 1979-10-17 1981-05-21 Seiko Epson Corp Mos type semiconductor device
JPS5678495A (en) * 1979-11-29 1981-06-27 Toshiba Corp Preparation of base

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01128420A (en) * 1987-11-13 1989-05-22 Agency Of Ind Science & Technol Glass substrate for semiconductor element and manufacture thereof
CN106653861A (en) * 2017-01-03 2017-05-10 京东方科技集团股份有限公司 Thin film transistor, fabrication method of thin film transistor, array substrate and fabrication method of array substrate

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