JPS59124100A - Access time measuring device - Google Patents

Abstract

PURPOSE:To shorten a measurement time by measuring a maximum and a minimum access time by the 1st comparing means and the 2nd comparing means which has a delay circuit. CONSTITUTION:Expected value data sent out of a data generator 1b is supplied to a comparator 9 and to supply the delay circuit 9 to one input terminal of a comparator 10. The output of a measurement sample 4 is supplied to the other- side input terminals of the comparators 3 and 10 and timing pulses from a strobe timing generator 1c are further supplied to compare the measurement sample output data and expected value data at the same time. The delay circuit 9 is applied with the data preceded the expected value data from the generator 1b, and the data is delayed by one cycle and supplied to the comparator 10, so the maximum and minimum access times are obtained at outputs OUT1 and OUT2 at the same time on real-time basis.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an access time measuring device, and more particularly to an access time measuring device capable of simultaneously measuring maximum access time and minimum access time.

(2) Background of the technology In recent years, various measuring devices and test devices have been put into practical use for various checks and device inspections in semiconductor processes, and these measurements handle a large amount of data, making it difficult to produce test results in a short period of time. A measuring device is required.

In particular, the capacity of semiconductor devices such as memories continues to increase,
In measuring the access time of these memories, more time is required to measure the maximum access time and the minimum access time, and there has been a strong desire to shorten these measurement times.

(3) Problems with conventional technology Figure 1 is a system diagram of a conventional access time measurement device;
The figure is an explanatory diagram of the waveform of Figure 1.

In FIG. 1, 1 is a pattern generator, and the pattern generator 1 is composed of an address pattern generator 1a, a data generator 1b, and a strobe timing generator IC.
The address pattern generated by the address pattern generator 1a is applied to the data generator B1b, the strobe timing generator IC, and the driver circuit 2.

The data generator 1b generates comparison data (expected value) based on the address pattern generator 1a. The comparison data from the data generator 1b is applied to one input terminal of a comparator 3, for example, an exclusive-or gate circuit, and the output of the measurement sample 4 is generated based on the address pattern added from the driver circuit 2 to the memory of the measurement sample 4. The output obtained at the end is applied to the other input terminal of the comparator 3.

The timing pulse from the strobe timing generator 1c is applied to the comparator 3, and the output data of the measurement sample 4 is compared with the expected value generated by the data generator 1b, using the timing of the strobe timing generator 1c.

The operating waveforms of the above configuration will be explained with reference to FIGS. 2(a) to fdl. The output waveform of the address pattern generator 1a is the second
1H1VIL shown by solid and broken lines as shown in FIG. +a+, and the output of the data generator 1b is inverted from low level L to high level H as shown in FIG.

The output from the measurement sample 4 rises or falls as 5a, 5b, 5c, and 5d depending on the number of memory gates in the measurement sample 4, as shown by the solid line and broken line dl in FIG.

Furthermore, when the timing pulse from the strobe timing generator 1c is moved from the broken line position to the solid line position 6a, 6b, and 6c as shown in FIG. 2 (C1), the comparative output of the comparator 3 is as follows. .

That is, when the expected value is "H" and the measured sample output is "H", the output of the comparator 3 is "L", a path is judged, and the maximum access time 7 (see FIG. 2 (bl)) is measured. As shown in Figure 3 (see BL), the maximum access time can be found by finding the strobe timing that passes all address patterns for all address patterns. The expected value is the same as the maximum address time measurement method except that the expected value of the previous address delayed by l cycles is required.As mentioned above, conventional access time measurement devices There is only one comparator 3, and the expected value from the data generator can only be generated in either the current cycle or the previous cycle, so the maximum address time and minimum access time must be measured twice, which is a big problem. 40 to 5 Qse for 64-bit memory, etc.
This method had the disadvantage of requiring c.

(4) Object of the Invention In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide an access time measuring device that can simultaneously measure the maximum access time and the minimum access time to shorten the measurement time.

(5) Structure and purpose of the invention is to compare the expected value derived from the pattern data generation means and the output data of the measurement sample driven by the atres data derived from the pattern generation means. The maximum access time and the minimum access time are simultaneously measured by the first comparing means and the second comparing means which compares the delayed output derived from the expected value data through the delay means and the measured sample output data. This is achieved by providing an access time measuring device having the following characteristics.

(6) Examples of the invention An embodiment of the present invention will now be described in detail with reference to FIG.

FIG. 3 is a system diagram of the address time measuring device of the present invention, and the same parts as in FIG. 1 are given the same reference numerals and redundant explanation will be omitted. The expected value data taken out from the data generator 1b is applied to the first comparator 3 and the delay circuit 9, and the delayed output is applied to one input terminal of the second comparator 10. The second comparator 10, like the first comparator 3, can be constructed from an exclusive OR gate circuit.

The output from the measurement sample 4 is applied to the other input terminals of the first and second comparators 3.10, and the timing pulse from the strobe timing generator 1c is applied to the first and second comparators. The measurement sample output data and the expected value data are simultaneously compared by the first and second comparators.

By configuring as described above, the data one cycle before the expected value data from the data generator 1b is added to the delay circuit 9, and after being delayed by one cycle, it is applied to the exclusive OR gate circuit which is the second comparator. Maximum access time 7 at the current timing in order to
and a minimum access time of 8 can be obtained simultaneously at the first and second comparator outputs 0UTI and 0UT2.

(6) Effects of the Invention As explained in detail above, the access time measuring device of the present invention can simultaneously measure the maximum access time and the minimum access time, making it possible to measure access times of large-capacity memories, etc. It has a feature that can significantly reduce time.

[Brief explanation of the drawing]

Figure 1 is a system diagram of a conventional access time measurement device;
Figures +a) to Fdl are explanatory diagrams of waveforms in Figure 1, and Figure 3 is a system diagram of the access time measurement device of the present invention. In the figure 1... Pattern generator 1a... Address pattern generator 1b... Data generator
IC...Strobe timing generator 2...
・Driver circuit 3...First comparator 4...Measurement sample 9...Delay circuit 10...Second comparator 1st (¥) 2nd (2) 1. Display of incident 1988 Patent Application No. 233786 2, Name of the invention Access time measurement device 3, Relationship with the amended person case Patent applicant address 1015 Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture Name Fujitsu Ltd. 4, Agent Postal code 211 Address゛1015 Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture March 9, 1982 (shipment date March 29, 1981) 6
, Column 7 of "4. Brief explanation of drawings" of the specification subject to amendment, Line 9 of page 8 of the specification of contents of amendment... [Figures 2 (a) to (d)
) The text “〆” should be corrected to read “Figure 2.”

Claims (1)

[Claims] first comparing means for comparing expected value data derived from the pattern data generating means and output data of a measurement sample driven by the address data derived from the pattern generating means; An access time measuring device characterized in that the maximum access time and the minimum access time are simultaneously measured by a second comparing means that compares the derived delay output and the measured sample output data.