JPS59121880A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable to increase the density and integration of a nonvolatile memory cell by integrating memory transistor and a selective transistor, thereby performing the memory cell in a smaller element occupying area. CONSTITUTION:An element forming region and a field oxidized film region 30 are formed on a P type silicon substrate 21, and an oxidized film 23 is formed. Then, a selective gate 35 is, for example, formed by accumulating a polycrystalline silicon and then selectively removing it. Then, a hole is opened, an oxidized film is removed, and a tunnel oxidized film 27 is grown. A hole 32 is formed, and an N<+> type high density impurity region 223 is formed. Then, an oxidized film 24 is formed, and a floating gate 26 is provided. At this time, an N<+> type impurity region is formed even on the extension of the source 221. Subsequently, an oxidized film 28 is grown, and a control gate 29 is provided. Thereafter, source 221 and a drain 222 of N<+> type impurity region are formed, and a protective film 33 is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a nonvolatile semiconductor memory device having a floating gate and a gate gate, and particularly relates to an electrically rewritable memory device◇.

[Prior art and its problems]

For example, the one shown in Figure 1 is known as an electrically switchable nonvolatile memory having a floating gate.
FIG. 1(a) is a plan view, and FIG. 1(b) is a plan view.

(c) is a cut-away view of A-A', p, -B' of (a), respectively. 40° N+ layer 12 formed on P-type silicon substrate 11
1゜122, floating gates 15 stacked sequentially between these n+ layers 12, 1122 with insulating films 13゜14 interposed therebetween.
A memory transistor is constituted by the gate 16 and the gate 16.
Insulating film 17 between +-122 and 123
A selection transistor is constructed by the gate electrode 18 formed through the n+ layer 12. The floating gate 1 is connected to the floating gate 1 through a thin insulating film 19 on which a tunnel flow can flow.
5 and floating gate 15 and n"JWI 124
It is carried out by the exchange of electric charge between degrees. 20 is a field insulating film.

The selection transistor is provided for selectively writing or erasing when the memory elements are arranged in a matrix on the same substrate. Therefore, in this conventional structure, one memory element is constructed by arranging two transistors in a planar manner, which increases the area occupied by the memory element, which poses a major obstacle to further increasing the density.

[Purpose of the invention]

The present invention is a nonvolatile semiconductor memory device that improves the shortcomings of conventional devices, and realizes a nonvolatile memory element that has the same functions as the conventional device, but with a smaller device footprint, and enables high-density integration. The purpose is to provide the following.

[Summary of the invention]

The present invention uses a memory element structure in which a memory transistor and a selection transistor are integrated. That is, as shown in FIG. 2(a), two selection gates are provided between the source (221) and drain (222) of the memory transistor with an insulating film (c) interposed therebetween. A thin insulating film (2'0) through which current can flow is extended between the high concentration impurity region (228) provided under the source (221) and the source (221) via the insulating film C2 to function as a gate electrode. Furthermore, a floating gate I20 is installed on top of the insulating film Q4) and +27), and a control@1 gate (21) is installed through an insulating film 12. Part of b) is the source (221)
, the part that is not broken in the selection gate I25) of the channel part between the drain (222)? o< configured. Information in the memory element is rewritten by transferring charges between the high concentration impurity region (223) and the floating gate 6). Figure 2 (b) is the A-A' cross section, (c)
shows the B-B' cross section.

〔Effect of the invention〕

According to the present invention, a non-volatile semiconductor memory capable of selectively replacing electricity by about 1 can be realized with a device occupying area of 1 by a wide margin compared to the conventional one.
It can be realized as a jurisdiction.

[Embodiments of the invention]

The present invention will be explained in detail below. As shown in FIG. 3(a), an element formation region and a field oxide film region (to) are formed on a P-type silicon substrate (2I), and an oxide film is formed. Next, a selective layer (25) is formed by depositing, for example, polycrystalline silicon and then selectively removing it by a known method. Next, as shown in (b), an opening is provided to remove the oxide film in the tunnel oxide film region, and after removing the oxide film, the tunnel oxide film (
20 is grown to a thickness of, for example, 200A. A at this time
-A' cross section and B-B' cross section are shown in (f) and (g), respectively. Next, an opening (321) is provided for introducing impurities into the tunnel region, and an n+ high concentration impurity region (223) is formed.Next, as shown in (d), an oxide film (24) is formed. , a floating gate 126) is installed. The cross section is (
hHi). At this time, an n+ impurity region is also formed in the extended portion of the source (221). Next, as shown in (e), an oxide film α barrel is grown and a dll gate is installed. Then the source (221) is the impurity region.

0(J)(k) to form the drain (222) and install the protective film (33).

The equivalent circuit of this memory element can be expressed as shown in Figure 4. Writing to this memory element is performed using the source potential (Vs),
Tre (7 potential (Vo) M'4th place (GNDLK Ho')
) selection gate'-position (VG'2), control gate potential ('
This is done by keeping both voltages (a+) at a high level (~20V) and injecting the electron into the floating gate through the tunnel current. In unselected cells, charge injection does not occur because either the selection gate or the control gate is kept at a low level.

Next, when erasing this memory element, the selection gate potential (
VO2) is kept at a low potential (GND), and the source potential (Vs
) to a high level (~20V), and by keeping the selection gate potential (VGI) high only in the cells for which you wish to erase, the table is released in the tunnel region, and in the non-selected cells to be erased, the selection gate potential is kept high. When the potential (Vat) is at a low level (G
ND), so erasure does not occur.

Further, the drain level (VD) is kept open or kept at a potential such that no current flows between the drain and the source.

[Other examples of redundancy]

In the above embodiment V, a case has been described in which the tunnel region is connected to the source via the transistor of the selection gate, but the same effect can be obtained even if the tunnel region is connected to the drain. That is, as shown in FIG.
(35) is installed, and the tunnel region faces the n impurity region (828) and the floating gate through a thin oxide film CD of about 200A. The control gate (13!j) is installed through the control gate (13!j).
), the selection gate GJ5) and the iH control gate (iH control gate) are kept at a high potential (~20V), charge (magnetons) are injected in the tunnel region and the memory is rewritten. select gate 65) at a high potential (~20V)
.

By keeping the control gate (T) at a low potential (GND) and the drain (821) still at potential, charge is released in the tunnel region and memory is rewritten. .

[Brief explanation of drawings]

Figure 1 (,) is a plan view for explaining the conventional example, (b)
. (c) is a cross-sectional view showing the cross-sectional printing of A- and B-bi; FIG. 2 (,) is a plan view for explaining the present invention in detail; (b)
. (c) is a sectional view showing a cross section at A- and a cross section at B-B';
Figures (a) to (k) are diagrams for explaining one embodiment of the present invention, Figure 4 is a circuit diagram showing an equivalent circuit in one embodiment of the present invention, and Figure 85 (a) is a diagram for explaining an embodiment of the present invention. Plan views for explaining the embodiment, (b) and (C) are A-A? , BB' is a cross-sectional view. Agent: Patent attorney Noriyuki Chika (and 1 other person) Figure 1'/2''. Figure 2

Claims (1)

[Claims] In a memory device in which an electrically rewritable non-volatile memory element having a floating gate and a 711IJ control gate is integrated on a semiconductor substrate, the non-volatile memory element has a source and a drain formed apart from each other on the semiconductor substrate. and another high-concentration impurity region, a part of the channel region between the source and the drain, and a selection gate installed on the channel region between the other germ-concentration impurity region and the source or drain via an insulating film. At least a part of this selection gate is covered with an insulating film, and at least a part of the other high concentration impurity region of Mf is covered with an insulating film that is large enough to cause a tunnel effect, and the source , a floating gate layered so as to cover a part of the channel region between the drains with an insulating film interposed therebetween, and a control layer layered so as to cover at least a part of the floating gate with an insulating film interposed therebetween. Il
A nonvolatile semiconductor memory device characterized by being composed of l gates.