JPH0352231B2 - - Google Patents
Info
- Publication number
- JPH0352231B2 JPH0352231B2 JP57227430A JP22743082A JPH0352231B2 JP H0352231 B2 JPH0352231 B2 JP H0352231B2 JP 57227430 A JP57227430 A JP 57227430A JP 22743082 A JP22743082 A JP 22743082A JP H0352231 B2 JPH0352231 B2 JP H0352231B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate
- source
- drain
- floating gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000012535 impurity Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 230000000694 effects Effects 0.000 claims description 3
- 230000005641 tunneling Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Landscapes
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は浮遊ゲートと制御ゲートを有する不揮
発性半導体メモリ装置に係り、特に電気的に書き
換え可能なメモリ装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a nonvolatile semiconductor memory device having a floating gate and a control gate, and more particularly to an electrically rewritable memory device.
浮遊ゲートを有する電気的に書き換え可能な不
揮発性メモリとして、例えば第１図に示すものが
知られている。第１図のａは平面図であり、ｂ，
ｃはそれぞれａのＡ−A′，Ｂ−B′断面図である。
Ｐ型シリコン基板１１に形成されたn+層１２1，
１２2、これらのn+層１２1，１２2間に絶縁膜１
３，１４を介して順次積層された浮遊ゲート１５
および制御ゲート１６によりメモリトランジスタ
が構成されている。またn+層１２2，１２3とこれ
らのn+層１２2，１２3間に絶縁膜１７を介して形
成されたゲート電極１８により選択用トランジス
タが構成されている。記憶内容の書き換えはn+
層１２2と連続的に形成されたn+層１２4上にトン
ネル電流の流れうる薄い絶縁膜１９を介して浮遊
ゲート１５を延在させて、浮遊ゲート１５とn+
層１２4間の電荷の授受により行なわれる。２０
はフイールド絶縁膜である。
As an electrically rewritable nonvolatile memory having a floating gate, for example, the one shown in FIG. 1 is known. In FIG. 1, a is a plan view, b,
c is a cross-sectional view taken along line A-A' and line B-B' of a.
n + layer 12 1 formed on P-type silicon substrate 11,
12 2 , an insulating film 1 is placed between these n + layers 12 1 and 12 2
Floating gates 15 stacked sequentially through 3 and 14
and control gate 16 constitute a memory transistor. Further, a selection transistor is constituted by the n + layers 12 2 and 12 3 and a gate electrode 18 formed between the n + layers 12 2 and 12 3 with an insulating film 17 interposed therebetween. Rewriting memory contents is n +
The floating gate 15 is extended over the n + layer 12 4 formed continuously with the layer 12 2 through a thin insulating film 19 through which a tunnel current can flow, and the floating gate 15 and the n +
This is done by transferring charges between the layers 124 . 20
is the field insulating film.
選択用トランジスタはこのメモリ素子が同一基
板上にマトリツクス状に配置された時、選択的に
書き込みあるいは消去を行うために設けられてい
る。従つてこの従来構造は平面的に２つのトラン
ジスタを設置する事により、一つの記憶素子を構
成しており、記憶素子の占有面積が大きくなり高
密度化を計る上で大きな障害となつている。 The selection transistor is provided for selectively writing or erasing when the memory elements are arranged in a matrix on the same substrate. Therefore, in this conventional structure, one memory element is constructed by installing two transistors in a planar manner, which increases the area occupied by the memory element, which is a major obstacle in achieving higher density.
本発明は上述した従来装置の欠点を改良したも
ので、従来と同じ機能を有する不揮発性メモリ素
子を、より小さい素子占有面積で実現し、高密度
集積化を可能とした不揮発性半導体メモリ装置を
提供することを目的とする。
The present invention improves the above-mentioned drawbacks of the conventional device, and provides a nonvolatile semiconductor memory device that has the same functions as the conventional device, but with a smaller device footprint, and that enables high-density integration. The purpose is to provide.
本発明はメモリトランジスタと選択トランジス
タを一体化したメモリ素子構造を用いる。即ち、
第２図ａに示す如く、メモリトランジスタのソー
ス２２１、とドレイン２２２の間に絶縁膜２３を
介して選択ゲート２５が設けられる。この選択ゲ
ートは同時にトンネル電流の流れうる薄い絶縁膜
２７下に設けられた高濃度不純物領域２２３とソ
ース２２１との間で絶縁膜２３を介してゲート電
極として作用する如く延在されている。更に、そ
の上部に絶縁膜２４、及び２７を介して浮遊ゲー
ト２６が設置され更に、絶縁膜２８を介して制御
ゲート２９が設置されている。また、浮遊ゲート
２６の一部はソース２２１、ドレイン２２２の間
のチヤネル部分の選択ゲート２５で被れていない
部分を被う如く構成されている。本記憶素子の情
報の書き替えは高濃度不純物領域２２３と浮遊ゲ
ート２６の間での電荷の授受によつて行なわれ
る。第２図ｂはＡ−A′断面、ｃはＢ−B′断面を
示す。
The present invention uses a memory element structure in which a memory transistor and a selection transistor are integrated. That is,
As shown in FIG. 2a, a selection gate 25 is provided between the source 221 and drain 222 of the memory transistor with an insulating film 23 interposed therebetween. The selection gate is extended between the source 221 and a high concentration impurity region 223 provided under a thin insulating film 27 through which a tunnel current can flow, so as to act as a gate electrode via the insulating film 23. Further, a floating gate 26 is installed on top of the floating gate 26 with insulating films 24 and 27 interposed therebetween, and a control gate 29 is further installed with an insulating film 28 interposed therebetween. Further, a part of the floating gate 26 is configured to cover the channel portion between the source 221 and the drain 222 that is not covered by the selection gate 25. Information in the memory element is rewritten by transferring charges between the high concentration impurity region 223 and the floating gate 26. FIG. 2b shows the A-A' cross section, and FIG. 2C shows the B-B' cross section.
本発明によれば、選択的に電気的書き換え可能
な不揮発性半導体メモリを、従来に比べ素子占有
面積を大巾に低減して実現する事ができる。
According to the present invention, it is possible to realize a selectively electrically rewritable nonvolatile semiconductor memory with a significantly reduced element occupation area compared to the conventional memory.
以下、本発明の実施例を説明する。第３図ａに
示す様に、Ｐ型シリコン基板２１上に素子形成領
域とフイールド酸化膜領域３０を形成し、酸化膜
２３を形成する。次に、選択ゲート２５を例えば
多結晶ケイ素を堆積後、公知の方法により選択除
去して形成する。次にｂに示す様に、トンネル酸
化膜領域の酸化膜を除去する開口部を設け、酸化
膜を除去後、トンネル酸化膜２７を例えば200Å
の厚さに成長させる。この時のＡ−A′断面及び
Ｂ−B′断面を各々ｆ，ｇに示す。次に、トンネ
ル領域への不純物導入のための開口部３２を設
け、n+高濃度不純物領域２２３を形成する。次
に、ｄに示す如く、酸化膜２４を形成し、浮遊ゲ
ート２６を設置する。その断面をｈ，ｉに示す。
この時ソース２２１の延在部にもn+不純物領域
が形成されている。次に、ｅの様に酸化膜２８を
成長させ、制御ゲート２９を設置する。その後、
n+不純物領域であるソース２２１、ドレイン２
２２を形成し、保護膜３３を設置するｊ，ｋ。
Examples of the present invention will be described below. As shown in FIG. 3a, an element formation region and a field oxide film region 30 are formed on a P-type silicon substrate 21, and an oxide film 23 is formed. Next, the selection gate 25 is formed by, for example, depositing polycrystalline silicon and selectively removing it by a known method. Next, as shown in b, an opening is provided to remove the oxide film in the tunnel oxide film region, and after removing the oxide film, the tunnel oxide film 27 is formed to a thickness of, for example, 200 Å.
Grow to a thickness of . The A-A' and B-B' cross sections at this time are shown in f and g, respectively. Next, an opening 32 for introducing impurities into the tunnel region is provided, and an n + high concentration impurity region 223 is formed. Next, as shown in d, an oxide film 24 is formed and a floating gate 26 is installed. Its cross section is shown in h and i.
At this time, an n + impurity region is also formed in the extended portion of the source 221 . Next, as shown in e, an oxide film 28 is grown and a control gate 29 is installed. after that,
Source 221 and drain 2 which are n + impurity regions
22 and install a protective film 33 j, k.
本記憶素子の等価回路は第４図のように表す事
ができる。本記憶素子の書き込みはソース電位
VS、ドレイン電位VDを低電位（GND）に保ち、
選択ゲート電位VG2、制御ゲート電位VG1を共に
高電位（〜20V）に保つ事によりトンネル電流に
より浮遊ゲートへの電子が注入される事により行
なわれる。非選択のセルでは選択ゲートあるいは
制御ゲートのいずれか又は両方が低電位に保たれ
る事により、電荷の注入は起こらない。 The equivalent circuit of this memory element can be expressed as shown in FIG. Writing to this memory element is done at the source potential.
Keep V S and drain potential V D at low potential (GND),
This is done by keeping both the selection gate potential V G2 and the control gate potential V G1 at a high potential (~20V), so that electrons are injected into the floating gate by a tunnel current. In unselected cells, either or both of the selection gate and the control gate is kept at a low potential, so that charge injection does not occur.
次に、本記憶素子の消去を行う場合、選択ゲー
ト電位VG2を低電位（GND）に保ち、ソース電位
VSを高電位（〜20V）とし、消去を行いたいセル
のみ、選択ゲート電位VG1を高電位に保つ事によ
り、トンネル領域で電子が放出され、消去が行な
われる非選択セルでは選択ゲート電位VG1が低電
位（GND）に保たれるので消去は起こらない。
また、ドレイン電位VDは開放もしくはドレイン、
ソース間に電流の流れない程度の電位に保つてお
く。 Next, when erasing this memory element, the selection gate potential V G2 is kept at a low potential (GND) and the source potential
By setting V S to a high potential (~20V) and keeping the selection gate potential V G1 high only for the cells to be erased, electrons are emitted in the tunnel region, and for unselected cells to be erased, the selection gate potential Erasing does not occur because V G1 is kept at a low potential (GND).
In addition, the drain potential V D is open or drain
Keep the potential at a level that does not allow current to flow between the sources.
上記の実施例では、トンネル領域が選択ゲート
のトランジスタを介してソースに接続されている
場合について説明したが、ドレインに接続されて
いても同様の効果を得る事ができる。即ち、第５
図に示す如く、Ｐ型シリコン基板３１上に酸化膜
３３を介して制御ゲート３５が設置され、トンネ
ル領域は200Å程度の薄い酸化膜３７を介してn+
不純物領域３２３と浮遊ゲート３６が対向してい
る。浮遊ゲート３６上には、酸化膜３８を介して
制御ゲート３９が設置されている。本記憶素子の
書き込みを行うには、ドレイン３２１、及びソー
ス３２２を低電位（GND）に保ち、選択ゲート
３５、制御ゲート３９を高電位（〜20V）に保つ
事により、トンネル領域で電荷（電子）の注入が
おこり、記憶の書き換えが行なわれる。逆に選択
ゲート３５を高電位（〜20V）、制御ゲート３９
を低電位（GND）に保ち、ドレイン３２１を高
電位に保つ事により、トンネル領域で電荷の放出
が起こり、記憶の書き換えが行なわれる。
In the above embodiment, a case has been described in which the tunnel region is connected to the source via the selection gate transistor, but the same effect can be obtained even if the tunnel region is connected to the drain. That is, the fifth
As shown in the figure, a control gate 35 is installed on a P-type silicon substrate 31 through an oxide film 33, and a tunnel region is formed through an oxide film 37 with a thickness of about 200 Å .
Impurity region 323 and floating gate 36 face each other. A control gate 39 is provided on the floating gate 36 with an oxide film 38 interposed therebetween. To write to this memory element, the drain 321 and source 322 are kept at a low potential (GND), and the selection gate 35 and control gate 39 are kept at a high potential (~20V). ) occurs, and the memory is rewritten. Conversely, the selection gate 35 is set to a high potential (~20V), and the control gate 39 is set to a high potential (~20V).
By keeping the drain 321 at a low potential (GND) and the drain 321 at a high potential, charge is released in the tunnel region and memory is rewritten.
第１図ａは従来例を説明するための平面図、
ｂ，ｃはＡ−A′，Ｂ−B′の断面を示す断面図、
第２図ａは本発明の概要と説明するための平面
図、ｂ，ｃはＡ−A′断面、Ｂ−B′断面を示す断
面図、第３図ａ〜ｋは本発明の一実施例を説明す
るための図、第４図は本発明の一実施例における
等価回路を示す回路図、第５図ａは本発明の他の
実施例を説明するための平面図、ｂ，ｃはＡ−
A′，Ｂ−B′の断面図である。
FIG. 1a is a plan view for explaining a conventional example;
b, c are cross-sectional views showing the cross sections of A-A' and B-B',
Figure 2a is a plan view for explaining the outline of the present invention, b and c are cross-sectional views showing the A-A' cross section and the B-B' cross-section, and Figures 3 a to k are one embodiment of the present invention. 4 is a circuit diagram showing an equivalent circuit in one embodiment of the present invention, FIG. 5 a is a plan view for explaining another embodiment of the present invention, and b and c are A. −
It is a sectional view of A' and BB'.
Claims (1)
え可能な不揮発性メモリ素子を半導体基板上に集
積形成してなるメモリ装置において、不揮発性メ
モリ素子は半導体基板上に互いに離隔して形成さ
れたソース、ドレイン及び他の高濃度不純物領域
と、前記ソース、ドレイン間のチヤネル領域の一
部、及び前記他の高濃度不純物領域と前記ソース
又はドレイン間のチヤネル領域上に絶縁膜を介し
て設置された選択ゲートと、この選択ゲートの少
くとも一部を絶縁膜を介して被うと共に前記他の
高濃度不純物領域の少くとも一部をトンネル効果
が生じる程度の絶縁膜を介して被い、しかも前記
ソース、ドレイン間のチヤネル領域の一部を絶縁
膜を介して被う如く積層配設された浮遊ゲート
と、この浮遊ゲートの少くとも一部を絶縁膜を介
して被う如く積層配設された制御ゲートとから構
成した事を特徴とする不揮発性半導体記憶装置。1. In a memory device in which an electrically rewritable non-volatile memory element having a floating gate and a control gate is integrated on a semiconductor substrate, the non-volatile memory element has a source and a drain formed separately from each other on the semiconductor substrate. and another high concentration impurity region, a part of the channel region between the source and the drain, and a selection gate installed on the channel region between the other high concentration impurity region and the source or drain via an insulating film. and at least a part of the selection gate is covered with an insulating film, and at least a part of the other high concentration impurity region is covered with an insulating film to the extent that a tunneling effect occurs, and the source, A floating gate arranged in a stacked manner so as to cover a part of the channel region between the drains with an insulating film interposed therebetween, and a control gate arranged in a stacked manner so as to cover at least a part of the floating gate with an insulating film interposed therebetween. A nonvolatile semiconductor memory device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57227430A JPS59121880A (en) | 1982-12-28 | 1982-12-28 | Non-volatile semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57227430A JPS59121880A (en) | 1982-12-28 | 1982-12-28 | Non-volatile semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59121880A JPS59121880A (en) | 1984-07-14 |
| JPH0352231B2 true JPH0352231B2 (en) | 1991-08-09 |
Family
ID=16860725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57227430A Granted JPS59121880A (en) | 1982-12-28 | 1982-12-28 | Non-volatile semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59121880A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1198108B (en) * | 1986-11-18 | 1988-12-21 | Sgs Microelettronica Spa | A TWO-LEVEL AISPROM MEMORY CELL OF POLYSILICIO WITH TUNNEL OXYDE AREA |
| JP2830447B2 (en) * | 1990-10-15 | 1998-12-02 | 日本電気株式会社 | Semiconductor nonvolatile storage device |
-
1982
- 1982-12-28 JP JP57227430A patent/JPS59121880A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59121880A (en) | 1984-07-14 |
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