JPS59119830A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59119830A
JPS59119830A JP22839982A JP22839982A JPS59119830A JP S59119830 A JPS59119830 A JP S59119830A JP 22839982 A JP22839982 A JP 22839982A JP 22839982 A JP22839982 A JP 22839982A JP S59119830 A JPS59119830 A JP S59119830A
Authority
JP
Japan
Prior art keywords
photoresist
wafer
chamber
ion
ion implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22839982A
Other languages
Japanese (ja)
Inventor
Takashi Matsumoto
隆 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22839982A priority Critical patent/JPS59119830A/en
Publication of JPS59119830A publication Critical patent/JPS59119830A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation

Abstract

PURPOSE:To enable to reduce the process of IC manufacture by a method wherein ions are implanted in the wafer on which a photoresist pattern is formed, and then said photoresist is removed by performing a plasma ashing using excited oxygen. CONSTITUTION:An ion-implanting chamber 1 and a photoresist-removing chamber 2 are coupled through the intermediary of a gate valve 3. Said ion-implanting chamber 1 is maintained at 10<-6>Torr or thereabout by performing an evacuation from an exhaust tube 4 in the direction as shown by arrows in the diagram, and the photoresist-removing chamber 2 is maintained at 0.1Torr or thereabout by performing an evacuation from an exhaust tube 5 in the direction as shown by arrows in the diagram using a rotary pump. In the ion-implanting chamber 1, ion-implantation is performed on the wafer 6 whereon a desired a desired photoresist pattern was formed in the preceding process, and the control of the threshold voltage of the transistor region formed on the wafer can be accomplished. Then, the wafer 6 is moved to the photoresist removing chamber 2, and after the photoresist has been removed by supplying high frequency- excited oxygen and the like into the photoresist removing chamber 2, the wafer is picked out from the chamber for performance of the next process.

Description

【発明の詳細な説明】 (+、1発明の技術分野 本発明は半導体装置の製造方法、詳しくばウェハに対し
てなされるイオン注入工程において、イオン注入がなさ
れたウェハを搬出する予備排気室にホトレジスト除去装
置を設置してホトレジス1−を除去する方法に関する。
Detailed Description of the Invention (+, 1 Technical Field of the Invention) The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a preliminary evacuation chamber from which the ion-implanted wafer is taken out, in an ion implantation process performed on a wafer. This invention relates to a method for removing photoresist 1- by installing a photoresist removal device.

(2)技術の背景 築積回路(1に)1!造」二基においては、ウェハの露
光をなす光学装置、エツチング装置、イオン注入装置等
が別個に配設され、それぞれの装置において露光、エツ
チング、イオン注入等の工程か実施される。ウェハにI
Cを形成するに際しては、これらの装置の間でウェハを
搬送するごとが要求される。
(2) Technology background construction circuit (in 1) 1! In the two manufacturing units, an optical device for exposing the wafer, an etching device, an ion implantation device, etc. are installed separately, and processes such as exposure, etching, and ion implantation are performed in each device. I on the wafer
When forming C, it is necessary to transport the wafer between these devices every time.

IC製造工場が自動化されていない場合、上記したウェ
ハの搬送は人手によってなされたが、最近はIC製造工
場における自動化が促進され、ウェハの搬送のためには
搬送車、ベルトコンベヤ等が使用され、これらの1般送
装置は大型化される傾向にある。
If the IC manufacturing factory was not automated, the above-mentioned wafer transportation was done manually, but recently, automation in IC manufacturing factories has been promoted, and transport vehicles, belt conveyors, etc. are used to transport the wafer. These general feeding devices tend to be larger.

前記のウェハ搬送装置はその内部にウェハを収容してい
るため、ウェハに対する損傷を回避する目的で高速運転
することなく、はぼ人の歩く速度に等しい速度で移動す
る。
Since the wafer transport device contains the wafer therein, it moves at a speed equal to the walking speed of a human, without operating at high speed in order to avoid damage to the wafer.

かくして、TCi造工場における自1すJ化が進むにつ
れて、光学装置、エツチング装置ξ、イオンt′L−人
装置等の間のウェハの1殻送ば、大型化し、人の歩く速
度にほぼ等しい速度で運転される搬送装置によってなさ
れるi頃向にある。
Thus, as the TCi manufacturing plant becomes more compact, the amount of time it takes to send one wafer between the optical device, etching device ξ, ion t'L-human device, etc. increases, and the speed is almost equal to the walking speed of a person. i direction, which is done by a conveying device operated at speed.

(3)従来技術と問題点 IC製造」−場においては、上記した搬送装置が使用さ
れる一方で、製造時間(一般に手番と呼称される)の短
縮が要求される。すなわち、搬送装置は高速移動に不向
きであるにもかかわらず、IC製造の全」二枚に要する
時間(手番)の短縮は製造歩留りの向上の観点から強く
要求される。しかし、現在使用されている1般送装置は
j[G速運転に向かないごとか理由となり、Ic製造]
二二基おける自動化と丁番の短し11ば互いに相客れな
い関係にあり、これが現在のIC製造」二基における重
要な問題として歩留り向上の見地から検問されているも
のである。
(3) Prior Art and Problems While the above-mentioned transport device is used in the IC manufacturing field, there is a demand for shortening the manufacturing time (generally referred to as turn). In other words, although the conveyance device is not suitable for high-speed movement, there is a strong demand for shortening the time (hands) required to manufacture two ICs from the viewpoint of improving manufacturing yield. However, the 1st general feeder currently in use is not suitable for G-speed operation, and is manufactured by Ic.
Automation and short hinges are incompatible with each other, and this is an important issue in current IC manufacturing that is being examined from the standpoint of improving yield.

特にMO5型1cにおいて、エンハンスメント/ディプ
リーションモード(E/ D mode)の回路動作を
実現するために、イオン注入法によるしきい(ll’t
X′l圧の制御を行うことは一般に知られている。
In particular, in MO5 type 1c, in order to realize enhancement/depletion mode (E/D mode) circuit operation, threshold (ll't)
It is generally known to control the X'l pressure.

ずなわら、シリコンウェハー1−のしきい(ij:j電
圧制御をなそうとするトランジスタ領域を除いて、ウェ
ハをホ1−レノス1一般で覆い、次いでイオン注入を行
う。引続きポトレシス1−を除去した後に次工程へと進
む。
First, the wafer is covered with HO 1-RENOS 1 in general, except for the transistor region where threshold (ij:j voltage control is to be performed) of the silicon wafer 1-, and then ion implantation is performed. After removing it, proceed to the next step.

前記したボトレジスI・工程、イオン注入工程、ボトレ
ジス1−除去工程はそれぞれの装置を用いて独立に行わ
れる。かくして、ウェハの装置間移動に゛ついて前記し
た問題が発生ずることになる。
The bottom resist I step, the ion implantation step, and the bottom resist 1 removal step described above are performed independently using respective apparatuses. Thus, the problems described above regarding the movement of wafers from one device to another occur.

(4)発明の目的 本宛19農よ上記従来の問題点に鑑み、イオン注入装置
とホトレジスト除去装置との間のウェハ移動に要する時
間を有効利用し、ICII造の手番を短縮しうる半導体
装置の製造方法を提供することを目的とする。
(4) Purpose of the Invention In view of the above-mentioned conventional problems, a semiconductor device capable of shortening the steps in ICII manufacturing by effectively utilizing the time required for moving a wafer between an ion implantation device and a photoresist removal device. The purpose is to provide a method for manufacturing the device.

(5)発明の構成 そしてこの目的は、ホトレジストのパターンが形成され
たウェハに対しイオン注入室内でイオン注入をなし、次
いでイオン注入室に連結されたホトレジスト除去室にお
いて励起された酸素を用いるプラズマアッシングで前記
ホトレジストを1徐去することを特徴とする半導体装置
の製造方法を提供することによって達成される。
(5) Structure and purpose of the invention is to implant ions into a wafer on which a photoresist pattern has been formed in an ion implantation chamber, and then perform plasma ashing using excited oxygen in a photoresist removal chamber connected to the ion implantation chamber. This is achieved by providing a method for manufacturing a semiconductor device, characterized in that the photoresist is removed one step at a time.

(6)発明の実施例 以下本発明実施例を図面によって詳述する。(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

本発明方法の要旨は、前記した如くに、ホトレジスト工
程後に、イオン注入とホトレジス1−1除去とを一貫し
C行うにある。そのためには、添付し1面に1iji面
図で示す装置を用いる。同図を参照すると、■はイオン
注入室、2ばホトレジスト除去室を示し、これらの室は
ゲートバルブ3を介して連結されている。イオン注入室
1は例えばクライオポンプを用い”CJJI気管4から
矢印の示す方向に排気することにより10’−6Tor
r程度の圧力に保たれ、ホトレジスト処理室2はロータ
リポンプにより排気管5から矢印の方向に排気して0.
I Torr稈度の圧力に保つ。
The gist of the method of the present invention is that, as described above, after the photoresist process, ion implantation and removal of the photoresist 1-1 are performed consistently. For this purpose, a device is used which is attached and shown in the 1iji plane view on page 1. Referring to the figure, 2 indicates an ion implantation chamber, and 2 indicates a photoresist removal chamber, and these chambers are connected via a gate valve 3. The ion implantation chamber 1 is heated to 10'-6 Tor by evacuation from the CJJI trachea 4 in the direction indicated by the arrow using, for example, a cryopump.
The photoresist processing chamber 2 is evacuated from the exhaust pipe 5 in the direction of the arrow by a rotary pump to a pressure of about 0.
Maintain pressure at I Torr culm.

10−6Torr程度の圧力に保たれたイオン処理室1
において、前の工程で所望のホトレジストパターンが形
成されたウェハ6には所望のイオン注入がなされ、ウェ
ハに形成されたトランジスタ領域のしきい値電圧制御が
実現される。上記イオン注入の間ゲートバルブ3は閉じ
ておく。
Ion treatment chamber 1 maintained at a pressure of about 10-6 Torr
In this step, desired ions are implanted into the wafer 6 on which a desired photoresist pattern has been formed in the previous step, and threshold voltage control of the transistor region formed on the wafer is realized. The gate valve 3 is kept closed during the above ion implantation.

次に、ゲートバルブ3を開き、図示しないアームを用い
てウェハ6をホトレジスト除去室2に移動し、ゲートバ
ルブ3を閉じる。
Next, the gate valve 3 is opened, the wafer 6 is moved to the photoresist removal chamber 2 using an arm (not shown), and the gate valve 3 is closed.

次いで、高周波励起した酸素(02)をホトレジスト工
程後2に供給する。そのためには、図示しないソース例
えば酸素ホンへから酸素を矢印の方向に供給管7を通し
て供給し、供給管7ば高周波発生コイル8と組み合せた
配置により、■11周波励起された酸素がホトレジスト
処理室2に矢印の方向に送られる。なお、ホトレジスト
除去室2の真空度はイオン注入室1の真空度より低いか
ら、ホトレジスト除去室のQ、l Torr程度の圧力
維持は容易であり、ロータリポンプで足りる。また、酸
素の励起のためには、前記した高周波の他に一ンイクロ
波を用いてもよい。
Next, high-frequency excited oxygen (02) is supplied to the post-photoresist process 2. To do this, oxygen is supplied from a source (not shown), such as an oxygen horn, through the supply pipe 7 in the direction of the arrow, and the supply pipe 7 is arranged in combination with a high frequency generating coil 8. 2 is sent in the direction of the arrow. Incidentally, since the degree of vacuum in the photoresist removal chamber 2 is lower than the degree of vacuum in the ion implantation chamber 1, it is easy to maintain the pressure in the photoresist removal chamber at about Q,1 Torr, and a rotary pump is sufficient. Furthermore, in order to excite oxygen, one microwave may be used in addition to the above-mentioned high frequency.

ホトレジスト除去室2内で、前記した高周波励起酸素を
用いホトレジストをプラズマア・ノシングにより除去し
、しかる後は、図示しないアームを用いてウェハ6を室
外に出し次の工程に移す。
Inside the photoresist removal chamber 2, the photoresist is removed by plasma anothing using the above-mentioned high-frequency excited oxygen, and then the wafer 6 is taken out of the room using an arm (not shown) and transferred to the next step.

以上の説明から理解されうる如(、被処理ウェハ6がイ
オン注入室1からホトレジスト除去糸2に移1リノに要
する時間は、ケートバルブ3を開い−(rからアームで
ウェハ6をポトレシスl−除去室2に移すまでに消7y
される時間であるから、従来のイオン注入袋)?yから
別の場所に位置するホトレジスト除去装置に前記した搬
送装置を用いて移動するに要する時間に比べて大幅に短
縮される。
As can be understood from the above explanation, the time required for transferring the wafer 6 to be processed from the ion implantation chamber 1 to the photoresist removal line 2 is as follows. Disappeared 7y before moving to removal chamber 2.
Is it time for a conventional ion implantation bag)? The time required to move from Y to the photoresist removal equipment located at another location using the above-mentioned transport device is significantly reduced.

(7)発明の効果 以」二詳細に説明したように、本発明の方法によると、
ト10S型ICにおけるE/Dモートの回路動作を実現
するだめのイオン注入とポI・レジスト除去に要する時
間が大幅に低減され、それに応じてIC製造時間が短縮
されるので、製造歩留りの向上に効果大である。
(7) Effects of the Invention As explained in detail in 2, according to the method of the present invention,
The time required for ion implantation and POI/resist removal to realize the circuit operation of the E/D mode in the 10S type IC is significantly reduced, and the IC manufacturing time is shortened accordingly, improving the manufacturing yield. It is highly effective.

【図面の簡単な説明】[Brief explanation of the drawing]

添fd図面は本発明の方法を実施するために使用する装
置の概略断面図である。 1−イオン注入室、2−ボトレシスト 除去室、3−ゲートバルブ、4..5−排気管、6−ウ
ェハ、7−酸素供給管、8−間周波発生コイル
The accompanying drawings are schematic cross-sectional views of the apparatus used to carry out the method of the invention. 1-Ion implantation chamber, 2-Botrecyst removal chamber, 3-Gate valve, 4. .. 5-exhaust pipe, 6-wafer, 7-oxygen supply pipe, 8-interval frequency generation coil

Claims (1)

【特許請求の範囲】[Claims] ボトレシスI・のパターンが形成されたウェハに対しイ
オン注入室内でイオン注入をなし、次いでイオン注入室
に連結されたホトレジスト除去室において励起された酸
素を用いるプラスマアッシングで前記ポトレシストを除
去することを稍徴とずろ半導体装置の製造方法。
The wafer on which the Botresis I pattern is formed is subjected to ion implantation in an ion implantation chamber, and then the potresist is removed by plasma ashing using excited oxygen in a photoresist removal chamber connected to the ion implantation chamber. A method for manufacturing a semiconductor device.
JP22839982A 1982-12-27 1982-12-27 Manufacture of semiconductor device Pending JPS59119830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22839982A JPS59119830A (en) 1982-12-27 1982-12-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22839982A JPS59119830A (en) 1982-12-27 1982-12-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59119830A true JPS59119830A (en) 1984-07-11

Family

ID=16875853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22839982A Pending JPS59119830A (en) 1982-12-27 1982-12-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59119830A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53130975A (en) * 1977-03-18 1978-11-15 Anvar Method of and device for doping semiconductor substrate
JPS5587435A (en) * 1978-12-25 1980-07-02 Fujitsu Ltd Method of producing semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53130975A (en) * 1977-03-18 1978-11-15 Anvar Method of and device for doping semiconductor substrate
JPS5587435A (en) * 1978-12-25 1980-07-02 Fujitsu Ltd Method of producing semiconductor device

Similar Documents

Publication Publication Date Title
US7544959B2 (en) In situ surface contamination removal for ion implanting
US8257501B2 (en) Plasma doping device with gate shutter
TW201028804A (en) Substrate processing method
JPH10125762A (en) Apparatus and method for treating substrate
US20020197870A1 (en) High speed stripping for damaged photoresist
JP3160263B2 (en) Plasma doping apparatus and plasma doping method
JP2001148378A (en) Plasma processing apparatus, cluster tool and plasma control method
JPH07335711A (en) Reduced pressure/normal pressure treating device
KR20010043249A (en) Method of ion implantation
JPS59119830A (en) Manufacture of semiconductor device
JP2001118904A (en) Wafer treatment equipment having load lock chambers and carrying method of wafer to be treated
CN116564885A (en) Method for improving electric leakage of MOS tube caused by electric charge
JPH01161835A (en) Plasma treatment and device therefor
JPH01135015A (en) Semiconductor wafer treating device
JPS5858726A (en) Semiconductor processing device
US9373516B2 (en) Method and apparatus for forming gate stack on Si, SiGe or Ge channels
WO2001070517A1 (en) High speed stripping for damaged photoresist
JP5727853B2 (en) Plasma generation method
JPH01120811A (en) Semiconductor wafer treatment equipment
CN111564404B (en) Wafer desorption method and device
JP2887079B2 (en) Ashing equipment
JP3211535B2 (en) Manufacturing method of thin film element
JPH09115852A (en) Device and method for introducing impurity
JPH04277620A (en) Manufacture of semiconductor integrated circuit device
JPH09162173A (en) Method and system for ashing