CN111564404B - Wafer desorption method and device - Google Patents

Wafer desorption method and device Download PDF

Info

Publication number
CN111564404B
CN111564404B CN202010440572.7A CN202010440572A CN111564404B CN 111564404 B CN111564404 B CN 111564404B CN 202010440572 A CN202010440572 A CN 202010440572A CN 111564404 B CN111564404 B CN 111564404B
Authority
CN
China
Prior art keywords
wafer
electrostatic
reaction chamber
reverse voltage
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010440572.7A
Other languages
Chinese (zh)
Other versions
CN111564404A (en
Inventor
陈国动
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Naura Microelectronics Equipment Co Ltd
Original Assignee
Beijing Naura Microelectronics Equipment Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Naura Microelectronics Equipment Co Ltd filed Critical Beijing Naura Microelectronics Equipment Co Ltd
Priority to CN202010440572.7A priority Critical patent/CN111564404B/en
Publication of CN111564404A publication Critical patent/CN111564404A/en
Application granted granted Critical
Publication of CN111564404B publication Critical patent/CN111564404B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H01L21/6833Details of electrostatic chucks
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

The invention provides a wafer desorption method, which is used in semiconductor equipment, the semiconductor equipment comprises a reaction chamber and an electrostatic chuck arranged in the reaction chamber, the electrostatic chuck comprises a substrate and an electrostatic electrode, the substrate is used for bearing a wafer, the electrostatic electrode is arranged in the substrate, and the wafer desorption method comprises the following steps: introducing auxiliary gas into the reaction chamber until the auxiliary gas in the reaction chamber reaches a preset pressure; removing the electrostatic voltage absorbed by the wafer to zero; providing a reverse voltage to the electrostatic electrode, wherein the reverse voltage has a polarity opposite to that of the electrostatic voltage so as to ionize the auxiliary gas; and stopping providing the reverse voltage to the electrostatic electrode after the duration of providing the reverse voltage to the electrostatic electrode reaches the preset duration, and discharging the auxiliary gas out of the reaction chamber to finish desorption of the electrostatic chuck and the wafer. The invention also provides a wafer desorption device. The invention shortens the time required by wafer desorption and improves the production efficiency of the wafer.

Description

Wafer desorption method and device
Technical Field
The invention relates to the technical field of semiconductor processing, in particular to a wafer desorption method and device.
Background
In the integrated circuit chip manufacturing industry, wafers are typically placed on an electrostatic chuck in a reaction chamber for processing, which performs the functions of supporting, fixing, and controlling the temperature of the wafers. The electrostatic chuck is externally connected with a power supply, and before the main process is started, electrostatic voltage is provided for an electrostatic electrode of the electrostatic chuck so as to form an electrostatic field on the electrostatic chuck, and therefore a wafer is adsorbed on the electrostatic chuck; after the main process is finished, the electrostatic voltage is stopped from being supplied to the electrostatic chuck to remove the electrostatic field on the electrostatic chuck, so that the wafer and the electrostatic chuck are desorbed.
However, after the electrostatic voltage is stopped, electrostatic charges may exist on both the wafer and the electrostatic chuck, so that the wafer and the electrostatic chuck still attract each other, and a sticking phenomenon occurs.
In order to solve the above problems, a conventional wafer desorption method is as follows: after the main process is finished, a reverse voltage with the polarity opposite to that of the electrostatic voltage is provided to the electrostatic electrode in the electrostatic chuck to remove the electrostatic charge on the electrostatic chuck, however, since the above steps are performed in a vacuum environment, the reverse voltage cannot remove the electrostatic charge on the wafer, and therefore, plasma is also required to be introduced to remove the electrostatic charge on the wafer. Specifically, fig. 1 is a timing diagram of a conventional wafer desorption method, which includes a reverse voltage charge removal stage T1 and a plasma charge removal stage T2, as shown in fig. 1. In the reverse voltage de-electrification stage T1, all the gas in the reaction chamber is exhausted so as to make the reaction chamber in a vacuum state; at this time, the electrostatic voltage for adsorbing the wafer is stopped to the electrostatic electrode in the electrostatic chuck, and the reverse voltage having the polarity opposite to that of the electrostatic voltage is supplied to the electrostatic electrode for a certain period of time to remove the electrostatic charge on the electrostatic chuck. In the plasma de-electrifying stage T2, the supply of reverse voltage to the electrostatic electrode in the electrostatic chuck is stopped, the gas to be excited is introduced into the reaction chamber through the gas inlet mechanism, meanwhile, a driving signal is supplied to the radio frequency mechanism in the reaction chamber, and at the moment, the radio frequency mechanism excites the gas to be excited in the reaction chamber into plasma, so that electrostatic charges on the wafer and residual electrostatic charges on the electrostatic chuck are removed. However, increasing the plasma neutralization stage T2 after the reverse voltage neutralization stage T1 may result in the time required for desorption of the wafer and the electrostatic chuck being prolonged, which affects the production efficiency of the wafer, and the introduced plasma may cause plasma induced damage (Plasma induced damage, PID) to the wafer, thereby affecting the product yield of the wafer.
Disclosure of Invention
The invention aims at solving at least one of the technical problems existing in the prior art and provides a wafer desorption method and device.
In order to achieve the above object, the present invention provides a wafer desorption method for use in a semiconductor apparatus including a reaction chamber and an electrostatic chuck disposed in the reaction chamber, the electrostatic chuck including a substrate for carrying a wafer and an electrostatic electrode disposed in the substrate, wherein the wafer desorption method comprises:
introducing auxiliary gas into the reaction chamber until the auxiliary gas in the reaction chamber reaches a preset pressure;
evacuating the electrostatic voltage absorbed by the wafer to zero;
providing a reverse voltage to the electrostatic electrode, the reverse voltage having a polarity opposite to the electrostatic voltage to ionize the assist gas;
and stopping providing the reverse voltage to the electrostatic electrode after the duration of providing the reverse voltage to the electrostatic electrode reaches a preset duration, and discharging the auxiliary gas out of the reaction chamber to complete desorption of the electrostatic chuck and the wafer.
Optionally, before the step of introducing an assist gas into the reaction chamber, the wafer desorption method further includes:
and evacuating the refrigerant gas in the refrigerant gas pipeline in the semiconductor equipment.
Optionally, after the stopping the supplying of the reverse voltage to the electrostatic electrode, the method further comprises:
and evacuating the reverse voltage.
Optionally, the preset time period is 0.5s to 10s.
Optionally, the preset time period is 0.5s to 3s.
Optionally, the auxiliary gas includes: argon, oxygen, nitrogen or helium.
Optionally, the flow rate of the auxiliary gas is 100sccm to 2000sccm.
Optionally, the preset pressure is 50mT to 500mT.
Alternatively, the reverse voltage has an absolute value of 1.8KV to 4.5KV
The invention also provides a wafer desorption device which is used in semiconductor equipment, wherein the semiconductor equipment comprises a reaction chamber and an electrostatic chuck arranged in the reaction chamber, the electrostatic chuck comprises a matrix and an electrostatic electrode, the matrix is used for bearing a wafer, and the electrostatic electrode is arranged in the matrix; wherein, the wafer desorption device includes:
the gas transmission module is used for introducing auxiliary gas into the reaction chamber until the auxiliary gas in the reaction chamber reaches a preset pressure;
the power-off module is used for removing the electrostatic voltage absorbed on the wafer to zero;
a power supply module for providing a reverse voltage to the electrostatic electrode, the reverse voltage having a polarity opposite to the electrostatic voltage so as to ionize the auxiliary gas;
and the first exhaust module is used for exhausting the auxiliary gas out of the reaction chamber after the duration of supplying the reverse voltage to the electrostatic electrode by the power supply module reaches a preset duration.
The beneficial effects are that:
compared with the scheme of removing static charges on the static chuck through reverse voltage in the traditional wafer desorption method under vacuum environment, the method introduces auxiliary gas when the static charges are removed on the static chuck through the reverse voltage, and the auxiliary gas can effectively help to remove the static charges on the wafer after ionization in an electric field formed by the reverse voltage, so that plasma is not required to be introduced after the reverse voltage is provided to remove the static charges on the wafer, thereby shortening the time required by wafer desorption and improving the production efficiency. Meanwhile, as no plasma is introduced, the problem that the plasma causes induced damage (Plasma induced damage, PID) to the wafer can be prevented, and the product yield of the wafer is improved.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the description serve to explain, without limitation, the invention. In the drawings:
FIG. 1 is a timing diagram of a conventional wafer desorption method;
fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a flow chart of a wafer desorption method according to an embodiment of the present invention;
FIG. 4 is a timing diagram of a wafer desorption method according to an embodiment of the present invention;
FIG. 5a is a schematic diagram illustrating a wafer desorption process according to an embodiment of the present invention;
FIG. 5b is a schematic diagram of a wafer desorption process according to an embodiment of the present invention;
FIG. 6 is a second schematic diagram of a semiconductor device according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a wafer desorbing apparatus according to an embodiment of the present invention;
FIG. 8 is a third schematic diagram of a semiconductor device according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a semiconductor device according to an embodiment of the present invention.
Detailed Description
The following describes specific embodiments of the present invention in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
Unless defined otherwise, technical or scientific terms used in the embodiments of the present invention should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present invention belongs. The terms "first," "second," and the like, as used herein, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
An embodiment of the present invention provides a wafer desorption method, which is used in a semiconductor device, and fig. 2 is a schematic structural diagram of the semiconductor device provided in the embodiment of the present invention, as shown in fig. 2, where the semiconductor device includes: the wafer desorption method according to the embodiment of the present invention includes the steps of:
s1, introducing auxiliary gas into the reaction chamber until the auxiliary gas in the reaction chamber reaches a preset pressure.
S2, the electrostatic voltage absorbed by the wafer is removed to zero.
And S3, providing a reverse voltage to the electrostatic electrode, wherein the reverse voltage has the polarity opposite to that of the electrostatic voltage so as to ionize the auxiliary gas.
In the embodiment of the present invention, the electrostatic electrode 22 in the electrostatic chuck 2 may be a single electrostatic electrode or a double electrostatic electrode, and when the electrostatic electrode 22 in the electrostatic chuck 2 is a single electrostatic electrode, the electrostatic voltage provided to the electrostatic electrode 22 for adsorbing the wafer 3 may be a positive voltage, for example, 2.4KV, and the reverse voltage provided to the electrostatic electrode 22 may be a negative voltage, for example, -3.0KV.
And S4, stopping providing the reverse voltage to the electrostatic electrode after the duration of providing the reverse voltage to the electrostatic electrode reaches the preset duration, and discharging the auxiliary gas out of the reaction chamber to finish desorption of the electrostatic chuck and the wafer.
Fig. 4 is a timing chart of a wafer desorption method according to an embodiment of the present invention, as shown in fig. 4, in a reverse voltage de-charging stage T1, an auxiliary gas is introduced into the reaction chamber 1 until the auxiliary gas in the reaction chamber 1 reaches a preset pressure. Thereafter, the electrostatic voltage is evacuated to zero and a reverse voltage is supplied to the electrostatic electrode 22 to ionize the assist gas.
Compared with the scheme of removing electrostatic charges from an electrostatic chuck by reverse voltage in a vacuum environment in the traditional wafer desorption method, in the embodiment of the invention, auxiliary gas is introduced when the electrostatic charges are removed from the electrostatic chuck 2 by reverse voltage, the pressure of the auxiliary gas reaches the preset pressure, the ionization degree of the auxiliary gas with the preset pressure in an electric field formed by the reverse voltage is increased, so that free electrons near the wafer 3 are increased, and the increased free electrons are transferred to the wafer 3, and then the electrostatic charges on the wafer 3 can be effectively removed. Meanwhile, since no plasma is introduced, plasma induced damage (Plasma induced damage, PID) on the wafer 3 can be avoided, thereby improving the yield of the wafer 3.
In some embodiments, the assist gas may include, but is not limited to: argon, oxygen, nitrogen or helium are used as auxiliary gases for convenience of description, and the following description of the embodiments of the present invention will be given by taking argon as an auxiliary gas. In the embodiment of the present invention, the preset time period may be determined according to actual needs, specifically, the preset time period may be set to 0.5s to 10s, and in the embodiment of the present invention, the preset time period is preferably set to 0.5s to 3s. The flow rate of the assist gas may be 100sccm to 2000sccm. The preset pressure of the auxiliary gas may be 50mT to 500mT. The absolute value of the reverse voltage may be 1.8KV to 4.5KV.
Fig. 5a and 5b are schematic diagrams illustrating a wafer desorption process according to an embodiment of the present invention, and the wafer and electrostatic chuck desorption process according to an embodiment of the present invention is described below with reference to fig. 5a and 5 b. Specifically, as shown in fig. 5a, after the electrostatic voltage is stopped, electrostatic charges remain on both the wafer 3 and the electrostatic chuck 2, wherein the electrostatic charges on the electrostatic chuck 2 are generally negative charges, so that the electrostatic charges on the wafer 3 are induced positive charges. As shown in fig. 5b, when a reverse voltage is applied to the electrostatic electrode, the reverse voltage causes positive charges to accumulate on the electrostatic chuck 2, thereby neutralizing negative charges on the electrostatic chuck to effect removal of the electrostatic charges on the electrostatic chuck 2. The auxiliary gas is ionized in the electric field, the density of free electrons near the wafer 3 is increased, the increased free electrons are transferred to the wafer 3, and positive charges on the wafer 3 can be neutralized, so that electrostatic charges on the wafer 3 are removed. At the same time, the ions ionized from the auxiliary gas can also help to remove negative charges on the electrostatic chuck 2, thereby enhancing the removal effect of the reverse voltage on the electrostatic charges on the electrostatic chuck 2.
Fig. 6 is a second schematic structural diagram of a semiconductor device according to an embodiment of the present invention, as shown in fig. 6, in some embodiments, the electrostatic electrode 22 in the electrostatic chuck 2 may further be a double electrostatic electrode, specifically, the electrostatic electrode 22 includes a first sub-electrode 22a and a second sub-electrode 22b, and the electrostatic voltage for adsorbing the wafer 3 includes: a first electrostatic voltage applied to the first sub-electrode 22a and a second electrostatic voltage applied to the second sub-electrode 22b, the polarity of the first electrostatic voltage and the polarity of the second electrostatic voltage being opposite. In an embodiment of the present invention, the step of providing the reverse voltage to the electrostatic electrode 22 includes:
the first counter voltage is supplied to the first sub-electrode 22a, and the second counter voltage is supplied to the second sub-electrode 22 b. The polarity of the first reverse voltage is opposite to that of the first electrostatic voltage, and the polarity of the second reverse voltage is opposite to that of the second electrostatic voltage.
In the embodiment of the present invention, the first sub-electrode 22a may be a positive electrode and the second sub-electrode 22b may be a negative electrode. At this time, during the main process, the electrostatic voltage supplied to the first sub-electrode 22a is a positive voltage, for example, 1.2KV; the electrostatic voltage supplied to the second sub-electrode 22b is a negative voltage, for example, -1.2KV. In the reverse voltage neutralization stage T1, the first reverse voltage supplied to the first sub-electrode 22a is a negative voltage, for example, -1.5KV, and the second reverse voltage supplied to the second sub-electrode 22b is a positive voltage, for example, 1.5KV.
It should be noted that, in the above embodiment, when the electrostatic electrode 22 is a single electrostatic electrode, the absolute value of the reverse voltage refers to the absolute value of the voltage difference between the voltage applied to the electrostatic electrode 22 and the zero potential; when the electrostatic electrode 22 employs a double electrostatic electrode, the absolute value of the reverse voltage refers to the absolute value of the voltage difference between the voltage applied by the first sub-electrode 22a and the voltage applied by the second sub-electrode 22 b.
Referring to fig. 4 and fig. 6, in some embodiments, a coolant gas pipe 4 is further disposed on the substrate 21, the coolant gas pipe 4 penetrates through the substrate 21, and one end of the coolant gas pipe 4 is disposed towards the wafer 3, and the coolant gas pipe 4 is used for blowing coolant gas to the wafer 3 during the main process, so as to control the temperature of the wafer 3. In an embodiment of the present invention, before the step of introducing the assist gas into the reaction chamber 1, the wafer desorption method may further include: the refrigerant gas in the refrigerant gas pipeline 4 in the semiconductor equipment is exhausted.
In the embodiment of the invention, by exhausting the refrigerant gas in the refrigerant gas pipeline 4, the problem that the position of the wafer 3 is deviated due to the fact that the wafer 3 is jacked up by the refrigerant gas in the refrigerant gas pipeline 4 after the wafer 3 is desorbed with the electrostatic chuck 2 can be avoided.
In some embodiments, after stopping the supply of the reverse voltage to the electrostatic electrode 22, the desorption method further comprises: the reverse voltage is evacuated.
The embodiment of the invention further provides a wafer desorbing device, which is used in a semiconductor device, fig. 7 is a schematic structural diagram of the wafer desorbing device provided in the embodiment of the invention, fig. 8 is a schematic structural diagram of a third semiconductor device provided in the embodiment of the invention, and referring to fig. 7 and 8, the semiconductor device includes a reaction chamber 1 and an electrostatic chuck 2 disposed in the reaction chamber 1, the electrostatic chuck 2 includes a substrate 21 and an electrostatic electrode 22, the substrate 21 is used for carrying a wafer 3, and the electrostatic electrode 22 is disposed in the substrate 21 and is insulated from the substrate 21. The wafer desorbing apparatus 5 includes: the device comprises a gas transmission module 51, a power removal module 52, a power supply module 53 and a first exhaust module 54. The gas delivery module 51 is used for introducing auxiliary gas into the reaction chamber 1 until the auxiliary gas in the reaction chamber 1 reaches a preset pressure. The power-off module 52 is used for removing the electrostatic voltage absorbed on the wafer 3 to zero. The power supply module 53 is configured to provide a reverse voltage to the electrostatic electrode 22, the reverse voltage having a polarity opposite to that of the electrostatic voltage, so as to ionize the auxiliary gas. The first exhaust module 54 is configured to exhaust the auxiliary gas from the reaction chamber 1 after a period of time during which the power supply module 53 supplies the reverse voltage to the electrostatic electrode 22 reaches a preset period of time.
Specifically, the gas delivery module 51 in the wafer desorber 5 may be connected to the top of the reaction chamber 1 so that the assist gas may enter the reaction chamber 1 from the top of the reaction chamber 1, and the gas exhaust module 54 in the wafer desorber 5 may be connected to the bottom of the sidewall of the reaction chamber 1 so that the assist gas may exit the reaction chamber 1 from the bottom of the reaction chamber 1. As shown in fig. 4, in the reverse voltage charge removal stage T1, the auxiliary gas is introduced into the reaction chamber 1 through the gas delivery module 51 until the auxiliary gas in the reaction chamber 1 reaches a preset pressure. The electrostatic voltage on the wafer 3 is evacuated to zero by the evacuation module 52. A reverse voltage is provided to the electrostatic electrode 22 by the power supply module 52 to ionize the assist gas. Since the auxiliary gas is ionized in the electric field, the density of free electrons near the wafer 3 and the electrostatic chuck 2 increases, and the increased free electrons are transferred to the wafer 3, electrostatic charges on the wafer 3 can be effectively removed. After that, the power supply module 52 stops supplying the reverse voltage to the electrostatic electrode 22 and discharges the assist gas into the reaction chamber 1 through the first exhaust module 54, thereby completing desorption of the wafer 3.
By adopting the wafer desorption device 5 provided by the embodiment of the invention, the time required for desorption of the wafer 3 can be shortened, the production efficiency of the wafer 3 is improved, and meanwhile, as no plasma is introduced, the occurrence of plasma induced damage (Plasma induced damage, PID) on the wafer 3 can be avoided, and the product yield of the wafer is improved.
Fig. 9 is a schematic diagram of a semiconductor device according to an embodiment of the present invention, as shown in fig. 9, in some embodiments, the electrostatic electrode 22 includes a first sub-electrode 22a and a second sub-electrode 22b, and the electrostatic voltage for adsorbing the wafer 3 includes: a first electrostatic voltage applied to the first sub-electrode 22a and a second electrostatic voltage applied to the second sub-electrode 22b, the polarity of the first electrostatic voltage and the polarity of the second electrostatic voltage being opposite. The power supply module 53 includes: a first power sub-module 53a and a second power sub-module 53b. The first power sub-module 53a is electrically connected to the first sub-electrode 22a, and the first power sub-module 53a is configured to provide a first reverse voltage to the first sub-electrode 22 a. The second power supply sub-module 53b is electrically connected to the second sub-electrode 22b, and the second power supply sub-module 53b is configured to provide a second reverse voltage to the second sub-electrode 22 b. The polarity of the first reverse voltage is opposite to that of the first electrostatic voltage, and the polarity of the second reverse voltage is opposite to that of the second electrostatic voltage.
In an embodiment of the present invention, the power supply module 53 may provide a dc power supply. The first sub-electrode 22a may be a positive electrode and the second sub-electrode 22b may be a negative electrode. At this time, during the main process, the electrostatic voltage provided by the first power sub-module 53a to the first sub-electrode 22a is a positive voltage, for example, 1.2KV, and the electrostatic voltage provided by the second power sub-module 53b to the second sub-electrode 22b is a negative voltage, for example, -1.2KV. In the reverse voltage neutralization stage T1, the first power supply sub-module 53a and the second power supply sub-module 53b both change the polarity of the output voltage, the first reverse voltage supplied from the first power supply sub-module 53a to the first sub-electrode 22a is a negative voltage, for example, -1.5KV, and the second reverse voltage supplied from the second power supply sub-module 53b to the second sub-electrode 22b is a positive voltage, for example, 1.5KV.
In some embodiments, the substrate 21 is further provided with a coolant gas pipe 4, the coolant gas pipe 4 penetrates through the substrate 21, and one end of the coolant gas pipe 4 is disposed towards the wafer 3. The wafer desorbing apparatus 5 further includes: the second exhaust module 55 is used for exhausting the refrigerant gas in the refrigerant gas pipeline 4 before the auxiliary gas is introduced into the reaction chamber 1 by the gas conveying module 51. In the embodiment of the invention, by exhausting the refrigerant gas in the refrigerant gas pipeline 4, the problem that the position of the wafer 3 is deviated due to the fact that the wafer 3 is jacked up by the refrigerant gas in the refrigerant gas pipeline 4 after the wafer 3 is desorbed with the electrostatic chuck 2 can be avoided.
The present invention also provides a semiconductor device, fig. 10 is a schematic diagram of a structure of the semiconductor device provided in the embodiment of the present invention, and as shown in fig. 10, the semiconductor device includes: the semiconductor device comprises a reaction chamber 1 and an electrostatic chuck 2 arranged in the reaction chamber 1, wherein the electrostatic chuck 2 comprises a substrate 21 and an electrostatic electrode 22, the substrate 21 is used for bearing a wafer 3, the electrostatic electrode 22 is arranged in the substrate 21 and is insulated from the substrate 21, and the semiconductor device further comprises the wafer desorption device 5.
The wafer desorbing apparatus 5 includes: the device comprises a gas transmission module, a power removal module, a power supply module and a first exhaust module. The gas transmission module is used for introducing auxiliary gas into the reaction chamber 1 until the auxiliary gas in the reaction chamber 1 reaches a preset pressure. The power-off module is used for removing the electrostatic voltage absorbed by the wafer 3 to zero. The power supply module is connected to the electrostatic electrode 22 for providing a reverse voltage to the electrostatic electrode 22, the reverse voltage having a polarity opposite to that of the electrostatic voltage, so as to ionize the auxiliary gas. The first exhaust module is used for exhausting the auxiliary gas out of the reaction chamber 1 after the duration of the power supply module supplying the reverse voltage to the electrostatic electrode 22 reaches the preset duration.
The semiconductor device provided by the embodiment of the invention adopts the wafer desorption device, so that the time required by desorption of the wafer 3 and the electrostatic chuck 2 can be shortened, the production efficiency of the wafer 3 is improved, the occurrence of plasma-induced damage (Plasma induced damage, PID) on the wafer 3 is avoided, and the product yield of the wafer is improved.
In the embodiment of the invention, the semiconductor device is suitable for a plasma etching process, as shown in fig. 10, a dielectric window 6 is further disposed above the reaction chamber 1 of the semiconductor, an inductive coupling coil 7 is installed above the dielectric window 6, and an upper radio frequency source 81 is connected with the inductive coupling coil 7 through a matcher 82 and is used for exciting gas to be excited in the chamber into plasma. The lower rf source 91 is connected to the base 21 of the electrostatic chuck 2 through the lower matching unit 92, and is used for generating a direct current self-bias voltage on the surface of the wafer 3, attracting plasma, and performing processing on the surface of the wafer 3.
Although not shown in fig. 10, the gas delivery module may be connected to the dielectric window 6 so that the auxiliary gas may enter the reaction chamber 1 from the dielectric window 6, and the gas exhaust module 54 may be connected to the bottom of the sidewall of the reaction chamber 1 so that the auxiliary gas may be exhausted from the bottom of the reaction chamber 1 to the reaction chamber 1.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.

Claims (8)

1. A wafer desorption method for use in a semiconductor device comprising a reaction chamber and an electrostatic chuck disposed in the reaction chamber, the electrostatic chuck comprising a substrate for carrying a wafer and an electrostatic electrode disposed within the substrate, the wafer desorption method comprising:
introducing auxiliary gas into the reaction chamber until the auxiliary gas in the reaction chamber reaches a preset pressure;
evacuating the electrostatic voltage absorbed by the wafer to zero;
providing a reverse voltage to the electrostatic electrode, the reverse voltage having a polarity opposite to the electrostatic voltage to ionize the assist gas;
stopping providing the reverse voltage to the electrostatic electrode after the duration of providing the reverse voltage to the electrostatic electrode reaches a preset duration, and discharging the auxiliary gas out of the reaction chamber to complete desorption of the electrostatic chuck and the wafer;
prior to the step of introducing an assist gas into the reaction chamber, the wafer desorption method further comprises:
evacuating refrigerant gas in a refrigerant gas pipeline in the semiconductor device;
after the stopping of the supply of the reverse voltage to the electrostatic electrode, the method further comprises:
and evacuating the reverse voltage.
2. The wafer desorption method according to claim 1, wherein the preset time period is 0.5s to 10s.
3. The wafer desorption method according to claim 2, wherein the preset time period is 0.5s to 3s.
4. The wafer desorption method of claim 1, wherein the assist gas comprises: argon, oxygen, nitrogen or helium.
5. The wafer desorption method of claim 1, wherein the flow rate of the assist gas is 100sccm to 2000sccm.
6. The wafer desorption method according to claim 1, wherein the preset pressure is 50mT to 500mT.
7. The wafer desorption method according to claim 1, wherein the absolute value of the reverse voltage is 1.8KV to 4.5KV.
8. A wafer desorbing device for use in a semiconductor apparatus comprising a reaction chamber and an electrostatic chuck disposed in the reaction chamber, the electrostatic chuck comprising a substrate for carrying a wafer and an electrostatic electrode disposed within the substrate; the wafer desorbing device is characterized by comprising:
the gas transmission module is used for introducing auxiliary gas into the reaction chamber until the auxiliary gas in the reaction chamber reaches a preset pressure;
the power-off module is used for removing the electrostatic voltage absorbed on the wafer to zero;
a power supply module for providing a reverse voltage to the electrostatic electrode, the reverse voltage having a polarity opposite to the electrostatic voltage so as to ionize the auxiliary gas;
the first exhaust module is used for exhausting the auxiliary gas out of the reaction chamber after the duration of the reverse voltage provided by the power supply module to the electrostatic electrode reaches a preset duration;
and the second exhaust die is used for exhausting the refrigerant gas in the refrigerant gas pipeline in the semiconductor device before the gas transmission module is used for introducing the auxiliary gas into the reaction chamber.
CN202010440572.7A 2020-05-22 2020-05-22 Wafer desorption method and device Active CN111564404B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010440572.7A CN111564404B (en) 2020-05-22 2020-05-22 Wafer desorption method and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010440572.7A CN111564404B (en) 2020-05-22 2020-05-22 Wafer desorption method and device

Publications (2)

Publication Number Publication Date
CN111564404A CN111564404A (en) 2020-08-21
CN111564404B true CN111564404B (en) 2023-12-22

Family

ID=72075211

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010440572.7A Active CN111564404B (en) 2020-05-22 2020-05-22 Wafer desorption method and device

Country Status (1)

Country Link
CN (1) CN111564404B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101226871A (en) * 2007-01-15 2008-07-23 北京北方微电子基地设备工艺研究中心有限责任公司 Method for desorption of silicon slice
CN208923080U (en) * 2018-11-23 2019-05-31 长鑫存储技术有限公司 The static release device of electrostatic chuck

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6013740B2 (en) * 2012-02-03 2016-10-25 東京エレクトロン株式会社 Detachment control method and control device for plasma processing apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101226871A (en) * 2007-01-15 2008-07-23 北京北方微电子基地设备工艺研究中心有限责任公司 Method for desorption of silicon slice
CN208923080U (en) * 2018-11-23 2019-05-31 长鑫存储技术有限公司 The static release device of electrostatic chuck

Also Published As

Publication number Publication date
CN111564404A (en) 2020-08-21

Similar Documents

Publication Publication Date Title
US9972503B2 (en) Etching method
EP2911187A1 (en) Etching method
CN107431012B (en) Method for etching etched layer
JPH0794500A (en) Forming method of film
TWI324361B (en)
TWI756424B (en) Method of cleaming plasma processing
JP4642809B2 (en) Plasma processing method and plasma processing apparatus
TW201916159A (en) Plasma processing method
JP2005039015A (en) Method and apparatus for plasma processing
JPH09120988A (en) Plasma processing method
JP2022103235A (en) Plasma processing apparatus and plasma processing method
US20090242128A1 (en) Plasma processing apparatus and method
US11282701B2 (en) Plasma processing method and plasma processing apparatus
JP2019169635A (en) Cleaning method and processing unit
CN111564404B (en) Wafer desorption method and device
JPH1027780A (en) Plasma treating method
US9922841B2 (en) Plasma processing method
CN117677013A (en) Method for removing residual charge of electrostatic chuck and semiconductor process equipment
JP2948053B2 (en) Plasma processing method
JP2001093877A (en) Method for manufacturing semiconductor device
JP5727853B2 (en) Plasma generation method
TWI725406B (en) Plasma etching method and device
JP2003124186A (en) Plasma processing method
JP2022012610A (en) Substrate processing method, storage medium, and substrate processing device
JP2021005579A (en) Dry-etching method and manufacturing method of device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant