JPS59119719A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59119719A
JPS59119719A JP23312982A JP23312982A JPS59119719A JP S59119719 A JPS59119719 A JP S59119719A JP 23312982 A JP23312982 A JP 23312982A JP 23312982 A JP23312982 A JP 23312982A JP S59119719 A JPS59119719 A JP S59119719A
Authority
JP
Japan
Prior art keywords
layer
type
thickness
growth
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23312982A
Other languages
Japanese (ja)
Inventor
Toshiyuki Tanahashi
俊之 棚橋
Kazuo Nakajima
一雄 中嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23312982A priority Critical patent/JPS59119719A/en
Publication of JPS59119719A publication Critical patent/JPS59119719A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
    • H01S5/32Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/323Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/3235Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength longer than 1000 nm, e.g. InP-based 1300 nm and 1500 nm lasers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/02546Arsenides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02623Liquid deposition
    • H01L21/02625Liquid deposition using melted materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
    • H01S5/32Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/323Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/3235Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength longer than 1000 nm, e.g. InP-based 1300 nm and 1500 nm lasers
    • H01S5/32391Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength longer than 1000 nm, e.g. InP-based 1300 nm and 1500 nm lasers based on In(Ga)(As)P

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To obtain an excellent Al1-xInxAs layer of not less than 0.1mum thickness by previously designing thickness on an InP group semiconductor substrate or a melting liquid for growth constituting an AlInAs layer to a specific value or more when the melting liquid is brought into contact with the upper section of the substrate and the AlInAs layer is grown. CONSTITUTION:An N<+> type InP clad layer 12, an InGaAsP active layer 13, a P type AlInAs clad layer 14, a P type InP clad layer 15, a P type InGaAs contact layer 16 and an N type InP cap layer 17 are laminated on the N<+> type InP substrate 11 and liquid-phase epitaxial grown, and a window is bored to the layer 17 and a P-side electrode 18 being in contact with the layer 16 is attached and an N-side electrode 19 on the back of the substrate 11 respectively, thus manufacturing the semiconductor laser device. In the constitution, the thickness of a melt for growth is brought to 1mm. or more and a growth starting temperature is selected to approximately 750 deg.C and cooling velocity to approximately 0.3 deg.C/min when the P type AlInAs clad layer 14 functioning as confining carriers is grown. Accordingly, thickness of 0.1mm. or more required for confining carriers is obtained positively.

Description

【発明の詳細な説明】 (al  発明の技術分野 本発明は半導体装置の製造方法に係り、特にインジウム
・燐(InP )結晶基板上に液相エピタキシアル成長
法によりアルミニウム・インジウム・砒素(AI21n
Aa)層を形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and in particular, it relates to a method for manufacturing a semiconductor device.
Aa) Concerning a method of forming a layer.

(bl  従来技術と問題点 AQ+−xlng As結晶はInP結晶と格子整合す
るときは、InP結晶のバンドギャップ(1,35eV
)よりも大きなバンドギャップを有するため、光間し込
め効果が大きく、InPを基板とする半導体レーザ素子
等を作成するのに非常に有用な結晶である。ところが従
来All+−xlnXAs結晶は1、液相エピタキシア
ル成長法では非常に成長させにりく、近年に至り漸くご
く薄い層の成長が可能となった。
(bl Conventional technology and problems
), it has a large optical intercalation effect and is a very useful crystal for producing semiconductor laser devices etc. using InP as a substrate. However, conventional All+-xlnXAs crystals have been very difficult to grow using liquid phase epitaxial growth, and in recent years it has finally become possible to grow extremely thin layers.

しかし半導体素子を構成するには、良質なNll−XI
nxAs結晶層の厚さは通富0.1Cμm〕程度以上を
必要とするが、このような厚さにA12.−、■nXA
s結晶を成長させることは、依然として不可能であった
However, in order to construct semiconductor devices, high-quality Nll-XI
The thickness of the nxAs crystal layer needs to be about 0.1 Cμm or more, but A12. −,■nXA
It remained impossible to grow s crystals.

(C1発明の目的 本発明の目的は、M I−X I nx As層の成長
用メルト成長用原料融液)の厚さhを、h≧1 (nu
n)にすることによって、良質なN1ケIn)(As層
を0.1〔μm〕以上の厚さに成長させることの可能な
、半導体装置の製造方法を提供することにある。
(C1 Object of the Invention The object of the present invention is to set the thickness h of the raw material melt for melt growth for growing the M I-X I nx As layer) such that h≧1 (nu
It is an object of the present invention to provide a method for manufacturing a semiconductor device, which makes it possible to grow a high-quality N1 (In) (As) layer to a thickness of 0.1 [μm] or more by using n).

(d)  発明の構成 本発明の特徴は、インジウム・燐系半導体結晶基板上。(d) Structure of the invention The feature of the present invention is on an indium/phosphorous semiconductor crystal substrate.

またはインジウム・燐系半導体結晶層上に、所定の成長
用融液を接触せしめてアルミニウム・インジウム・砒素
よりなる半導体層を含む半導体積層構造を液相成長せし
めるに際し、前記半導体結晶基板または半導体層上に接
触せしめる前記アルミニウム・インジウム・砒素層の成
長用融液の前記半導体結晶基板または半導体結晶層上に
おける厚さを、1  (mm)以上とすることにある。
Alternatively, when a predetermined growth melt is brought into contact with an indium/phosphorous semiconductor crystal layer to cause liquid phase growth of a semiconductor stacked structure including a semiconductor layer made of aluminum, indium, and arsenic, the semiconductor crystal substrate or the semiconductor layer is The thickness of the melt for growing the aluminum/indium/arsenic layer on the semiconductor crystal substrate or the semiconductor crystal layer that is brought into contact with the semiconductor crystal substrate is 1 (mm) or more.

(el  発明の実施例 本願の発明者らは、液相エピタキシアル成長法によるA
Q’1−xInx ’As層の成長について種々検討の
結果、成長用メルトの量を十分に多くすることにより、
M +−x I nx AsJiiを液相成長させ得る
ことを見出した。即ち液相エピタキシアル成長法で厚い
Ml +−xIr+xAs層を成長させることが出来な
かったのは、Nの分配係数が非常に大きいため、液相中
のN含有率が急速に減少するためであることに着目し、
使用する成長用メルトの量を増大することによって、液
相中のNの含有率の減少速度を相対的に低下させる方法
を試みた。第1図はその結果を示す図で、縦軸は成長用
メルトのメルト溜め中における厚さh(後述)、横軸は
AIL−xInxAsの臨界成長厚さ、即ち成長させ得
る良質なA121−X I nx As層の厚さで、こ
れ以上厚く成長させても良質な結晶は得られないという
最大厚さを示す。なお同図は、凡そ780(”C)の成
長温度で液相エピタキシアル成長せしめた結果を示すも
のである。
(el Embodiment of the Invention The inventors of the present application have developed A
Q'1-xInx 'As a result of various studies regarding the growth of the As layer, by increasing the amount of growth melt sufficiently,
It has been found that M + -x Inx AsJii can be grown by liquid phase growth. That is, the reason why it was not possible to grow a thick Ml + - x Ir + x As layer using the liquid phase epitaxial growth method is because the N content in the liquid phase decreases rapidly because the N distribution coefficient is very large. Focusing on that,
An attempt was made to relatively reduce the rate of decrease in the N content in the liquid phase by increasing the amount of growth melt used. Figure 1 shows the results, where the vertical axis is the thickness h (described later) of the growth melt in the melt reservoir, and the horizontal axis is the critical growth thickness of AIL-xInxAs, that is, the high-quality A121-X that can be grown. The thickness of the Inx As layer indicates a maximum thickness at which a good quality crystal cannot be obtained even if the layer is grown thicker. The figure shows the results of liquid phase epitaxial growth at a growth temperature of approximately 780°C.

図より明らかな如く臨界成長厚さはAlt r−x I
 nx As層成長用のメルトの厚さhに強く依存し、
hの増大に比例して増加する。従って厚いMl +−x
 Ir+xAs層を成長させるには、成長用メルトの厚
さhを大きくしてやれば良い。半導体素子の構造上N、
ヶInXAs層の厚さは通常0.1〔μm〕程度以上を
必要とする。この厚さのAll’ +−x I nXA
s1itを成長させるには、同図より成長用メルトの厚
さhは凡そI  (mm)以上必要であることが判明し
た。
As is clear from the figure, the critical growth thickness is Alt r-x I
strongly depends on the melt thickness h for nx As layer growth;
It increases in proportion to the increase in h. Therefore thick Ml +−x
In order to grow the Ir+xAs layer, it is sufficient to increase the thickness h of the growth melt. Due to the structure of the semiconductor element, N,
The thickness of the InXAs layer usually needs to be about 0.1 [μm] or more. All' +-x I nXA of this thickness
In order to grow s1it, it was found from the same figure that the thickness h of the growth melt is required to be approximately I (mm) or more.

第2図は液相成長方法に使用する成長用ボートの要部を
示す断面図である。同図において、1はカーボン等から
なるボート基体、2はスライダ、3は成長用メルト、4
はメルト溜め、5はInP半導体基板等の被処理半導体
基板である。
FIG. 2 is a sectional view showing the main parts of a growth boat used in the liquid phase growth method. In the figure, 1 is a boat base made of carbon or the like, 2 is a slider, 3 is a growth melt, and 4 is a boat base made of carbon or the like.
5 is a melt reservoir, and 5 is a semiconductor substrate to be processed, such as an InP semiconductor substrate.

本発明はM +−x I nx As層を成長させるに
際し、第1図に示す結果に基づき、上記メルト溜め4中
における成長用メルト3の厚さhを大きくしてやること
により、成長用メルトの量を大きなものとしておき、も
ってAll!+−xIn)(As層の成長に伴って液相
中から失われるNの量の割合を相対的に小さくする。即
ちメルト3中におけるNの含有率の変動を少なくしてや
ることを骨子とする。
In the present invention, when growing an M + -x Inx As layer, the amount of the growth melt is increased by increasing the thickness h of the growth melt 3 in the melt reservoir 4, based on the results shown in FIG. Let's make it a big thing and say "All!" +-xIn) (The ratio of the amount of N lost from the liquid phase with the growth of the As layer is made relatively small. That is, the main point is to reduce the fluctuation of the N content in the melt 3.

以下本発明の一実施例を第1図及び第2図を参照しなが
ら第3図により説明する。
An embodiment of the present invention will be described below with reference to FIG. 3 while referring to FIGS. 1 and 2.

本実施例では面方位(100)のn中型1nP基板上1
1上に、n″型InPよりなるクラッド層12. In
GaAsPよりなる活性層13.p型Al2InAsよ
りなるクラッド層14.I)型InPよりなるクラッド
層15.p型InGaAsPよりなるコンタクト層16
.n型1nPよりなるキャップ層17を液相エピタキシ
アル成長により順次形成して、半導体レーザ装置を作成
する例である。
In this example, 1
1, a cladding layer 12 made of n″ type InP is disposed on top of the cladding layer 12. In
Active layer 13 made of GaAsP. Cladding layer 14 made of p-type Al2InAs. I) Cladding layer 15 made of type InP. Contact layer 16 made of p-type InGaAsP
.. This is an example in which a semiconductor laser device is manufactured by sequentially forming an n-type 1nP cap layer 17 by liquid phase epitaxial growth.

n′−型InP基板11上に上記積層構造を形成するに
は、それぞれ次のような液相組成を有する成長用メルト
を使用する。なお以下に記す組成は原子数比で示す。
In order to form the above laminated structure on the n'-type InP substrate 11, a growth melt having the following liquid phase composition is used. Note that the compositions described below are shown in atomic ratios.

第1層:n・型1nP層12 In: 0.925.  P : 0.032.  S
n: 0.043第2層=p型InXGa、x八s+−
y P y層13x=o、3;yζ0.35 In:  0.8413.  八s:  0.1373
.  Ga:  0.0164゜Cd : 0.005
0 第3層:p型AL−xlnXAs層14X=0.52 Ml : 0.0006. As: 0.1413. 
In: 0.8513゜cd:0.006B 第4屓=p型1nP層15 In: 0.958.P : 0.033.  Cd:
’ 0.009第5層=p型InxG’a(−z AS
I−y P y層16X#0.7 ; y#0.35 In: 0.8410. As: 0.1372. G
a: 0.0165゜P  : 0.0050.Zn:
 0.0003第6層=n型InP層 In: 0.958.   P  : 0.033. 
 Sn: 0.009なお第3層目のp型Ml +−x
 I nxAs層14成長用メルトのメルト厚は凡そ5
(mm)とした。また成長開始温度は略790C’C)
とし、冷却速度を略0.3〔℃〕で温度を降下させなが
ら連続的に成長を行う。
First layer: n-type 1nP layer 12 In: 0.925. P: 0.032. S
n: 0.043 2nd layer = p-type InXGa, x8s+-
y P y layer 13x=o, 3; yζ0.35 In: 0.8413. Eights: 0.1373
.. Ga: 0.0164°Cd: 0.005
0 Third layer: p-type AL-xlnXAs layer 14X=0.52 Ml: 0.0006. As: 0.1413.
In: 0.8513°cd: 0.006B 4th layer=p-type 1nP layer 15 In: 0.958. P: 0.033. Cd:
' 0.009 5th layer = p-type InxG'a (-z AS
I-y P y layer 16X#0.7; y#0.35 In: 0.8410. As: 0.1372. G
a: 0.0165°P: 0.0050. Zn:
0.0003 6th layer = n-type InP layer In: 0.958. P: 0.033.
Sn: 0.009 Third layer p-type Ml +-x
The melt thickness of the melt for growing the InxAs layer 14 is approximately 5
(mm). Also, the growth starting temperature is approximately 790C'C)
Growth is performed continuously while decreasing the temperature at a cooling rate of about 0.3 [° C.].

上記各層の成長時間はそれぞれ凡そ700秒、15秒。The growth time of each layer was approximately 700 seconds and 15 seconds, respectively.

1230秒、200秒、60秒、40秒である。They are 1230 seconds, 200 seconds, 60 seconds, and 40 seconds.

この結果InP基板11上に下記のような厚さを有する
各層が形成された。
As a result, layers having the following thicknesses were formed on the InP substrate 11.

第1層二〇″″型InPJit12  ・・・・・・・
・・ 3 〔μm〕第2層:p型InGaAsP層13
・・・・・・0.2〃第3層:p型MI I−x I 
nX’As層14・0.5  〃第4層:p型InP層
15  ・・・・・・・・・ 1.0〃第5層:p型I
nGaAsP層16・・・・・・0.5〃第6層:n型
1nP層17  ・・・・・・・・・ 0.3〃このよ
うに本実施例では第3層のp型Ml r−x I nX
A s層14は、クラッド層としてキャリア閉じ込めに
必要な0.1〔μm〕以上の厚さが得られた。
1st layer 20″″ type InPJit12 ・・・・・・・・・
... 3 [μm] Second layer: p-type InGaAsP layer 13
・・・・・・0.2〃Third layer: p-type MI I-x I
nX'As layer 14.0.5 4th layer: p-type InP layer 15 1.0 5th layer: p-type I
nGaAsP layer 16...0.5 6th layer: n-type 1nP layer 17...0.3 Thus, in this example, the third layer p-type Ml r −x I nX
The As layer 14 had a thickness of 0.1 [μm] or more, which is necessary for carrier confinement as a cladding layer.

上述のように成長させたダブルへテロ構造のウェーハに
、所定のパターンを有する5i02膜(図示せず)を形
成し、これをマスクとして第6層目のn型InP層17
を選択的に除去して、幅凡そ5 〔μm〕のストライプ
状の窓を開口した後、金−亜鉛(Au  Zn)よりな
るp電極18を形成する。次いで、n型InP基板11
の背面に金−錫(八u−5n)よりなるn電極19を形
成する。しかる後、襞間法を施して個々の素子に分離す
ることにより、半導体レーザ素子が得られる。
A 5i02 film (not shown) having a predetermined pattern is formed on the double heterostructure wafer grown as described above, and using this as a mask, the sixth n-type InP layer 17 is formed.
is selectively removed to open a striped window with a width of about 5 μm, and then a p-electrode 18 made of gold-zinc (Au Zn) is formed. Next, the n-type InP substrate 11
An n-electrode 19 made of gold-tin (8u-5n) is formed on the back surface of the substrate. Thereafter, a semiconductor laser device is obtained by performing a fold-to-fold method to separate the semiconductor laser device into individual devices.

以上のようにして得られた本実施例の半導体レーザ素子
は、活性層13のp側のへテロバリヤーが、従来の半導
体レーザ素子のp型!nPJMよりもバンドギャップの
大きいp型A12 +−x InXAsnXAs用いて
構成されており、しかもp型M)+−)<InxAsn
XAs層さが0.1〔μm〕以上あるので、キャリアの
閉じ込め効果が大きい。闇値電流1 thは、I th
oc exp (T/ To )で表されるが、従来の
半導体レーザ素子では上式におけるToが凡そ60(’
K)であったのに対し、本実施例では凡そ1oo、rK
:+と増大し、しかも再現性も向上した。
In the semiconductor laser device of this example obtained as described above, the heterobarrier on the p side of the active layer 13 is the p-type of the conventional semiconductor laser device! It is constructed using p-type A12 +-x InXAsnXAs, which has a larger band gap than nPJM, and moreover, p-type M)+-)<InxAsn
Since the XAs layer has a thickness of 0.1 [μm] or more, the carrier confinement effect is large. Dark value current 1 th is I th
It is expressed as oc exp (T/To), but in conventional semiconductor laser devices, To in the above equation is approximately 60 ('
K), whereas in this example, it is approximately 1oo, rK
: Increased to +, and reproducibility also improved.

なお上記一実施例ではInGaAsPよりなる活性層1
3の一方にのみAt2 +−x I nXAsよりなる
クラッド層14を設けた例を示したが、本発明はこれに
限定されるものではない。即ちM +−x I nXA
s層は活性層13のいずれか一方或いは両側に設けても
良い。
Note that in the above embodiment, the active layer 1 made of InGaAsP
Although an example has been shown in which the cladding layer 14 made of At2 + -x I nXAs is provided only on one side of the substrate 3, the present invention is not limited thereto. That is, M +−x I nXA
The s-layer may be provided on either one or both sides of the active layer 13.

更に本発明を用いて形成するM I−X LnxAs層
は、半導体レーザ装置のクラッド層に限定されるもので
はなく 、At)+−X InXAsが如何なる目的に
使用されるものであってもよい。本発明はInP系の半
導体結晶基板或いはInP系の半導体結晶層上に、At
2+−xInxAs層を形成する総ての場合に用いるこ
とが出来る。
Further, the M I-X LnxAs layer formed using the present invention is not limited to the cladding layer of a semiconductor laser device, and At)+-X InXAs may be used for any purpose. The present invention provides an InP based semiconductor crystal substrate or an InP based semiconductor crystal layer.
It can be used in all cases of forming 2+-xInxAs layers.

(fl  発明の詳細 な説明した如(本発明によれば、液相エピタキシアル成
長法により、0.1〔μm〕以上の厚さを有するMl 
+−x I nXAs層を容易且つ再現性良く成長させ
ることが可能である。従ってInP結晶を基板とする半
導体装置を構成するのにA12 +−x I販Asを用
いることが出来るようになり、半導体レーザ装置等の特
性が向上し、しかも製造が容易となる。
According to the present invention, Ml having a thickness of 0.1 [μm] or more is grown by a liquid phase epitaxial growth method.
It is possible to grow a +-x I nXAs layer easily and with good reproducibility. Therefore, A12+-x As can be used to construct a semiconductor device using an InP crystal as a substrate, improving the characteristics of a semiconductor laser device, etc., and making manufacturing easier.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理及び効果を示す曲線図、第2図は
本発明の一実施例を示す要部断面図、第3図は上記一実
施例の製造工程と得られた半導体装置を示す要部断面図
である。 図において、1は液相成長用ポート基体、2はスライダ
、3は成長用メルト、4はメルト溜め、5はInP半導
体基板く被処理基板)、11はn+型InP基板、12
はn型InPよりなるクラッド層、13はInGaAs
Pよりなる活性層、14はp型Ml l−X I nx
 Asよりなるクラッド層、I5はp型InGaAsP
よりなるクラッド層、16はp型1nGaAsPよりな
るコンタクト層、17はn型InPよりなるキャップ層
を示す。 第1rM 簗 2図 第3W1 8 −頒一
FIG. 1 is a curve diagram showing the principle and effect of the present invention, FIG. 2 is a cross-sectional view of a main part showing an embodiment of the present invention, and FIG. 3 is a diagram showing the manufacturing process of the above embodiment and the semiconductor device obtained. FIG. In the figure, 1 is a port substrate for liquid phase growth, 2 is a slider, 3 is a growth melt, 4 is a melt reservoir, 5 is an InP semiconductor substrate (substrate to be processed), 11 is an n+ type InP substrate, 12
13 is a cladding layer made of n-type InP, and 13 is InGaAs.
Active layer made of P, 14 is p-type Ml l-X I nx
Cladding layer made of As, I5 is p-type InGaAsP
16 is a contact layer made of p-type 1nGaAsP, and 17 is a cap layer made of n-type InP. 1st rM Yan Figure 2 3rd W1 8 - Koichi

Claims (1)

【特許請求の範囲】[Claims] インジウム・燐系半導体結晶基板上、またはインジウム
・燐系半導体結晶層上に、所定の成長用融液を接触せし
めてアルミニウム・インジウム・砒素よりなる半導体層
を含む半導体積層構造を液相成長せしめるに際し、前記
半導体結晶基板または半導体層上に接触せしめる前記ア
ルミニウム・インジウム・砒素層の成長用融液の前記半
導体結晶基板または半導体結晶層上における厚さを、1
(mm)以上とすることを特徴とする半導体装置の製造
方法。
When a semiconductor layered structure including a semiconductor layer made of aluminum, indium, and arsenic is grown in a liquid phase by contacting a prescribed growth melt on an indium/phosphorous semiconductor crystal substrate or an indium/phosphorus semiconductor crystal layer. , the thickness on the semiconductor crystal substrate or semiconductor crystal layer of the melt for growing the aluminum-indium-arsenic layer that is brought into contact with the semiconductor crystal substrate or semiconductor layer is 1.
(mm) or more.
JP23312982A 1982-12-24 1982-12-24 Manufacture of semiconductor device Pending JPS59119719A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23312982A JPS59119719A (en) 1982-12-24 1982-12-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23312982A JPS59119719A (en) 1982-12-24 1982-12-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59119719A true JPS59119719A (en) 1984-07-11

Family

ID=16950195

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23312982A Pending JPS59119719A (en) 1982-12-24 1982-12-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59119719A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5309467A (en) * 1991-10-08 1994-05-03 Nec Corporation Semiconductor laser with InGaAs or InGaAsP active layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5309467A (en) * 1991-10-08 1994-05-03 Nec Corporation Semiconductor laser with InGaAs or InGaAsP active layer

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