JPS6021586A - Compound semiconductor device - Google Patents

Compound semiconductor device

Info

Publication number
JPS6021586A
JPS6021586A JP58127682A JP12768283A JPS6021586A JP S6021586 A JPS6021586 A JP S6021586A JP 58127682 A JP58127682 A JP 58127682A JP 12768283 A JP12768283 A JP 12768283A JP S6021586 A JPS6021586 A JP S6021586A
Authority
JP
Japan
Prior art keywords
layer
inp
ingaasp
oxide film
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58127682A
Other languages
Japanese (ja)
Inventor
Motonao Hirao
平尾 元尚
Yoshihisa Fujisaki
芳久 藤崎
Shinji Tsuji
伸二 辻
Yoshinori Nakayama
義則 中山
Yasutoshi Kashiwada
柏田 泰利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58127682A priority Critical patent/JPS6021586A/en
Publication of JPS6021586A publication Critical patent/JPS6021586A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • H01S5/2275Buried mesa structure ; Striped active layer mesa created by etching

Abstract

PURPOSE:To prevent the variation of element shape by side etching by a method wherein the surface layer of an InGaAsP/InP series multilayer epitaxial crystal is made of InP, and an oxide film is formed thereon and chemically etched. CONSTITUTION:An N type InP layer 6, an InGaAsP active layer 5, a P type InP clad layer 4, an InGaAsP contact layer 3, an InP layer 2, and an InGaAsP cap layer 1 are grown on an InP substrate 7 by a liquid growing method. The cap layer 1 is removed by etching, a phosphorus glass film being formed on the InP layer 2 and made as a mask 8, and being then etched with Br-methanol solution. Then, the side surface is filled with a P type InP layer 9, an N type Inp layer 10, and an InGaAsP layer 11 by liquid phase growth. Since no side etching generates, the width of an active layer can be set at a constant value with good reproducibility. After removal of the oxide film and the InP layer 2, a P-side electrode 12 and an N-side electrode 13 are formed and then the laser diode is completed.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、InGaAsP/InP系材料を用いた異種
接金材料に係り、特に長波長半導体レーザ、その他長波
長発光ダイオード、PET等にも利用可能な化合物半導
体装置に関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a dissimilar welding material using InGaAsP/InP-based materials, and is particularly applicable to long wavelength semiconductor lasers, other long wavelength light emitting diodes, PET, etc. The present invention relates to a compound semiconductor device.

〔発明の背景〕[Background of the invention]

長波長レーザ、特に埋込みへテロレーザは活性層を含む
多層成長層を酸化膜をマスクとしてメサエッチングし〜
1.5μm幅の活性層幅を制御する必要がある。従来の
長波長レーザは例えば第1図に示すようなn −In 
p基板上に4層構造の多層成長層”” I”P、 工n
GaAsP、p I”P。
Long wavelength lasers, especially buried hetero lasers, perform mesa etching on multilayer growth layers including the active layer using an oxide film as a mask.
It is necessary to control the active layer width to a width of 1.5 μm. A conventional long wavelength laser is, for example, an n-In laser as shown in FIG.
Multilayer growth layer with 4-layer structure on p substrate
GaAsP, p I”P.

I n G a A s Pを用い、第4層のInGa
AsP表面ノー上に酸化膜を形成し、この酸化膜をマス
クとして化学エツチングによ)メサ構造を形成していた
(b)。
Using InGaAsP, the fourth layer of InGa
An oxide film was formed on the AsP surface, and a mesa structure was formed by chemical etching using this oxide film as a mask (b).

このようなInGaAsP4元混晶を用いると第2図に
示すように混晶組成と共に結晶のサイドエツチングが生
じ、しかも、このサイドエツチングは酸化膜の被着条件
などに左右されサイドエッチング量を定量的に制御する
ことが困難になる。一方、素子に電極を形成する場合を
考えると、サイドエツチングの大きいAs量の多い混晶
組成の方が接触抵抗を低くする上で有利である。
When such an InGaAsP quaternary mixed crystal is used, side etching of the crystal occurs depending on the composition of the mixed crystal as shown in Figure 2. Moreover, this side etching is influenced by the deposition conditions of the oxide film, and the amount of side etching cannot be determined quantitatively. becomes difficult to control. On the other hand, when considering the case where electrodes are formed in a device, a mixed crystal composition with a large amount of As and a large amount of side etching is advantageous in terms of lowering the contact resistance.

従来の技術では、このサイドエツチング量を小さくする
ため接触抵抗的には不利なInPに近い組成を用いざる
を得なかったため、低接触抵抗の電極を形成するのに高
濃度のZn拡散技術が必要であった。7.nの拡散係数
は非常に大きいため、高表面濃度の浅い拡散層を再現性
よく得ることは極めて困難である。
In conventional technology, in order to reduce the amount of side etching, it was necessary to use a composition close to InP, which is disadvantageous in terms of contact resistance, so high concentration Zn diffusion technology is required to form electrodes with low contact resistance. Met. 7. Since the diffusion coefficient of n is very large, it is extremely difficult to obtain a shallow diffusion layer with high surface concentration with good reproducibility.

〔発明の目的〕[Purpose of the invention]

本発明は前述したような結晶のサイドエツチングによる
素子形状のバラツキを防止し、なおかつ拡散技術を用い
なくても結晶中へ結晶成長時に導入された不純物のみで
も低接触抵抗のオーム性電極をhsa度の高いInGa
AspまたはInGaAS混晶上に形成した半導体装置
を提供することにある。
The present invention prevents variations in the element shape due to the side etching of the crystal as described above, and can also form ohmic electrodes with low contact resistance at high temperatures even with impurities introduced into the crystal during crystal growth without using diffusion technology. High InGa
An object of the present invention is to provide a semiconductor device formed on Asp or InGaAS mixed crystal.

〔発明の概要〕[Summary of the invention]

本発明は上記に述べてきたような問題点をなくし、良好
なオーム性接触を有するInGaAsP/InP系半導
体装置を提供するもので、第3図(a)に示すような多
層構造結晶を形成する。本発明の特徴は多層結晶成長時
、将来電極を形成すべき第1のI”GaAapまたはI
 nG a A 84元Qr3元混晶上に第2のInP
層又は第2.第3のInP十InGaAsP層を設ける
ことにある。次いで、第3のI n G a A s 
PJ−は化学エツチングにより全面エッチオフし、第2
のI n P#表面上に所定のパターンを酸化膜をマス
クとして形成する。第3のInGaAsP4元混晶は、
結晶成長時、表面層がInPであると熱分解によシ成長
表面が鏡面状でなくなるのを防止するためのものである
から、結晶成長方法によって、表面からのPのwI離の
ない場合には必要ない。
The present invention eliminates the above-mentioned problems and provides an InGaAsP/InP-based semiconductor device having good ohmic contact, and forms a multilayer crystal structure as shown in FIG. 3(a). . The feature of the present invention is that during multilayer crystal growth, the first I''GaAap or I
nG a A second InP on 84-element Qr ternary mixed crystal
layer or second layer. The purpose is to provide a third InP and InGaAsP layer. Then, the third InGaAs
PJ- is completely etched off by chemical etching, and the second
A predetermined pattern is formed on the InP# surface using an oxide film as a mask. The third InGaAsP quaternary mixed crystal is
During crystal growth, if the surface layer is InP, this is to prevent the growing surface from becoming mirror-like due to thermal decomposition. is not necessary.

次いで、このInP表面層に形成したマスクによって多
層結晶をエツチングする。この場合表面層がInPであ
るため、適当なエツチング液を選択すると、全くサイド
エツチングのないメサ構造を形成することが可能になる
。更に、メサエッチで除去した部分に第4のInGaA
sP4元混晶または第5.第4のInP +InGaA
sP層を形成して平面構造を形成する。最後にI n 
PJ面の酸化マスクを除去し、InPを選択エツチング
して、メサ部の表面層を第2のInGaAsPまたはI
nGaAs4元または3元混晶として、この上に電極を
形成して菓子を作る。
Next, the multilayer crystal is etched using a mask formed on this InP surface layer. In this case, since the surface layer is InP, by selecting an appropriate etching solution, it is possible to form a mesa structure without any side etching. Furthermore, a fourth InGaA layer is added to the area removed by mesa etch.
sP quaternary mixed crystal or 5th. 4th InP + InGaA
A planar structure is formed by forming an sP layer. Finally I n
The oxidation mask on the PJ surface is removed, the InP is selectively etched, and the surface layer of the mesa is covered with a second InGaAsP or I
Confectionery is made by forming an electrode on the nGaAs quaternary or ternary mixed crystal.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を第3図によって説明する。本図
は埋込みへテロ型レーザの工程を示すものである。第3
図(a)に示すように多層成長層(6層)を行なった。
An embodiment of the present invention will be described below with reference to FIG. This figure shows the process of a buried hetero-type laser. Third
Multilayer growth (6 layers) was performed as shown in Figure (a).

(100)InP基板7上にn型I n P 6 、 
InGaAsP活性層5.1)型IflFクラッド層4
.InGaAsPニア:/タクト層3.IflP層2及
びI n G a A s Pキャラプ層1を液相成長
法により成長した。上記成長においてInGaAsPの
組成はInPと格子定数が一致し発光波長が1.3pm
に相当するIn0.48GaO,!12AS0.24P
O−76の組成にしI”GaAspコンタクト層は同様
にInPと格子定数が一致し、波光波長が〜1.5μm
に相当するI no、gGao、s+A8o、sPo、
gの組成を用いた。最上層のInGaAsP1は、活性
層のI ” G a A S P 5と同一組成を用い
た。該多層成長層上のキャップ層I n G a A 
s P 1を化学エツチングにより除去した後、第3図
(b)に示すように、InP層2の上に燐ガラス膜をC
VD法で形成し、エツチングマスクとした。更に該結晶
をf3r−メタノール溶液でエツチングして第3図(C
)の形状を形成した後、再び液相成長により該結晶の側
面を連続的にp型InP層9、n型InP層10、I 
nG a A s P層11で埋込み、第3図(d)の
構造を作った。この場合マスクの燐ガラス膜はInP結
晶上に被着されており、全くサイドエツチングが生じな
いため、マスクの燐ガラス膜幅を6μと一定にしておい
て、再現性よく、活性層の幅を2μの一定値にすること
が可能であった。埋込み成長後、酸化膜を除去し、表面
のInP層2を除去した後、p側電極、n側電極を形成
、ヘキ開によ#)aooμmのチアビイティを形成して
レーザダイオードを形成した。これら相当するInGa
Asp組成でバンドギャップが小さく容易に直列抵抗の
3〜4Ωと小さい埋込みへテロ型レーザを作ることが可
能であった。上記レーザは温度加速試験の結果IQ’h
r以上の平均寿命を有することが確認された。
(100) n-type I n P 6 on the InP substrate 7,
InGaAsP active layer 5.1) IfIFF cladding layer 4
.. InGaAsP near:/tact layer 3. The IflP layer 2 and the InGaAsP cap layer 1 were grown by liquid phase growth. In the above growth, the composition of InGaAsP has the same lattice constant as InP, and the emission wavelength is 1.3 pm.
In0.48GaO, ! 12AS0.24P
Similarly, the lattice constant of the I"GaAsp contact layer with the composition of O-76 matches that of InP, and the optical wavelength is ~1.5 μm.
I no, gGao, s+A8o, sPo, corresponding to
The composition of g was used. The uppermost InGaAsP1 layer has the same composition as the active layer I''GaASP5.The cap layer InGaAsP1 on the multilayer growth layer
After removing sP1 by chemical etching, a phosphorus glass film is deposited on the InP layer 2, as shown in FIG. 3(b).
It was formed by the VD method and used as an etching mask. Furthermore, the crystals were etched with f3r-methanol solution and shown in Figure 3 (C
), the side surfaces of the crystal are successively coated with a p-type InP layer 9, an n-type InP layer 10, an I
It was filled with an nGaAsP layer 11 to form the structure shown in FIG. 3(d). In this case, the phosphorus glass film of the mask is deposited on the InP crystal, and no side etching occurs. Therefore, the width of the phosphorus glass film of the mask is kept constant at 6μ, and the width of the active layer can be adjusted with good reproducibility. It was possible to maintain a constant value of 2μ. After the buried growth, the oxide film was removed, the InP layer 2 on the surface was removed, a p-side electrode and an n-side electrode were formed, and a chirality of #) aoo μm was formed by opening to form a laser diode. These corresponding InGa
With the Asp composition, it was possible to easily create a buried hetero laser with a small band gap and a series resistance of 3 to 4 Ω. The above laser has IQ'h as a result of temperature acceleration test.
It was confirmed that it has an average lifespan of r or more.

上記のInGaAsP4元結晶のサイドエツチングを防
止し、なおかつ低接触抵抗を有する電極を形成する方法
は、他の構造を有する埋込みへテロ型レーザ、および、
微少な発光、受光面積を有するInGaAsP4元結晶
系の長波長発光ダイオード、受光素子にも有効であるこ
とが確認された。
The above method of forming an electrode that prevents side etching of the InGaAsP quaternary crystal and has low contact resistance includes a buried hetero-type laser having another structure, and
It was confirmed that the present invention is also effective for long wavelength light emitting diodes and light receiving elements of the InGaAsP quaternary crystal system, which have minute light emitting and light receiving areas.

更に、レーザを構成するI ” G a A S Pの
4元組成は当然のことながら、1.0μm〜1.5μm
の所望の発光波長範囲を自由に選ぶことが可能である。
Furthermore, the quaternary composition of I''GaA SP constituting the laser is, of course, 1.0 μm to 1.5 μm.
It is possible to freely select a desired emission wavelength range.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の埋込へテロ構造レーザに用いる多層成長
結晶の断面図およびメサエッチングをした結晶の断面図
、第2図は酸化膜下のI n G a A s P44
元組成結晶のサイドエツチング量の関係を示したグラフ
、第3図は本発明を適用した場合の結晶構造の断面図及
び素子断面図である。 第3図において、 1・・・InGaAsPキャップ層、2・・・InPマ
スク形成層、3・・・P InGaAsP電極形成層、
4・・・p−InPクラッド層、5・・・InGaA、
sP活性層、6・・・n −In pバッファ層、7・
 n”−InP基板、8・・・燐ガラスエツチングマス
ク、9・・・p−InP埋込み層、10・・・n −I
n p埋込み層、11・・・InGaA8P埋込層、1
2°”p側電極、13 ・n 1ltl電極。 fJ i 図 第2図 1fJ3 図
Figure 1 is a cross-sectional view of a multilayer grown crystal used in a conventional buried heterostructure laser and a cross-sectional view of a mesa-etched crystal, and Figure 2 is a cross-sectional view of an I n Ga As P44 crystal under an oxide film.
FIG. 3 is a graph showing the relationship between the side etching amount of the original composition crystal, and is a cross-sectional view of the crystal structure and a cross-sectional view of the device when the present invention is applied. In FIG. 3, 1... InGaAsP cap layer, 2... InP mask forming layer, 3... P InGaAsP electrode forming layer,
4... p-InP cladding layer, 5... InGaA,
sP active layer, 6...n-In p buffer layer, 7.
n''-InP substrate, 8... phosphorus glass etching mask, 9... p-InP buried layer, 10... n-I
n p buried layer, 11...InGaA8P buried layer, 1
2°” p-side electrode, 13 ・n 1ltl electrode. fJ i Figure 2 1fJ3 Figure

Claims (1)

【特許請求の範囲】 1、InGaAsP/InP系多ノーエピタキシャル結
晶の表面に酸化膜を形成して部分的な化学エツチングを
行なうに際し、酸化膜を形成する表面層をInPとし、
その上に酸化膜を形成して部分的な化学エツチングを行
なうことを特徴とする化合物半導体装置。 2、上記多層結晶の表面層をInP層とするに際し結晶
成長時の最終成長層をIn()aAsPd元混晶として
のInGaASP4元混晶を選択エツチングにより除去
した後、第2層のInP層上に酸化膜を形成して部分的
な化学エツチングを行なうことを特徴とする特許請求の
範囲第1項記載の化合物半導体装置。 3、上記の部分エツチングに用いる酸化膜として燐ガラ
ス(PSG)膜を用いることを特徴とする特許請求の範
囲第1頁記載の化合物半導体装置。
[Claims] 1. When forming an oxide film on the surface of an InGaAsP/InP multi-no epitaxial crystal and performing partial chemical etching, the surface layer on which the oxide film is formed is InP,
A compound semiconductor device characterized by forming an oxide film thereon and performing partial chemical etching. 2. When forming the surface layer of the above multilayer crystal into an InP layer, after removing the InGaASP quaternary mixed crystal as the In()aAsPd original mixed crystal as the final growth layer during crystal growth by selective etching, the InP layer as the second layer is removed. 2. The compound semiconductor device according to claim 1, wherein an oxide film is formed on the surface of the semiconductor layer, and then partial chemical etching is performed. 3. The compound semiconductor device according to claim 1, wherein a phosphorous glass (PSG) film is used as the oxide film used in the partial etching.
JP58127682A 1983-07-15 1983-07-15 Compound semiconductor device Pending JPS6021586A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58127682A JPS6021586A (en) 1983-07-15 1983-07-15 Compound semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58127682A JPS6021586A (en) 1983-07-15 1983-07-15 Compound semiconductor device

Publications (1)

Publication Number Publication Date
JPS6021586A true JPS6021586A (en) 1985-02-02

Family

ID=14966098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58127682A Pending JPS6021586A (en) 1983-07-15 1983-07-15 Compound semiconductor device

Country Status (1)

Country Link
JP (1) JPS6021586A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4948753A (en) * 1984-03-27 1990-08-14 Matsushita Electric Industrial Co., Ltd. Method of producing stripe-structure semiconductor laser
US5316967A (en) * 1992-01-21 1994-05-31 Mitsubishi Denki Kabushiki Kaisha Method for producing semiconductor device
US5344791A (en) * 1991-07-05 1994-09-06 Hewlett-Packard Company Diffusion control of p-n junction location in multilayer heterostructure light emitting devices
US5786234A (en) * 1995-10-17 1998-07-28 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor laser

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4948753A (en) * 1984-03-27 1990-08-14 Matsushita Electric Industrial Co., Ltd. Method of producing stripe-structure semiconductor laser
US5344791A (en) * 1991-07-05 1994-09-06 Hewlett-Packard Company Diffusion control of p-n junction location in multilayer heterostructure light emitting devices
US5316967A (en) * 1992-01-21 1994-05-31 Mitsubishi Denki Kabushiki Kaisha Method for producing semiconductor device
US5786234A (en) * 1995-10-17 1998-07-28 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor laser

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