JPS59118317U - automatic gain control circuit - Google Patents

automatic gain control circuit

Info

Publication number
JPS59118317U
JPS59118317U JP931283U JP931283U JPS59118317U JP S59118317 U JPS59118317 U JP S59118317U JP 931283 U JP931283 U JP 931283U JP 931283 U JP931283 U JP 931283U JP S59118317 U JPS59118317 U JP S59118317U
Authority
JP
Japan
Prior art keywords
circuit
automatic gain
gain control
output
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP931283U
Other languages
Japanese (ja)
Inventor
加藤 伊智朗
Original Assignee
日本無線株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本無線株式会社 filed Critical 日本無線株式会社
Priority to JP931283U priority Critical patent/JPS59118317U/en
Publication of JPS59118317U publication Critical patent/JPS59118317U/en
Pending legal-status Critical Current

Links

Landscapes

  • Control Of Amplification And Gain Control (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図面は本考案の一実施例を示すブロック回路図である。 1・・・受信空中線、2・・・増幅器、3・・・復調器
、4・・・標本化回路、5・・・量子化回路、6・・・
判定回路、7・・・AGC電圧発生回路。
The drawing is a block circuit diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Receiving antenna, 2... Amplifier, 3... Demodulator, 4... Sampling circuit, 5... Quantization circuit, 6...
Judgment circuit, 7... AGC voltage generation circuit.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)受信機の復調出力を一定時間間隔で標本化する回
路と、該標本化回路の出力を所定のスレッショルドレベ
ルにて2値信号に量子化する回路と、該量子化回路の出
力が所定値範囲にあるか否かの判定を行う判定回路と、
該判定回路からのAGC制御電圧信号に応じて増幅器の
増幅度を制御するためのAGC電圧を発生するAGC電
圧発生回路とを備え、前記復調出力をディジタル信号に
変換したディジタル信号を利用して前記増幅器の増幅度
を制御することを特徴とする受信機の自動利得制御回路
(1) A circuit that samples the demodulated output of the receiver at regular time intervals, a circuit that quantizes the output of the sampling circuit into a binary signal at a predetermined threshold level, and a circuit that samples the output of the quantization circuit at a predetermined threshold level. a determination circuit that determines whether the value is within the value range;
and an AGC voltage generation circuit that generates an AGC voltage for controlling the amplification degree of the amplifier according to the AGC control voltage signal from the determination circuit, and uses a digital signal obtained by converting the demodulated output into a digital signal to generate the An automatic gain control circuit for a receiver, characterized by controlling the amplification degree of an amplifier.
(2)実用新案登録請求の範囲第1項の回路において、
前記判定回路において判定する2値信号の数を変更する
ことによって容易に時定数の変更が可能であることを特
徴とする自動利得制御回路。
(2) In the circuit set forth in paragraph 1 of the claims for utility model registration,
An automatic gain control circuit characterized in that the time constant can be easily changed by changing the number of binary signals judged in the judgment circuit.
JP931283U 1983-01-26 1983-01-26 automatic gain control circuit Pending JPS59118317U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP931283U JPS59118317U (en) 1983-01-26 1983-01-26 automatic gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP931283U JPS59118317U (en) 1983-01-26 1983-01-26 automatic gain control circuit

Publications (1)

Publication Number Publication Date
JPS59118317U true JPS59118317U (en) 1984-08-09

Family

ID=30140776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP931283U Pending JPS59118317U (en) 1983-01-26 1983-01-26 automatic gain control circuit

Country Status (1)

Country Link
JP (1) JPS59118317U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5367334A (en) * 1976-11-26 1978-06-15 Sharp Corp High-speed writing type digital automatic gain control circuit and itsdriving system
JPS5532216A (en) * 1978-08-23 1980-03-06 Matsushita Electric Ind Co Ltd Automatic recording level setter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5367334A (en) * 1976-11-26 1978-06-15 Sharp Corp High-speed writing type digital automatic gain control circuit and itsdriving system
JPS5532216A (en) * 1978-08-23 1980-03-06 Matsushita Electric Ind Co Ltd Automatic recording level setter

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