JPS615069U - automatic gain control device - Google Patents
automatic gain control deviceInfo
- Publication number
- JPS615069U JPS615069U JP8786984U JP8786984U JPS615069U JP S615069 U JPS615069 U JP S615069U JP 8786984 U JP8786984 U JP 8786984U JP 8786984 U JP8786984 U JP 8786984U JP S615069 U JPS615069 U JP S615069U
- Authority
- JP
- Japan
- Prior art keywords
- gain control
- signal
- control circuit
- control device
- automatic gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Television Receiver Circuits (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【図面の簡単な説明】
第１図は本考案の自動利得制御装置１が関連して実施さ
れるテレビジョン受信機の構成を示す図、第２図はＡＧ
Ｃ回路７と制御回路９の電気回路図、第３図はＳＥＣＡ
Ｍ方式受信時のトランジスタＱ１〜Ｑ３に関連した入力
出力信号の波形図、第４図はＰＡＬ方式受信時のトラン
ジスタＱ１〜Ｑ３に関連した入出力信号の波形図、第５
図はスイッチＳ３が導通されるときの第４図での入出力
信号の波形図である。
１・・・自動利得制御回路、７，８・・・ＡＧＣ回路、
９・・・制御回路。[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing the configuration of a television receiver that is implemented in conjunction with the automatic gain control device 1 of the present invention, and FIG.
Electrical circuit diagram of C circuit 7 and control circuit 9, Figure 3 is SECA
FIG. 4 is a waveform diagram of input/output signals related to transistors Q1 to Q3 during M system reception, and FIG. 5 is a waveform diagram of input/output signals related to transistors Q1 to Q3 during PAL system reception.
The figure is a waveform diagram of the input/output signals in FIG. 4 when the switch S3 is turned on. 1... Automatic gain control circuit, 7, 8... AGC circuit,
9...Control circuit.
Claims (1)
その検出レベルに対応して前記信号の受信増幅利得を一
定にする複数の各受信信号毎の複数の利得制御回路と、 比較的高い検出レベルを有する前記予め定めた信号に対
応した利得制御回路に関連して設けられ、比較的低い検
出レベルを有する受信信号を受信しているときに−、受
信増幅利得の高くなる信号を導出して、その利得制御回
路を待機状態とする・ 制御回路とを含むことを特徴と
する自動利得制御装置。[Scope of claim for utility model registration] Detecting the level of a predetermined signal included in the received signal,
a plurality of gain control circuits for each of a plurality of received signals that keep the reception amplification gain of the signal constant in accordance with the detection level; and a gain control circuit corresponding to the predetermined signal having a relatively high detection level. A control circuit which is provided in connection with the control circuit and derives a signal that increases the reception amplification gain when receiving a reception signal having a relatively low detection level and puts the gain control circuit in a standby state. An automatic gain control device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8786984U JPS615069U (en) | 1984-06-13 | 1984-06-13 | automatic gain control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8786984U JPS615069U (en) | 1984-06-13 | 1984-06-13 | automatic gain control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS615069U true JPS615069U (en) | 1986-01-13 |
| JPH0413890Y2 JPH0413890Y2 (en) | 1992-03-30 |
Family
ID=30640482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8786984U Granted JPS615069U (en) | 1984-06-13 | 1984-06-13 | automatic gain control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS615069U (en) |
-
1984
- 1984-06-13 JP JP8786984U patent/JPS615069U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0413890Y2 (en) | 1992-03-30 |
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