JPS58189648U - Input level detection circuit - Google Patents

Input level detection circuit

Info

Publication number
JPS58189648U
JPS58189648U JP1982086548U JP8654882U JPS58189648U JP S58189648 U JPS58189648 U JP S58189648U JP 1982086548 U JP1982086548 U JP 1982086548U JP 8654882 U JP8654882 U JP 8654882U JP S58189648 U JPS58189648 U JP S58189648U
Authority
JP
Japan
Prior art keywords
input level
detection circuit
level detection
agc circuit
abstract
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1982086548U
Other languages
Japanese (ja)
Other versions
JPS6238356Y2 (en
Inventor
今野　豪雄
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1982086548U priority Critical patent/JPS58189648U/en
Publication of JPS58189648U publication Critical patent/JPS58189648U/en
Application granted granted Critical
Publication of JPS6238356Y2 publication Critical patent/JPS6238356Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例を示すブロック図である。第
２図および第３図は本考案の一実施例の・　　動作を説
明する図である。FIG. 1 is a block diagram showing an embodiment of the present invention. FIGS. 2 and 3 are diagrams for explaining the operation of an embodiment of the present invention.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＡＧＣ回路を有するＦＭ受信装置において、ＡＧＣ回路
で入力レベル変動の圧縮された信号をレベル検波し、そ
の検波出力を基準電圧と比較しその差分だけを増幅する
直流増幅する入力レベル検出回路。In an FM receiver having an AGC circuit, an input level detection circuit performs DC amplification by level detecting a signal with compressed input level fluctuations in the AGC circuit, comparing the detected output with a reference voltage, and amplifying only the difference.
JP1982086548U 1982-06-10 1982-06-10 Input level detection circuit Granted JPS58189648U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982086548U JPS58189648U (en) 1982-06-10 1982-06-10 Input level detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982086548U JPS58189648U (en) 1982-06-10 1982-06-10 Input level detection circuit

Publications (2)

Publication Number Publication Date
JPS58189648U true JPS58189648U (en) 1983-12-16
JPS6238356Y2 JPS6238356Y2 (en) 1987-09-30

Family

ID=30095342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982086548U Granted JPS58189648U (en) 1982-06-10 1982-06-10 Input level detection circuit

Country Status (1)

Country Link
JP (1) JPS58189648U (en)

Also Published As

Publication number Publication date
JPS6238356Y2 (en) 1987-09-30

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