JPS59117819A - Series resistance type digital-analog converter - Google Patents

Series resistance type digital-analog converter

Info

Publication number
JPS59117819A
JPS59117819A JP22909582A JP22909582A JPS59117819A JP S59117819 A JPS59117819 A JP S59117819A JP 22909582 A JP22909582 A JP 22909582A JP 22909582 A JP22909582 A JP 22909582A JP S59117819 A JPS59117819 A JP S59117819A
Authority
JP
Japan
Prior art keywords
hole
resistance
layer
resistor
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22909582A
Other languages
Japanese (ja)
Inventor
Haruyoshi Takaoka
高岡 晴義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22909582A priority Critical patent/JPS59117819A/en
Publication of JPS59117819A publication Critical patent/JPS59117819A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters

Abstract

PURPOSE:To improve the accuracy of D/A conversion without so much increase in the entire area by widening the area of through-holes at the end of a resistance layer and leaving the area of the through-hole at the middle as it is. CONSTITUTION:A through-hole N5' of the same size as that of a through-hole N5 at the end of the resistance layer 1 is added to the outside of the through- hole N5 so as to bring both through-holes N5, N5' in contact with each other. Then, the parasitic resistance RN5 of this part is reduced to nearly a half in a simple consideration (in terms of the area). The reason why the N5' is provided at the outside of the N5 is that it is not necessary to change the method setting the value of the resistor R4 depending on the interval between the through-holes N4 and N5. Since the area of the through-holes of the end of the resistance layer is widened and the area of the through-hole at the middle is kept unchanged, the accuracy of D/A conversion is improved without giving so much increase in the entire area.

Description

【発明の詳細な説明】 発明の技術分野 本発明は抵抗直列型D/Aコンバータに関し、特にこれ
を集積回路で構成する際のコンタクト抵抗の影響をレイ
アウト面から軽減しようとするものである。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a resistor series type D/A converter, and is particularly directed to reducing the influence of contact resistance when configuring this as an integrated circuit from a layout standpoint.

従来技術と問題点 IC化された抵抗直列型D/Aコンバータでは、複数本
の拡散抵抗又は多結晶シリコン抵抗等を配列し、これら
を直列に接続しかつ多数の中間点から引出し線を導出し
、両端には基準電圧を印加しそしてデジタル入力に応じ
てスイッチをオン・オフして該引出し線を選択し、目的
とした電圧レベル(アナログ値)を抵抗分割により出力
する。第1図は4×3のマトリクスに抵抗を配列したパ
ターン例で、第2図はその等価回路である。第1図にお
いて、1は拡散層(または多結晶シリコン層等)による
抵抗層で、図示しないが拡散抵抗なら半導体基板に不純
物を所定形状にイオン打込み若しくは拡散することによ
り、また多結晶シリコン抵抗なら半導体基板上に絶縁膜
を介して多結晶シリコンを被着しこれをパターニングす
ることにより形成され、表面ば絶縁膜で覆われる。これ
らの拡散層の両端および中間部複数箇所に対応する絶縁
膜にはコンタクト用のスルーホールN 1−N 5を等
間隔で設け、これにより抵抗値の等しい4本の直列抵抗
R1〜R4が構成される。破線で示す4は、スルーホー
ルN1−N3を通して抵抗層1に接続する配線層である
。拡散層2.3についても同様であり、スルーホールを
通して抵抗層に接続する配線層4により、抵抗層3本が
直列に接続されその直列抵抗層から多数の引出し線が導
出された抵抗分圧回路が構成される。即ち直列に接続さ
れ抵抗値が等しい12本の抵抗R1〜RI2は一端で第
1の基準電圧V1に他端で第2の基準電圧■2に接続さ
れ、これらの抵抗層のスルーホールN2〜N15から引
出される配線層4はスイッチ5l−812により選択的
に(デジタル入力に応じて)出力端子OUTに接続され
る。このD/Aコンバータの最大出力はデジタル人力1
100でスイッチS1をオンにしたときに得られ、また
最小出力はデジタル入力0001でスイッチS1゜をオ
ンにしたときに得られる。そして、オンにするスイッチ
を81□1 3111 3101 ・・・・・・の順に
選択することで出力電圧は0より段階的に(1/12ず
つ)11  (Vl−V2)/12まで上昇する。4ビ
ツト2値信号の組合せは16通りであるから、抵抗層を
もう1本増加して4×4マトリクスとすることによりこ
れに対応できる。通常D/Aコンバータには8×8また
は16×8マトリクスつまり64または128ステツプ
の分圧回路が設けられる。
Conventional technology and problems In a resistor series D/A converter integrated with an IC, multiple diffused resistors or polycrystalline silicon resistors are arranged, connected in series, and lead lines are derived from many intermediate points. , a reference voltage is applied to both ends, and the lead line is selected by turning on/off a switch in accordance with the digital input, and a target voltage level (analog value) is outputted by resistor division. FIG. 1 shows an example of a pattern in which resistors are arranged in a 4×3 matrix, and FIG. 2 shows its equivalent circuit. In FIG. 1, 1 is a resistance layer made of a diffusion layer (or a polycrystalline silicon layer, etc.). Although not shown, in the case of a diffusion resistance, impurities are ion-implanted or diffused into a semiconductor substrate in a predetermined shape, and in the case of a polycrystalline silicon resistance, It is formed by depositing polycrystalline silicon on a semiconductor substrate via an insulating film and patterning it, and the surface is covered with the insulating film. Through holes N1-N5 for contacts are provided at equal intervals in the insulating film corresponding to both ends and multiple locations in the middle of these diffusion layers, thereby forming four series resistors R1 to R4 with equal resistance values. be done. 4 indicated by a broken line is a wiring layer connected to the resistance layer 1 through through holes N1-N3. The same applies to the diffusion layer 2.3, and a resistance voltage divider circuit is formed in which three resistance layers are connected in series by a wiring layer 4 connected to the resistance layer through a through hole, and a number of lead lines are led out from the series resistance layer. is configured. That is, 12 resistors R1 to RI2 connected in series and having the same resistance value are connected to the first reference voltage V1 at one end and the second reference voltage 2 at the other end, and are connected to the through holes N2 to N15 in these resistance layers. The wiring layer 4 drawn out from the circuit is selectively connected (depending on the digital input) to the output terminal OUT by a switch 5l-812. The maximum output of this D/A converter is digital human power 1
100 and the switch S1 is turned on, and the minimum output is obtained when the digital input is 0001 and the switch S1 is turned on. Then, by selecting the switches to be turned on in the order of 81□1 3111 3101 . . . , the output voltage increases from 0 step by step (in steps of 1/12) to 11 (Vl-V2)/12. Since there are 16 combinations of 4-bit binary signals, this can be accommodated by adding one more resistance layer to form a 4.times.4 matrix. Typically, a D/A converter is provided with an 8.times.8 or 16.times.8 matrix, or 64 or 128 step voltage divider circuit.

本例はこれを簡単化して示すものである。This example shows this in a simplified manner.

ところで、第1図に示すレイアウトであると、拡散層1
〜3と金属配線層4がコンタクトするスルーホールNl
、N2.・・・・・・部分において、それぞれコンタク
トによる寄生抵抗RNI〜RN15が生じる。このうち
RNI、RN5.RN6.RNIO,RNII、RNI
5は基準電圧v1からV2への電流バスに直列に介在す
るので、この値が大きいと分割電圧が狂い、出力電圧の
誤差原因となる。通常スルーホールNl、N2の寸法は
その間に形成される抵抗R+ + R21・・・・・・
の値を等しくするために均一に設定され、且つ高密度化
のために小面積化される。このため、該寄性抵抗の値が
30Ω程度に達することもあり、この場合に分圧用の抵
抗R1,R2,・・・・・・の値が数100Ω程度と小
さいと(抵抗R1,R2・・・・・・が多数ある場合は
各抵抗の値は小さくなり勝ちで、それでも全体としては
かなり高抵抗となってしまう)、該寄性抵抗の値が無視
できなくなる。
By the way, in the layout shown in FIG.
Through hole Nl where ~3 and metal wiring layer 4 are in contact
, N2. . . . , parasitic resistances RNI to RN15 occur due to the contacts, respectively. Of these, RNI, RN5. RN6. RNIO, RNII, RNI
5 is interposed in series with the current bus from the reference voltage v1 to V2, so if this value is large, the divided voltage will be distorted, causing an error in the output voltage. Normally, the dimensions of through-holes Nl and N2 are the resistance R+ + R21 formed between them.
are set uniformly to make the values equal, and the area is reduced to increase density. For this reason, the value of the parasitic resistance may reach about 30Ω, and in this case, if the value of the voltage dividing resistors R1, R2, etc. is as small as about several hundred Ω (resistances R1, R2, etc.). (If there are a large number of resistors, the value of each resistor will tend to be small, but the overall resistance will still be quite high), and the value of the parasitic resistor cannot be ignored.

発明の目的 本発明は、上記の問題点をレイアウト面から、しかも全
体の面積はさほど増大させることなく改善しようとする
ものである。
OBJECTS OF THE INVENTION The present invention attempts to improve the above-mentioned problems from the layout perspective without significantly increasing the overall area.

発明の構成 本発明は、拡散層または多結晶シリコン層等による抵抗
層を複数本基板上に形成し、各抵抗層を覆う絶縁膜には
該抵抗層と配線層とのコンタクト用のスルーホールをそ
れぞれ複数個設け、該スルーホールを通して配線して複
数本の該抵抗層を全て直列に接続しかつその直列抵抗層
から多数の引出し線を導出して、該直列抵抗層の両端に
加えられる基準電圧を段階的に抵抗分割可能としたD/
Aコンバータにおいて、各抵抗層の端部にあって基準電
圧源または他の抵抗層との接続に使用されるスルーボー
ルは、各抵抗層中間部のスルーホールより大面積化した
ことを特徴とするが、以下図示の実施例を参照しながら
これを詳細に説明する。
Structure of the Invention The present invention comprises forming a plurality of resistance layers such as diffusion layers or polycrystalline silicon layers on a substrate, and forming through holes in an insulating film covering each resistance layer for contact between the resistance layers and wiring layers. A reference voltage is applied to both ends of the series resistance layer by providing a plurality of each, connecting the plurality of resistance layers in series by wiring through the through holes, and leading out a large number of lead wires from the series resistance layer. D/ that allows resistance division in stages
In the A converter, the through ball located at the end of each resistance layer and used for connection with the reference voltage source or other resistance layer is characterized by having a larger area than the through hole in the middle of each resistance layer. However, this will be explained in detail below with reference to the illustrated embodiment.

発明の実施例 第3図(A)(B)は本発明の異なる実施例を示す平面
図で、(A)に示す例は抵抗層端部のスルーホールN5
 (Nl、N6.NIO,Ni1.N15についても同
様)の外側に同寸法のスルーホールN5′を追加し、配
線4を抵抗Nlに両スルーホールN5.N5’を通して
コンタクトさせるようにしたものである。これによりこ
の部分の寄性抵抗RN5は単純に(面積的に)考えて1
/2に低下する。ここでN5’をN5の外側に設けるの
は、抵抗R4の値をスルーホールN4とN5の離間距離
で設定する方法を変更せずに済むためである。同図(B
)に示す例は端部のスルーホールN6 (N’l、N5
.Nl O,Nl 1.Nl 5についても同様)の面
積を同様の理由で外側に拡大したものである。この場合
でもスルーホールN7とN6の離間距離は抵抗R5を形
成する長さに保たれる。
Embodiments of the invention FIGS. 3(A) and 3(B) are plan views showing different embodiments of the present invention. The example shown in FIG.
(Same goes for Nl, N6.NIO, Ni1.N15) A through hole N5' of the same size is added to the outside of Nl, N6.NIO, Ni1.N15, and both through holes N5. Contact is made through N5'. As a result, the parasitic resistance RN5 in this part can be simply considered (in terms of area) as 1
/2. The reason why N5' is provided outside N5 is that it is not necessary to change the method of setting the value of resistor R4 based on the distance between through holes N4 and N5. The same figure (B
) is the through hole N6 (N'l, N5
.. Nl O, Nl 1. The same applies to Nl 5), which is expanded outward for the same reason. Even in this case, the distance between the through holes N7 and N6 is maintained at a length that forms the resistor R5.

なお、この他にコンタクト抵抗値分を抵抗セグメントで
補正する方法も考えられる。つまり、(R++RN1)
=R2=R3= (Ra+RN5)= (R5+RN6
)=・・・・・・−R11−(R1゜+RN15)を成
立させる方法である。しかし、この方法では、コンタク
ト抵抗値が製造上不安定であるため、実施困比な面があ
る。
In addition, another method can be considered in which the contact resistance value is corrected using resistance segments. That is, (R++RN1)
=R2=R3= (Ra+RN5)= (R5+RN6
)=...-R11-(R1°+RN15). However, this method is difficult to implement because the contact resistance value is unstable during manufacturing.

発明の効果 以上述べたように本発明では、抵抗層端部のスルーホー
ルNl、N5.N6等の面積は広げ、中間部のスルーホ
ールN2.N3.等の面積はそのままにしておくので、
全体の面積はさほど増大させずに(各抵抗層を、拡大し
たスルーホールに対応する分だけ長くするので、若干の
面積増大はあるが)D/A変換精度を改善することがで
きる。
Effects of the Invention As described above, in the present invention, the through holes Nl, N5 . The area of N6 etc. is widened and the through hole N2. N3. Since the area of , etc. is left as is,
The D/A conversion accuracy can be improved without significantly increasing the overall area (although there is a slight increase in area since each resistor layer is lengthened to correspond to the enlarged through hole).

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は抵抗直列型D/Aコンバータの一
例を示す平面パターン図および等価回路図、第3図(A
)(B)は本発明の各実施例を示す要部の平面パターン
図である。 図中、1〜3は抵抗層、4は配線層、Nl、N5、・・
・・・・は端部のスルーホール、N2.N3・・・・・
・は中間部のスルーホール、R1,R2・・・・・・は
分圧用抵抗である。 出願人 富士通株式会社 代理人弁理士  青  柳    稔 第1図 ■1 一 第2図
Figures 1 and 2 are a planar pattern diagram and an equivalent circuit diagram showing an example of a resistor series type D/A converter, and Figure 3 (A
)(B) is a plan pattern diagram of a main part showing each embodiment of the present invention. In the figure, 1 to 3 are resistance layers, 4 is a wiring layer, Nl, N5,...
... is a through hole at the end, N2. N3...
. is a through hole in the middle, and R1, R2, . . . are voltage dividing resistors. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi Figure 1 ■1 - Figure 2

Claims (1)

【特許請求の範囲】 (11拡散層または多結晶シリコン層等による抵抗層を
複数本基板上に形成し、各抵抗層を覆う絶縁膜には該抵
抗層と配線層とのコンタクト用のスルーホールをそれぞ
れ複数個設け、該スルーホールを通して配線して複数本
の該抵抗層を全て直列に接続しかつその直列抵抗層から
多数の引出し線を導出し−て、該直列抵抗層の両端に加
えられる基準電圧を段階的に抵抗分割可能としたD/A
コンバータにおいて、各抵抗層の端部にあって基準電圧
源または他の抵抗層との接続に使用されるスルーホール
は、各抵抗層中間部のスルーホールより大面積化したこ
とを特徴とする抵抗直列型D/Aコンバータ。 (2)抵抗層端部が延長され、その端部および延長部に
大面積化したスルーホールが設けられることを特徴とす
る特許請求の範囲第1項記載の抵抗直列型D/Aコンバ
ーク。
[Claims] (11) A plurality of resistance layers such as diffusion layers or polycrystalline silicon layers are formed on a substrate, and an insulating film covering each resistance layer has a through hole for contacting the resistance layer and a wiring layer. A plurality of resistor layers are connected in series by wiring through the through holes, and a large number of lead wires are led out from the series resistor layer and are added to both ends of the series resistor layer. D/A that enables step-by-step resistance division of reference voltage
A resistor characterized in that in a converter, a through hole at the end of each resistor layer used for connection with a reference voltage source or another resistor layer has a larger area than a through hole in the middle of each resistor layer. Series type D/A converter. (2) The resistor series type D/A converter according to claim 1, wherein the end portion of the resistive layer is extended, and a through hole with a large area is provided at the end portion and the extended portion.
JP22909582A 1982-12-24 1982-12-24 Series resistance type digital-analog converter Pending JPS59117819A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22909582A JPS59117819A (en) 1982-12-24 1982-12-24 Series resistance type digital-analog converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22909582A JPS59117819A (en) 1982-12-24 1982-12-24 Series resistance type digital-analog converter

Publications (1)

Publication Number Publication Date
JPS59117819A true JPS59117819A (en) 1984-07-07

Family

ID=16886671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22909582A Pending JPS59117819A (en) 1982-12-24 1982-12-24 Series resistance type digital-analog converter

Country Status (1)

Country Link
JP (1) JPS59117819A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5613829A (en) * 1979-07-13 1981-02-10 Nec Corp Voltage dividing circuit
JPS56166629A (en) * 1980-05-28 1981-12-21 Matsushita Electric Ind Co Ltd Resistance network and digital-to-analog converter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5613829A (en) * 1979-07-13 1981-02-10 Nec Corp Voltage dividing circuit
JPS56166629A (en) * 1980-05-28 1981-12-21 Matsushita Electric Ind Co Ltd Resistance network and digital-to-analog converter

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