WO1989004553A1 - Semiconductor devices with programmable passive-component layer and process for producing the same - Google Patents

Semiconductor devices with programmable passive-component layer and process for producing the same Download PDF

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Publication number
WO1989004553A1
WO1989004553A1 PCT/GB1988/000995 GB8800995W WO8904553A1 WO 1989004553 A1 WO1989004553 A1 WO 1989004553A1 GB 8800995 W GB8800995 W GB 8800995W WO 8904553 A1 WO8904553 A1 WO 8904553A1
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WO
WIPO (PCT)
Prior art keywords
layer
passive components
polysilicon
semiconductor device
active devices
Prior art date
Application number
PCT/GB1988/000995
Other languages
French (fr)
Inventor
Peter Fred Blomley
Original Assignee
Lsi Logic Europe Plc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Europe Plc filed Critical Lsi Logic Europe Plc
Priority to GB8915545A priority Critical patent/GB2219436A/en
Publication of WO1989004553A1 publication Critical patent/WO1989004553A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11801—Masterslice integrated circuits using bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to semiconductor devices which include- a programmable passive-component layer, and is also concerned with a process for producing such devices. Included within the scope of the invention are both integrated circuit (IC) arrays and also semiconductor wafers processed to a stage where they incorporate the programmable passive-component layer.
  • IC integrated circuit
  • the invention is relevant both to analogue arrays and to analogue/digital arrays.
  • the present invention arises from a consideration of how best to produce application specific system ICs (ASSICs).
  • ASSICs application specific system ICs
  • the turnaround from "sign off" to end of batch and supply of parts is usually about two to three weeks, and could be as little as one week.
  • the average total processing time of all layers in an IC would be in the range of twelve to sixteen weeks.
  • this is the metal layers with the vias (metal to metal contacts) and in some cases with the inclusion of the contacts to the silicon as well.
  • the active devices e.g. bipolar or CMOS, are fixed in terms of their integer values as programmed b the metal layers.
  • the programming of the passive component layer or layers is achieved by again using the metal layers, connecting resistors either in parallel or series or in a combination of both, in order to make up the required values.
  • the problem with such techniques is that the range of passive component values is fixed absolutely and one has to have a very high degree of redundancy in order to be able to create a useful range of component values. This is extremely wasteful and does not necessarily guarantee that one can create the particular component values which one needs for the customer's requirements.
  • the key problem with any analogue design is the massive range of passive components which are required. In most cases these are a wide range of matched resistors with some small capacitors.
  • a polysilicon layer is used for the gates of the CMOS devices and for the emitters of the bipolar devices. It is a primary object of the present invention to use a layer of material which has a substantially linear resistance characteristic as a programmable passive-component layer.
  • the material may be polysilicon or chrome disilicide for example.
  • this polysilicon material for example would not be considered as a programmable- resistance because * the polysilicon layer usually only occurs in CMOS technology and, because its resistance is relatively low (50ohms per square), it would be incompatible with CMOS linear designs.
  • these materials are extremely useful and appropriate.
  • a semiconductor wafer which incorporates a layer of material which has a substantially linear resistance characteristic and which is arranged to be programmed with passive components.
  • an IC array, analogue or analogue/digital which comprises a layer of material which has a substantially linear resistance characteristic and which is programmed with passive components.
  • the material of the layer is preferably polysilicon or chrome disilicide.
  • a process for the manufacture of semiconductor wafers or IC arrays which comprises the steps of: a) effecting a first, etching step to define at least part of active devices; b) depositing a layer of material having a substantially linear resistance characteristic; and, c) patterning desired passive components on said 4 laye _
  • the patterning of the passive components is effected by a second etching step following the first etching step which defines the 5 active components.
  • At least one metal definition stage follows the patterning of the passive components.
  • Fig. shows part of a BiCMOS analogue array to illustrate how the programmable passive component area 35 is integrated into the array;
  • Fig. 2 illustrates the sequence of process steps in the creation of an IC array in accordance with the invention
  • Fig. 3 shows one alternative analogue array
  • Fig. 4 shows a further alternative analogue array
  • Fig. 5 shows a total system layout in .accordance with the invention.
  • bipolar devices are indicated at B
  • P-channel MOS transistors are indicated at P
  • N-channel MOS transistors are indicated at N
  • resistors are indicated at R
  • capacitors are indicated at C.
  • Fig. 1 shows a typical analogue array.
  • the area in which the passive components, here shown as resistors R and capacitors C, are created or patterned is indicated generally by the cross-hatched area 10 which encompasses the active components B,P,N. Power rails are indicated at -Vg, +Vs, 0, +Vs and -Vs.
  • the centre group 12 of active devices P,B may define basic amplifier blocks.
  • the group 14 of active devices N,P shown at the right-hand side of Fig.1 may define logic gates, as required.
  • Each active device is shown as having a width dimension of 24 micron.
  • the active device spacing is based on a grid of 6 micron pitch.
  • Fig. 2 illustrates the sequence of manufacturing steps involved in the creation of a wafer or IC array of the present invention.
  • the initial, conventional BiCMOS process steps, indicated generally at 16, are first carried out using masks, for example 12 masks.
  • One step in this process, as indicated in Fig. 2 is a first etch stage 18 carried out on a polysilicon layer in order to define the gates of the CMOS devices and the bipolar emitters, i.e. active devices.
  • the wafers undergo ion implantation, etc. as indicated at 20. This includes the CMOS source/drain implants.
  • a layer of material having a substantially linear resistance characteristic in this embodiment referred to as polysilicon by way of example, is deposited, as step 22, in the area or areas designated for the passive components of the array.
  • polysilicon a layer of material having a substantially linear resistance characteristic
  • the polysilicon layer is deposited on top of the silicon surface.
  • CMOS gates and bipolar emitters, as well as the presently unconfigured passive component area are covered by a photoresist coating and * using a mask, the polysilicon area is etched to create the desired passive components from the predefined areas. These predefined areas, such as that indicated at 10 in Fig. 1, do not have active devices within them.
  • This second etch stage configures the passive component area or areas 10. This technique allows an array to be constructed which, for the first time, allows the customer to define his own passive component values on an analogue design array.
  • Polysilicon resistors can also be used for creating' the metal routing channels.
  • chrome disilicide is an alternative material which can be used. Indeed, the
  • 25 scope of the invention includes any material which has a linear or substantially linear resistance . characteristic and which is compatible with the other manufacturing process steps.
  • Figs. 3 and 4 show two alternatives to the layout
  • the choice of topology mainly depends on the required ratio between the active B,P and N devices and the total value of the resistors R arid/or capacitors.
  • the active devices B,P,N are logic gates and the passive
  • Fig. 5 shows an arrangement for a total IC array comprising digital and analogue sections.
  • the digital section 34 is a compacted array of standard cells which are metal programmable and the analogue section 36 may be composed as described above.
  • a test logic area 38' is provided therebetween.
  • a ratio of approximately 4 to 1 is presently preferred for the ratio between the areas of .the * digital and ' analogue sections 34,36 respectively.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A semiconductor wafer or IC array, either analogue or analogue/digital, includes a layer of material which has a substantially linear resistance characteristic and which can be programmed with passive components, i.e. resistors (R) and capacitors (C). The material is preferably polysilicon or chrome disilicide. The passive components (R, C) are configured within the area (10) surrounding active devices (B, P, N) such as CMOS devices and bipolar devices. The process for producing the desired configuration of passive components may include etching of the layer of material.

Description

SEMICONDUCTOR DEVICES WITH PROGRAMMABLE PASSIVE- COMPONENT LAYER AND PROCESS FOR PRODUCING THE SAME
This invention relates to semiconductor devices which include- a programmable passive-component layer, and is also concerned with a process for producing such devices. Included within the scope of the invention are both integrated circuit (IC) arrays and also semiconductor wafers processed to a stage where they incorporate the programmable passive-component layer. The invention is relevant both to analogue arrays and to analogue/digital arrays.
The present invention arises from a consideration of how best to produce application specific system ICs (ASSICs). In the ASSIC field, the all important factor is time. The turnaround from "sign off" to end of batch and supply of parts is usually about two to three weeks, and could be as little as one week. Against this background, the average total processing time of all layers in an IC would be in the range of twelve to sixteen weeks. Hence, in order to be able to process designs quickly, only a part of the process is programmed with the needs of the customer. Normally, this is the metal layers with the vias (metal to metal contacts) and in some cases with the inclusion of the contacts to the silicon as well.
For some time, it has been the object of the manufacturers of ASSICs to integrate systems on a chip, and this has been achieved for digital devices which only need metal connections programmed to the customer's needs. It is an object of the present invention to move forward to the far more demanding analogue domain. This includes the total integration of advanced analogue functions with the complex digital functions. It has been thought in the past that this "system integration" could be created by using a wide range of "all mask layer" cells, each programmed to the specific customer's requirements. However, this approach has a number of drawbacks, primarily because of the customised nature of the' approach.
It is an object of the invention to provide an extremely flexible, approach so that a customer is able to programme the required values oh the semiconductor devices, e.g. the array, itself. In the majority of cases this "need to programme" can be confined to just the passive components, e.g. resistors and capacitors. The active devices, e.g. bipolar or CMOS, are fixed in terms of their integer values as programmed b the metal layers. In the existing techniques, the programming of the passive component layer or layers is achieved by again using the metal layers, connecting resistors either in parallel or series or in a combination of both, in order to make up the required values. However, the problem with such techniques is that the range of passive component values is fixed absolutely and one has to have a very high degree of redundancy in order to be able to create a useful range of component values. This is extremely wasteful and does not necessarily guarantee that one can create the particular component values which one needs for the customer's requirements. The key problem with any analogue design is the massive range of passive components which are required. In most cases these are a wide range of matched resistors with some small capacitors.
In our established BiCMOS process, as part of the process sequence, a polysilicon layer is used for the gates of the CMOS devices and for the emitters of the bipolar devices. It is a primary object of the present invention to use a layer of material which has a substantially linear resistance characteristic as a programmable passive-component layer. The material may be polysilicon or chrome disilicide for example. Normally, this polysilicon material for example would not be considered as a programmable- resistance because* the polysilicon layer usually only occurs in CMOS technology and, because its resistance is relatively low (50ohms per square), it would be incompatible with CMOS linear designs. However, with the advent of bipolar devices and fine line photolithography (1.5 microns) these materials are extremely useful and appropriate.
In accordance with one aspect of the present invention there is provided a semiconductor wafer which incorporates a layer of material which has a substantially linear resistance characteristic and which is arranged to be programmed with passive components.
In accordance with another aspect of the present invention there is provided an IC array, analogue or analogue/digital, which comprises a layer of material which has a substantially linear resistance characteristic and which is programmed with passive components. The material of the layer is preferably polysilicon or chrome disilicide.
Also in accordance with the invention there is provided a process for the manufacture of semiconductor wafers or IC arrays, which comprises the steps of: a) effecting a first, etching step to define at least part of active devices; b) depositing a layer of material having a substantially linear resistance characteristic; and, c) patterning desired passive components on said 4 laye _
Preferably, the patterning of the passive components is effected by a second etching step following the first etching step which defines the 5 active components.
Preferab-ly, at least one metal definition stage follows the patterning of the passive components.
A major advantage of the present invention is the efficiency with which resistors and capacitors can be
10 defined, i.e. configured, and implemented without a major impact on either performance or die size. The present invention is particularly appropriate for use
.- with the BiCMOS process, but is not limited thereto.
It is possible to carry put the patterning of the
15 area to be configured with the passive components by using one of the fields of a (X1 ) low cost mask. This is possible even when the base technology is at the 0.8 micron process feature level. By carrying out this
• patterning step at a relatively late stage in the
20 BiCMOS process substantial advantages are achieved.
For example, one achieves a dramatic improvement in cost, as only one extra layer is used over standard metal programmable arrays. Also, a turn-round time of one week should be possible. This is the first time
25 that analogue designers have been offered this combination of advantages, and is the key to the creation of a wide range of standard cells which can be held as topology maps in a CAD system.
In order that the invention may be fully 30 understood, a more detailed description of the invention will now be given by way of example and with reference to the accompanying drawings, in which:
Fig. shows part of a BiCMOS analogue array to illustrate how the programmable passive component area 35 is integrated into the array; Fig. 2 illustrates the sequence of process steps in the creation of an IC array in accordance with the invention;
Fig. 3 shows one alternative analogue array; Fig. 4 shows a further alternative analogue array; and,
Fig. 5 shows a total system layout in .accordance with the invention.
The following description is given with reference to the BiCMOS process, although it is emphasised that the present invention can be utilised with and incorporated into other manufacturing processes. In the drawings bipolar devices are indicated at B, P-channel MOS transistors are indicated at P, N-channel MOS transistors are indicated at N, resistors are indicated at R, and capacitors are indicated at C.
Fig. 1 shows a typical analogue array. The area in which the passive components, here shown as resistors R and capacitors C, are created or patterned is indicated generally by the cross-hatched area 10 which encompasses the active components B,P,N. Power rails are indicated at -Vg, +Vs, 0, +Vs and -Vs. The centre group 12 of active devices P,B may define basic amplifier blocks. The group 14 of active devices N,P shown at the right-hand side of Fig.1 may define logic gates, as required. Each active device is shown as having a width dimension of 24 micron. The active device spacing is based on a grid of 6 micron pitch.
Fig. 2 illustrates the sequence of manufacturing steps involved in the creation of a wafer or IC array of the present invention. The initial, conventional BiCMOS process steps, indicated generally at 16, are first carried out using masks, for example 12 masks. One step in this process, as indicated in Fig. 2, is a first etch stage 18 carried out on a polysilicon layer in order to define the gates of the CMOS devices and the bipolar emitters, i.e. active devices. Next, the wafers undergo ion implantation, etc. as indicated at 20. This includes the CMOS source/drain implants. Then, a layer of material having a substantially linear resistance characteristic, in this embodiment referred to as polysilicon by way of example, is deposited, as step 22, in the area or areas designated for the passive components of the array. One of the key points is that the polysilicon layer is deposited on top of the silicon surface. Thus, the position of this layer
22 in the process sequence is nearly ideal for customer programming. The wafers which are thus created can
* then be stacked and stored, as indicated at 24, awaiting further processing in accordance with particular customers needs. Then, when the customer indicates the particular passive components and passive component values which are required, the wafers are further processed. This is here shown as including a second etch stage 26. The defined CMOS gates and bipolar emitters, as well as the presently unconfigured passive component area, are covered by a photoresist coating and* using a mask,, the polysilicon area is etched to create the desired passive components from the predefined areas. These predefined areas, such as that indicated at 10 in Fig. 1, do not have active devices within them. This second etch stage configures the passive component area or areas 10. This technique allows an array to be constructed which, for the first time, allows the customer to define his own passive component values on an analogue design array.
After this second etch stage 26 there is a conformal coating of BPSG (boron phosphorus silicon glass) and final RTA (rapid transient anneal), indicated at 28. The passive components can then be connected using standard metal interconnects. This is shown in Fig. 2 as 3 mask stages, involving two metal layers and the creation of vias, indicated as a whole at 30. These processing stages which follow the second 5 etch are extremely easy and quick. As indicated above, wafers, preprocessed and just' awaiting resistor and capacitor configuration and metal interconnect* definition, can be stored as an intermediate step, after the basic BiCMOS process, awaiting customers
10 needs. This gives the further advantage that the wafers -can be tested at this stage, when stored, thus
■ ensuring that they are satisfactory before being programmed. The technique of the present invention allows fully programmable resistor and capacitor values
•15 to be available to the customer and gives a substantial advantage in that' the approach adopted for advanced analogue arrays can now be nearly identical to that adopted for logic arrays. Using this approach, a true "sea of elements" with full auto-routing capability is
20 produced. Polysilicon resistors can also be used for creating' the metal routing channels.
Although polysilicon has been referred to above as the material deposited at step 22, chrome disilicide is an alternative material which can be used. Indeed, the
25 scope of the invention includes any material which has a linear or substantially linear resistance . characteristic and which is compatible with the other manufacturing process steps.
Figs. 3 and 4 show two alternatives to the layout
30 of the analogue array shown, in Fig. 1. The choice of topology mainly depends on the required ratio between the active B,P and N devices and the total value of the resistors R arid/or capacitors. In Fig. 4 the active devices B,P,N are logic gates and the passive
35 components 32 are quad devices. Fig. 5 shows an arrangement for a total IC array comprising digital and analogue sections. The digital section 34 is a compacted array of standard cells which are metal programmable and the analogue section 36 may be composed as described above. A test logic area 38' is provided therebetween. A ratio of approximately 4 to 1 is presently preferred for the ratio between the areas of .the* digital and' analogue sections 34,36 respectively.

Claims

CLAIMS :
1. A semiconductor wafer which incorporates a layer of material which has a substantially linear resistance characteristic and which is arranged to be programmed with passive components.
2. An integrated circuit array which incorporates a layer. of material which has a substantially linear resistance 'characteristic and which is programmed with passive components.
3. A semiconductor device as claimed in claim 1 or 2, in which the material is polysilicon.
4. A semiconductor device as claimed in claim 1 or * 2 , in which the material is chrome disilicide.
5. A semiconductor device as claimed in any preceding claim, in which the passive components are produced by etching said material layer.
6. A semiconductor device as claimed in any preceding claim, in which the passive components are positioned between areas of active devices.
7. A semiconductor device as claimed in any preceding claim, which comprises a plurality of active devices including CMOS devices and/or bipolar devices, and a layer of polysilicon etched to define gates of said active devices, with said layer of programmable material deposited on the underlying silicon surface.
8..An integrated circuit array as claimed in claim 7, which includes, on top of the layer programmed with passive components, a conformal coating of boron phosphorus silicon glass and at least one metal layer for metal interconnects.
9. A process for the manufacture of semiconductor wafers or IC arrays, which comprises the steps of; a) effecting a first, etching step to define at least part of active devices; b) depositing a layer of material having a substantially linear resistance characteristic; and c) patterning desired passive components on said layer.
10. A process as claimed in claim 9, in which the patterning of the passive components is effected by a second etching step.
11. A process as claimed in claim 10, in which said second etching step is carried out, using a mask, after covering" the unconfigured passive component area with a photoresist coating.
12. A process as claimed in claim 9, 10 or 11, which includes at least one metal definition stage following the patterning of the passive components.
13. A process as claimed in any of claims 9 to 12, in which the material of the programmable layer is polysilicon or chrome disilicide.
14. A process as claimed in any of claims 9 to 13, in which said first etching step is effected on a layer of polysilicon to define gates of said active devices.
15. A process as claimed in claim 14, which includes depositing the programmable layer of material directlv on said first polysilicon layer.
PCT/GB1988/000995 1987-11-11 1988-11-11 Semiconductor devices with programmable passive-component layer and process for producing the same WO1989004553A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8915545A GB2219436A (en) 1987-11-11 1988-11-11 Semiconductor devices with programmable passive-component layer and process for producing the same

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GB8726366 1987-11-11
GB8726366A GB8726366D0 (en) 1987-11-11 1987-11-11 Ic array

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JP (1) JPH02502054A (en)
AU (1) AU2626388A (en)
GB (2) GB8726366D0 (en)
WO (1) WO1989004553A1 (en)

Cited By (3)

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Publication number Priority date Publication date Assignee Title
EP0382415A2 (en) * 1989-02-09 1990-08-16 Sony Corporation Semiconductor integrated circuit devices
EP0537782A1 (en) * 1991-10-18 1993-04-21 Nec Corporation Semicustom-made integrated circuit device with resistors over transistor array
US5631492A (en) * 1994-01-21 1997-05-20 Motorola Standard cell having a capacitor and a power supply capacitor for reducing noise and method of formation

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JPS60124015A (en) * 1983-12-08 1985-07-02 Seiko Epson Corp Magnetic head
DE3634850A1 (en) * 1985-10-15 1987-04-23 Mitsubishi Electric Corp Method of producing a VLSI semiconductor circuit device of the standard wafer type
JPH0666446A (en) * 1992-08-19 1994-03-08 Matsushita Electric Ind Co Ltd Personal space temperature environment conditioner

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JPS60124015A (en) * 1983-12-08 1985-07-02 Seiko Epson Corp Magnetic head
DE3634850A1 (en) * 1985-10-15 1987-04-23 Mitsubishi Electric Corp Method of producing a VLSI semiconductor circuit device of the standard wafer type
JPH0666446A (en) * 1992-08-19 1994-03-08 Matsushita Electric Ind Co Ltd Personal space temperature environment conditioner

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Title
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Patent Abstracts of Japan, volume 10, no. 99 (E-396)(2156), 16 April 1986, & JP-A-601240154 (SUMITOMO DENKI KOGYO K.K.) 29. November 1985 *
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0382415A2 (en) * 1989-02-09 1990-08-16 Sony Corporation Semiconductor integrated circuit devices
EP0382415A3 (en) * 1989-02-09 1991-04-10 Sony Corporation Semiconductor integrated circuit devices
US5101258A (en) * 1989-02-09 1992-03-31 Sony Corporation Semiconductor integrated circuit device of master slice approach
EP0537782A1 (en) * 1991-10-18 1993-04-21 Nec Corporation Semicustom-made integrated circuit device with resistors over transistor array
US5631492A (en) * 1994-01-21 1997-05-20 Motorola Standard cell having a capacitor and a power supply capacitor for reducing noise and method of formation

Also Published As

Publication number Publication date
EP0349605A1 (en) 1990-01-10
AU2626388A (en) 1989-06-01
GB2219436A (en) 1989-12-06
JPH02502054A (en) 1990-07-05
GB8726366D0 (en) 1987-12-16
GB8915545D0 (en) 1989-08-23

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