JPS59116804A - Shift register of sequence controller - Google Patents

Abstract

PURPOSE:To input bits of a shift register newly from an optional bit and to shift them by inputting the respective bits selectively and giving the bits priority. CONSTITUTION:When a signal 1 is inputted to a clock pulse input line ICL and a serial data input line to select the 1st bit by address lines A0-An, a latch circuit 31 latches the current signal contents of a data line ID1. At the same time, a pulse line ICLK1 is connected to an OR gate 72, so whose OR result is ''1'' and a one-bit latch circuit 32 stores the contents of a data input terminal D. Consequently, the contents are logic ''0'' because no signal is inputted to one input terminal ICLK2 of the gate 52, whose OR result of the gate 52 is ''0'' without reference to the contents of a data line ID2. The OR gate 62, therefore, depends upon the OR result of an OR gate 42. The OR gate 42 is forced by a resistance 92 to output ''1'' because no signal is inputted, and its OR result depends upon the input to the other terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a shift register function of a grain sequence controller, and particularly relates to a shift register capable of shifting contents after an intermediate bit.

[Prior art]

A general sequence controller has various logical operation functions, and a shift register operation function is one of its representative functions.

As input methods for this type of shift register, (1) a serial input method, and (2) a serial parallel input method have been put into practical use.

For example, FIG. 1 shows an example of (1), two paper boxes, and an example of (2), which is a general configuration of a shift register.

By the way, in the sequence control, depending on the content of the logical operation, it may be desired to hold the contents up to the middle of the shift register and shift the contents from 1 to 1+-U.

For example, in the comparison line shown in Figure 4, two types of parts "A" and "B" are processed continuously (b sauce, m king) and parts are added in the next process (spare part 1A" or "B"). The necessity is checked, and if the parts IA""Bl are to be distributed, the control VC is used to determine the value of the information corresponding to the parts on the competition line that can be stored in the shift register ζ method (1) above. In this case, the input part ≠; there is only one place, and it is not possible to change or shift the bits in the middle.In addition, in the method (2) above, although there are many input parts, the same one @ is input in parallel, so the contents of all bits cannot be changed. !1 Izf and it is not possible to retain the contents up to the middle. (This is also the same in (1)) Furthermore, serial/parallel switching must be performed, which is inconvenient. If it is a line, it becomes a complex sequence circuit or program.

As described above, the conventional shift register has a major drawback when it cannot shift the data with new data while retaining the contents up to the middle.

[Object of the Invention] It is an object of the present invention to overcome the above-mentioned drawbacks and to provide a sequence controller that can input a new value from a designated bit of a shift register and perform a shift operation.

[Summary of the invention]

In the present invention, each bit in the shift register has three
・The feature is that a selection circuit is provided to enable selective input, and a priority logic circuit is provided to allow each bit to perform a priority function.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 3, 4, and 5.

FIG. 3 shows the entire circuit configuration of the shift register according to the present invention, with data input switches 31 to 3 respectively.

It is a type of 1-bit sotraz hand circuit that has a clock (shift) pulse input terminal CLK, a clip input terminal CLR, and an output terminal Q, and is a two-man power AND of 42 to 4n and 52 to 5n.
(logical product) game), 62~6n, 72~7n182~8
1-9nl is connected to each circuit with a resistor.

Each wire is connected to the selection circuits 101 to 103 configured with a semiconductor switch 4-''r, as shown in the figure.
4. Clock input line ICLK from the serial data input line connected to the external control circuit that is not connected.

Address l1jlAo~ for the signal of clear human-powered ball CLH
It is configured to be selectively connected depending on the contents of An.

The operation of the shift register 3 constructed of n bits will now be described.

First, signal 111 is input to CLR 1 human power lineman,
At this time, if we consider the case where the first bits of address lines AO to An are all selected, (l" 1 "
v'I; (Hereinafter, each input line that is not input and each line that is not selected is defined as logic 10m.) The memory contents up to f'L of the 1-bit latch circuit 31 are cleared (logic 101), The output terminal Q has cleared contents.

At the same time, since the clear kneaded ball 0LRI is connected to the OR gate 82, the logical sum result is 111, so the contents of the 1-bit latch circuit 32 are cleared, and the output terminal Q
2 is the cleared content. Furthermore, the logical sum result of the OR gate 82 also clears the fixed 1-bit radius 4-33 connected to the OR gate 83 at the next stage. Similarly, all of the 1-bit bits 4- up to 3n bits in the latter stage are cleared.

Next, the clock pulse input kneaded ball CLK and the +)-r
Signal 111≠2 is input to the data input line and the address line A
Considering the case where the first bit≠ is selected by O to An, the latch circuit 31 will latch the signal content of 1 (logic 111) from the serial data line at this time! - (memorize), at the same time clock pulse kneaded ball 0LKI is OR gate 72
Since the logic result of the gate is 111, the 1-bit latch circuit 32 stores the contents of the data input terminal.

Now, the contents of the data input terminal at this time are as follows.

First, since no signal is input to one end of the AND gate 52, ICLK2, the logic becomes 101 and the AND gate 5
The logical result of 2 is 101 regardless of the contents of serial data linework D2.

Therefore, it depends on the rational results of the OR gate 62H and the OR gate 42. Therefore, considering the OR gate 42, one end of the input is connected to the serial data line XD2, but since no signal is input, the resistor 92VC,
1' is forced to the logic 11'', and the logic result depends on the input at the other end (the output Ql of the 1-bit controller 31).

In other words, the data input terminal DfC of 1 bit bit 4-32
1d 1 hit 9 tsu 4-31.47) Output signal "O"
"1 Bi Sotra Two I-31.1-t Game Input III
At this time, because ≠ 2 sets bottom time ≠ f is necessary,
The total output Q1 is 101) or 2 manpower.

Next, when the set lower time t: has passed, the output terminal Q.

In the example 111, Ql and 101 are output.

Thereafter, a shift operation is performed in which the storage contents from the previous stage of the 1-bit rats 4-33 to 3nij are stored fi in a similar manner.

In the above description, the serial data input and the signal from m are performed using the logic 111, but the logic 101 also operates on the same principle.

Now, next is the clock pulse line IC! Signal “1” to LK
A: 3rd bit ≠ input by address lines AO to An
Considering the case where 2 is selected, the following will occur.

First, clock pulse line ]: OLK, 3 is selected, and γ
In this case, the logic 1 is connected to the gate 53.
11'''r, and the AND result of the gate 53 depends on the content of the signal 3 from the serial data line. Therefore, if the input signal is logic 111, the output of the gate 53 is 11.
1"r' is input to one input terminal of the OR gate 63. Therefore, the OR gate 63 has 6 input terminals regardless of the other input terminal.
11 is output, and 1 bit is input to the data input terminal of 4-33. Conversely, if the signal from the serial data input line is logic "o", the AND gate 53's AND result is 1. '□ I, and the OR gate 63 is influenced by the output Y of the other input terminal (tend gate 43, but in this case, the signal 3 from the serial 1 data line is logic IO1, so the logical result of the AND gate 43 is 101.7. In other words, it has no relation to the output signal of the 1-bit latch 32 at the previous stage.

Well, clock pulse kneaded ball CLK3, or gate 73
The output of the gate 73 becomes logic 111 and becomes the data input terminal D (7').
Write down the signal contents.

By the way, the other input terminal of the off gate 73 is connected to the output terminal of the OR gate 72 at the previous stage, but since no signal is input thereto, the logic becomes 10@ and is unrelated.

Next, the operations of each section connected to the subsequent stage are performed in the same manner as the operations described above, and the contents stored in the 1-pin software are shifted to the subsequent stage.

However, 1 Bit Rats 4, which is earlier than 1 Bit Rats 4-33,
-31 to 32 signal inputs ≠: Not affected at all because there are none ≠: Since there are no signals, the stored contents are retained.

Next, when the signal 111 is input to the clear input line 10LR and the third bit is selected by the addresses 4Ao to An, it is connected to one end of the OR gate 83.

Since the output of the gate 83 becomes 111, the memory contents of the 1-bit trigger 33 are cleared.Furthermore, the output of the gate 83 is connected to the off gate 84 at the subsequent stage, so the 1-bit latch is set to 111. , and the subsequent 1-bit bit IN is cleared. However, since no signal is input to each of the 1-bit bits 4-31 to 32Il- in the previous stage, they are not cleared, and are therefore held in their stored contents.

As described above, it is possible to input to any bit of a shift register composed of multiple bits, and it is also possible to retain the input contents of the previous stage bit, and to give priority to all inputs to the previous stage bit. If a shift operation is performed, the value is T.

Therefore, the great invention was explained in the 4th south section above. It can be easily inserted into the control line.

・Furthermore, there is a system aT shown in FIG. 4 that requires the addition of parts, that is, the input of new serial data, but each person can find an application method.

For example, as shown in Fig. 5, when a product is checked at the end of several units, all the products up to that point are likely to be defective.
It can also be used to control processing in subsequent processes.

Also, for other purposes, several clock pulses from the middle,
By inputting the serial data 4, there are many ways to apply it, such as replacing or modifying the pattern from the middle.

〔Effect of the invention〕

According to the present invention, the memory up to any pit in the shift register can be retained and the subsequent bits can be shifted with a new input signal, so the sequence circuit can be easily programmed without complicating it. effective.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional serial input shift register, Figure 2 is a block diagram of a conventional serial/parallel input shift register, and the third factor is a circuit diagram of a serial input shift register according to the great invention. FIG. 5 is a diagram for explaining the present invention. 42-4n, 52-5n: Tend Gate, 62-6! n. 72-7n, 82-8n: first gate, 91-9n: resistor, 101-103: selection circuit.

Claims (1)

[Scope of Claims] 1. In a shift register having serial data input, shift pulse input, and manual clearing, any bit of a multi-bit storage unit that constitutes the shift register retains the memory contents of the previous stage of the arbitrary bit. A shift register for a sequence controller characterized by being equipped with a selection circuit that allows input while the controller is in the position. evening. 2. A shift register for a sequence controller, characterized in that a priority circuit is provided for prioritizing input to the preceding bit.