JPH0461361B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a shift register function of a sequence controller, and particularly to a shift register capable of shifting contents after an intermediate bit.

[Prior art]

A general sequence controller has various logical operation functions, and a shift register operation function is one of the typical functions.

As an input method for this kind of shift register (1) Serial input method (2) Serial/parallel input method have been put into practical use.

For example, FIG. 1 is an example of (1), and FIG. 2 is an example of (2), which is a general configuration of a shift register.

By the way, in a sequence control, depending on the content of the logical operation, it may be desirable to hold the contents up to a bit in the middle of the shift register and shift the contents after that bit.

For example, in a conveyor line as shown in Figure 4, two types of parts "A" and "B" are constantly flowing, processed by a processing machine, and parts are added in the next process (spare parts "A" or "B"). Information corresponding to the parts on the conveyor line can be stored in the shift register in the control that inspects the necessity of the parts and then distributes them into parts "A" and "B". However, in method (1) above, the input section is There is only one location and it is not possible to change or shift the bits in the middle. In addition, in the method (2) above, although there are a large number of input sections, the contents of all bits change because they are input simultaneously in parallel, making it impossible to retain the contents up to the middle. (this is
(1) is also the same) Furthermore, serial/parallel switching must be performed, which is inconvenient. If this is done using a function other than a shift register, it will require multiple sequence circuits and programs.

As described above, the conventional shift register has a major drawback in that it cannot perform a shift operation with new data while retaining the contents up to the middle.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to overcome the above-mentioned drawbacks and provide a sequence controller that can input new contents from any bit of a shift register and perform a shift operation.

[Summary of the invention]

The present invention is characterized in that a selection circuit is provided so that each bit in the shift register can be selectively inputted, and a priority logic circuit is provided to allow each bit to perform a priority function.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 3, 4, and 5.

FIG. 3 shows the circuit configuration of a shift register according to the present invention, and 31 to 3n are data input terminals D, clock (shift) pulse input terminals CLK, and 31 to 3n, respectively.
It is a type of 1-bit latch circuit having a clear input terminal CLR and an output terminal Q.
~5n is a 2-input AND gate, 62~6
72 to 7n, and 82 to 8n are two-input OR (logical sum) gates, and 91 to 9n are resistors connected to the potential V (logic "1"), respectively. Also, ID1
~IDn are serial data lines, ICLK1~ICLKn are clock pulse lines, and ICLR1~ICLRn are clear lines, which are connected to each of the above circuits.

In addition, each of the above lines is connected to selection circuits 101 to 103 made up of semiconductor switches, and a serial data input line ID and a clock input line are connected to an external control circuit (not shown).
ICLK, clear input line ICLR signal to address line
It is configured to be selectively connected depending on the contents of Ao to An.

The operation of the shift register 3 constructed of n bits as described above will be explained next.

First, consider the case where a signal "1" is input to the clear input line ICLR, and at this time the address lines Ao to An select the first bit. Then, the signal "1" is transmitted to the clear line ICLR1, and (no further input is made). (Each input line and each unselected line are defined as logic "0".) The 1-bit latch circuit 31 has its previous stored content cleared (logic "0"), and the output terminal _Q1 becomes the cleared content.

At the same time, since the clear line ICLR1 is connected to the OR gate 82, the logical sum result is "1", so the memory contents of the 1-bit latch circuit 32 are cleared, and the output terminal Q2 becomes the cleared contents. Further, since the logical sum result of the OR gate 82 is connected to the next stage OR gate 83, the 1-bit latch 33 is also cleared. Similarly, the latter
All 1-bit latches up to 3n bits are cleared.

Next, considering the case where the signal "1" is input to the clock pulse input line ICLK and the serial data input line and the first bit is selected by the address lines Ao to An, the latch circuit 31 selects the serial data line ID1 at this time. Latch (memorize) the signal content (logic "1"). At the same time, the clock pulse line ICLK
1 is connected to the OR gate 72, so the logic result of the gate becomes "1" and the 1-bit latch circuit 32 stores the contents of the data input terminal D.

Now, the contents of the data input terminal D at this time are as follows.

First, the input ICLK2 of the AND gate 52 becomes a logic "0" to which no signal is input, and the logic result of the AND gate 52 becomes "0" regardless of the contents of the serial data line ID2.

Therefore, OR gate 62 is dependent on the rational result of OR gate 42. Considering the OR gate 42, one end of the input is the serial data line.
It is connected to ID2, but since no signal is input, it is forced to logic "1" by the resistor 92, and the logic result depends on the input at the other end (output Q ₁ of 1-bit latch 31). .

That is, the data input terminal D of the 1-bit latch 32 receives the output signal "0" (1) of the 1-bit latch 31.
The bit latch 31 has a data input of "1", but since setup time is required, the output is not available at this point.
_Q1 is input as “0”).

Next, when the setup time has passed, the output terminal
“1” is output for Q ₄ and “0” for Q ₂ .

Thereafter, the 1-bit latches 33 to 3n undergo a similar shift operation to store the stored contents from the previous stage.

In the above description, the signal on the serial data input line ID is set to logic "1", but the same principle applies to logic "0".

Next, the signal "1" is input to the clock pulse line ICLK, and the third
Considering the case where a bit is selected, the result is as follows.

First, clock pulse line ICLK3 is selected,
Since it is connected to the AND gate 53, the logic is "1" in this case, and the AND result of the gate 53 depends on the signal content of the serial data line ID3. Therefore, if the input signal is logic "1", the output of the gate 53 is "1" and the OR gate 63
is input to one input end of the . Therefore, the OR gate 63 outputs "1" regardless of the other input terminal, and is input to the data input terminal D of the 1-bit latch 33. Conversely, if the signal on the serial data input line ID is logic "0", the logical product result of the AND gate 53 is "0", and the OR gate 63 is influenced by the other input terminal (output of the AND gate 43).
In this case, since the signal on the serial data line ID3 is logic "0", the logic result of the AND gate 43 is "0". That is, it has no relation to the output signal of the 1-bit latch 32 at the previous stage.

Now, the clock pulse line ICLK3 is also connected to one input terminal of the OR gate 73, and the output of the gate 73 becomes logic "1", thereby latching (memorizing) the signal contents of the data input terminal D mentioned above.

By the way, the other input terminal of the OR gate 73 is connected to the output terminal of the preceding OR gate 72, but since no signal is input to these, the logic is "0".
It is unrelated.

Next, the operations of each section connected to the subsequent stage are performed in the same manner as described above, and the contents stored in the 1-bit latch are shifted to the subsequent stage.

However, the 1-bit latch 31 to 32 at the stage preceding the 1-bit latch 33 is not affected at all because each signal is not input, and therefore their stored contents are retained.

Next, when the signal "1" is input to the clear input line ICLR and the third bit is selected by the address lines Ao to An, the output of the gate 83 is "1" because it is connected to one end of the OR gate 83. next door 1
The stored contents of the bit latch 33 are cleared, and since the output of the gate 83 is connected to the OR gate 84 at the subsequent stage, the 1-bit latch 34 is cleared, and the group of 1-bit latches at the subsequent stage are also cleared. However, each 1-bit latch 31 in the previous stage
.about.32 are not cleared because no signal is input. Therefore, its memory contents are retained.

As described above, input can be made to any bit of a shift register composed of multiple bits, the input contents of the previous stage bit can be retained, and the input to the previous stage bit can be prioritized in the shift operation. can be done.

Therefore, the present invention can be easily applied to the control of the conveyor line explained in FIG. 4 above.

Furthermore, although FIG. 4 shows control that requires the addition of parts, that is, the input of new serial data, various application methods can be considered.

For example, as shown in Figure 5, in a control where a product check at the end of several units indicates that all the products up to that point are likely to be defective, a clear input is forcibly entered and processing is performed in the subsequent process. It can also be used as a control.

In addition, as another use, by inputting several clock pulses and serial data from the middle,
There are many ways to apply it, such as replacing or modifying the pattern midway through.

〔Effect of the invention〕

According to the present invention, it is possible to perform a shift operation using a new input signal to the succeeding bits while retaining the memory up to an arbitrary bit in the shift register, so the effect can be easily performed without complicating the sequence circuit or its program. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional serial input shift register, FIG. 2 is a block diagram of a conventional serial/parallel input shift register, and FIG. 3 is a circuit diagram of a serial input shift register according to the present invention.
FIG. 4 and FIG. 5 are diagrams for explaining the present invention. 42-4n, 52-5n: AND gate, 62
~6n, 72~7n, 82~8n: Orgate,
91 to 9n: resistors, 101 to 103: selection circuits.

Claims (1)

[Claims] 1 It is a shift register with multiple stages and has a 1-bit latch provided in each stage of the multiple stages,
The one-bit latch has a data input terminal, a shift pulse input terminal, and an output terminal, and is supplied with an address signal and a data signal, and a first latch that supplies the data signal to the stage specified by the address signal.
a selection circuit, a shift pulse supply circuit that supplies a shift pulse to the stage specified above, and a shift pulse supply circuit provided at each stage after the second stage of the plurality of stages, when the stage is selected by the address signal, A second selection method for selectively supplying the data signal supplied to a stage, and when a stage preceding the stage concerned, selectively supplies the output signal of the 1-bit latch of the immediately preceding stage to the data input terminal of the 1-bit latch of the stage concerned. A shift register characterized by being equipped with a circuit.