JPS59116690A - Image display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image display device that can be used in display devices for teletext systems, captain systems, personal computers, television/video games, and the like.

Conventional configurations and their problems In recent years, display devices not only display characters and figures on the screen, but also have the function of erasing the screen, and there is a need to improve the screen display speed and screen erasing speed. There is. Figure 1 is a configuration diagram of a conventional image display device, in which (1) is a display circuit, (2)
) is an image memory in which image data to be displayed on the display circuit (1) is stored. A processor (3) controls the processing of the entire apparatus and reads and writes image data stored in the image memory (2).

(4)? ! The address bus (5) is a data bus, which is a signal line for exchanging values between the processor (3) and the image memory (2). The screen erasing operation of the image display device configured as described above will be explained below. To erase the screen, all you need to do is erase the image data stored in the image memory (2), and the processor (3) that controls the processing of the entire device
directly erases the image data in the image memory (2), however, during the period in which the processor (3) is erasing the image data in the image memory (2), the processor (3) directly erases the image data in the image memory (2). It had the disadvantage that it could not perform other processing.

FIG. 2 is a block diagram of another conventional image display device having a screen erasing function, in which a direct memory write circuit (6) is provided in addition to the structure shown in FIG. This direct memory write circuit (6) is connected to the processor (3) and the image memory (2) via an address bus (4) and a data bus (5). Now, in the image display device configured as shown in FIG. 2, when the processor (3) is not reading or writing image data in the image memory (2), the address bus (4) and data bus (5) are (3) When not in use, the direct memory write circuit (6) erases the image data in the image memory (2) in response to instructions from the processor (3) that controls the processing of the entire device. However, in the above configuration, the direct memory loading circuit (6) requires a circuit that generates a memory address that specifies the memory location for erasing the image data of the image memory (2). However, there was a problem in that the control thereof was also complicated.

OBJECTS OF THE INVENTION The present invention provides an image display device that does not require an address generation circuit for specifying image data to be used for erasing, and can erase one screen's worth of image data in the time it takes to display one screen without using a processor. purpose.

Structure of the Invention The image display device of the present invention includes a processor that controls processing of the entire device, an image memory that stores image data to be displayed by the processor, and a display that displays the image data stored in the image memory on a screen. and a memory control circuit for generating an erasing pattern for erasing image data stored in the image memory by the display circuit and the processor and controlling the erasing, and the memory control circuit is connected to the display circuit. The image data is erased by using the address output when reading the image data stored in the image memory as the address for erasing the image data stored in the image memory, thereby erasing the image data in the image memory. The screen is erased without using a circuit that generates a memory address that specifies a memory location for erasing the screen.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 3 to 5. FIG. 3 shows a configuration diagram of an image display device according to the present invention, where θυ is a processor that controls the processing of the entire device, θ is an image memory that stores image data to be displayed, and 0 is stored in the image memory θ. A display circuit 04) for displaying image data is a memory control circuit that controls reading and writing of the image memory θ. (101) (1,02) are a processor address bus and a processor data bus, both of which are signal lines for data communication between the processor θυ and the memory control circuit (+4).

(103) is a memory data bus, and the memory control circuit 04
) is connected to the image memory 0■ and the display circuit 0n, and is a signal line through which write data and read data are input and output to and from the image memory 0. (1o4) is a display address line through which the display circuit α□□□ specifies the memory address of the image memory Q2 in order to display the image data stored in the image memory (2) on the screen. It is connected. (105) is an image memory address line that specifies a memory address for reading and writing the image data stored in the image memory (+2), and the memory address specified by the processor 0υ or the memory address specified by the display circuit (13) is It is output from the memory control circuit θ and connected to the image memory 021. Reference numeral (106) is a memory control line, which is a signal line for controlling whether or not the image memory is activated.

FIG. 4 is a detailed diagram of the memory control circuit Q4) in FIG.
]) is an erase pattern register in which memory erase data is stored, (A) is a data selector, (C) is an address selector, (C) is a data buffer, and (C) is a control signal generation circuit. ) and the memory control line (106). (201) is the address select line, (202) is the data buffer control line, (
208) is an erase pattern write line, and (204) is a data select line. 3. Figure 5 is an operation waveform diagram showing signals output to the image memory address line (105), memory data bus (108), and memory control line (106). Figure 5 (a) shows the display operation. , (l) indicate an erase operation.

The operation and configuration of the image display device of this embodiment configured as described above will be explained in detail.

In FIG. 3, image data in an image memory 02) is read and written by a processor 01) and read out by a display circuit a. The memory control circuit (14) controls the image memory (12) by the processor 01) and the display circuit (13).
It controls the reading and writing of the data, and also controls the erasing operation.

The erase operation will be explained with reference to FIGS. 4 and 5. Let processor cycle (A) be the period during which the processor θ0 reads and writes the image memory θ→, and let the display cycle (B) be the period during which the display circuit a is reading out the image memory θ, the display circuit 03 reads the image by n bits. The image data in memory θa is read out, but in order to display it continuously, it is necessary to read it out repeatedly at regular intervals, so as shown in Figure 5 (a), the display cycle (B) is repeated at regular intervals, and the display cycle is repeated. (
The time other than B) is allocated to the processor cycle (A) 1. In order to erase the screen, it is sufficient to erase the image data in the image memory (6), and the display cycle shown in Fig. 5(a) Allocate an erase cycle instead. FIG. 5(b) shows that erase cycles (C) are performed alternately with processor cycles (A). The difference between the display cycle (B) and the erase cycle (C) is that in the cycle (B) displayed by the signal of the memory data bus (1Oa), image data is output from the image (Image memory Q), and in the erase cycle (C). '), erase data is output from the memory control circuit 0.4>, a read signal is output at the cycle (B) indicated by the memory control line (106'), and a write signal is output at the erase cycle (C). However, the display address is output to the image memory address line (105) regardless of the display cycle (B) or the erase cycle (C).

The memory control circuit a< that realizes the above operation will be explained in detail based on FIG. 4. In the processor cycle (A,), the processor 0υ reads and writes the image memory OJ through the memory control circuit 04), but when the processor 0]) performs a write operation, the control signal generation circuit (A) sends a message to the address selector (A). versus the processor address bus (
101,) and outputs a signal to the address select line (201) to output it to the image memory address line (105), and selects the processor data bus (1,02) for the data selector (a). Memory data bus (108
), and outputs a signal to the data select line (204) to output to the image memory 0, and also outputs a signal to the memory control line (1
06) to perform a write operation. When the processor 0]l) performs a read operation, the control signal generation circuit (a) selects the processor address bus (101) for the address selector (g) and selects the address to output it to the image memory address line (105). M (2ot), outputs a signal to the data buffer control line (202) for the data buffer (c) to output the memory data bus (10g) to the processor data bus (102), and Image memory (6)
A read signal is output to the memory control line (1'06) to perform a read operation. In the display book (B),
The display circuit θ group reads out the image memory θ smell through the memory control circuit (14), but when the display circuit α■ performs a read operation, the control signal generation circuit (
C) selects the display address line (104,) for the address selector (A) and selects the image memory address line (105,).
) is output to the address select line (201), and a signal is output to the memory control line (1) for the image memory (2).
A read signal is output to 06) and a read operation is performed.

At this time, image data from the image memory α is output to the memory data bus Hoa), and the display circuit 03 reads this image data.

Now, the operation of the erase cycle is as follows.

The control signal generation circuit (c) of the memory control circuit θXun outputs display address lines (104, 104,
) and outputs a signal to the address select line (201) to output it to the image memory address line (105).
A signal is output to the data select l-5S (204) to select the output of 1) and output it to the memory data bus (1o8), and the memory control line (106) is connected to the image memory 0'4.
') outputs a write signal and performs an erase operation. Even during the erase cycle (C), the display circuit (13 displays the data on the memory data bus (10, 9>), but during the erase cycle, the data on the memory data bus (108) is output from the erase pattern register Q1). Display circuit cL
ap displays this data, and in this way, the currently displayed image data in the image memory 02 can be erased in the display time of one screen. The erase pattern of the erase pattern register (QI) can be arbitrarily set by the processor 0υ, and is set using the erase pattern write line (208) of the control signal generation circuit (c).

In the second embodiment, the erasing pattern register Qυ is composed of a single number, but by using a plurality of registers and sequentially switching them, it is possible to erase with a more complicated pattern. In the embodiment, an example was shown in which display cycles and processor cycles were alternately performed, but it goes without saying that any combination may be used.

As described in the detailed description of the invention, according to the image display device of the present invention, the address for specifying the image data of the image memory generated by the display circuit is used as the address for erasing. A circuit for generating an address for specifying image data is unnecessary, and an excellent effect can be obtained in that one screen's worth of image data can be erased in the time it takes to display the screen without using a processor. As a result, the hardware of the display circuit and the erasing circuit is simplified, and the processor can perform processing without spending processing time on erasing the screen. Furthermore, by arbitrarily setting the erasing pattern stored in the erasing pattern register, it is possible to obtain the effect that the screen can be erased without being limited to a specific pattern.

[Brief explanation of the drawing]

1 and 2 are block diagrams of a conventional image display device, FIG. 8 is a block diagram of an embodiment of the image display device of the present invention, FIG. 4 is a detailed diagram of a memory control circuit, and FIG. 5 is a block diagram of an embodiment of the image display device of the present invention. It is an operation waveform diagram. (1) Display circuit, (2) Image memory, (3)
...Processor, (4) ...Address bus, (5)
...Data bus, (6)...Direct memory writing circuit, aυ...Processor, (6)--Picture column Φ memory, Q group...Display circuit, 041...Memory control circuit. Ql)... Erase pattern register, wire data selector, (A)... Address selector, H... Data buffer, (C)... Control signal generation circuit, (101
)...Processor address bus, (102)...
Processor data bus, (108)...Memory data bus, (104)...Display address line. (105)...Image memory address line, (106)
...Memory control line, (201)...Address select line, (202)...Data buffer control line,
(208)...Erase pattern writing line, (2
04) Data selection line agent Yoshihiro Morimoto (Figure 1 Figure 2 Figure 3 Figure 4 Figure 7/f4 Figure 5

Claims (1)

[Claims] 1. A processor that controls processing of the entire device, and an image memory that stores image data to be displayed by this processor;
a display circuit that displays the image data stored in the image memory on a screen; and a memory that generates and controls erasing patterns for erasing the image data stored in the image memory by the display circuit and the processor. A control circuit is provided, and the memory control circuit is configured to output the image data by using an address outputted when the display circuit reads the image data stored in the image memory as an address for erasing the image data stored in the image memory. An image display device configured to erase. 2. The image display device according to claim 1, wherein the erasing pattern generated by the memory control circuit can be set to any desired pattern by a processor that controls processing of the entire device.