JPS5911573U

JPS5911573U - FPN bit error rate measuring device

Info

Publication number: JPS5911573U
Application number: JP10624682U
Authority: JP
Inventors: 村崎　圭助; 谷垣　綱一; 御園生　勇
Original assignee: 日本放送協会
Priority date: 1982-07-15
Filing date: 1982-07-15
Publication date: 1984-01-24
Also published as: JPS6246383Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図はＦＰＮビット誤り率測定用パターンの構成例を
示す線図、第２図は本考案ＦＰＮビット誤り率測定装置
の構成例を示すブロック線図、第３図は同じくその各部
信号波形を示す波形図である。ＣＫ−ＰＴ・・・クロック信号再生用パターン、ＦＰＮ
−ＰＴ・・−ＦＰＮパターン、１−Ｘ、１−１〜１−９
゜１０．１８・・・アンドゲート、２−１〜２−９・・
・オアゲート、３−１〜３−９・・・シフトレジスタ、
４・・・多数決論理回路、５・・・２逓倍回路、６・・
・基準メモリ読出制御回路、７・＝・基準メモリ、８・
・・遅延回路、９・・・排他的オアゲート、１１・・・
カウンタ、１２・・・誤り表示器、１３・・・同期付加
回路、１４・・・同期分離回路、１５・・・８ｆｓｃ発
生回路、１６・・・ラインセレクタ、１７・・・クロッ
ク発生回路。６　　　　　　　　　　　　−FIG. 1 is a diagram showing an example of the configuration of a pattern for measuring FPN bit error rate, FIG. 2 is a block diagram showing an example of the configuration of the FPN bit error rate measuring device of the present invention, and FIG. 3 is a diagram showing the signal waveform of each part. FIG. CK-PT...Clock signal reproduction pattern, FPN
-PT...-FPN pattern, 1-X, 1-1 to 1-9
゜10.18...And gate, 2-1 to 2-9...
・OR gate, 3-1 to 3-9...shift register,
4...Majority logic circuit, 5...2 multiplier circuit, 6...
・Reference memory read control circuit, 7・=・Reference memory, 8・
...Delay circuit, 9...Exclusive OR gate, 11...
Counter, 12...Error indicator, 13...Synchronization addition circuit, 14...Synchronization separation circuit, 15...8fsc generation circuit, 16...Line selector, 17...Clock generation circuit. 6-

Claims

[Scope of utility model registration request]

FPNw that measures the FPN bit error rate of the FPN bit error rate measurement bang signal received by the teletext receiver
In the bit error rate measuring device, the clock recovery slam signal included in the received FPN bit error rate measuring bang signal over multiple lines is input into a plurality of shift registers line by line, and each shift is performed. While circulating in the register, a plurality of sets of output clock signals read from the plurality of shift registers are guided to a majority logic circuit to eliminate the loss of the output clock signal due to a bit error or line error in the clock regeneration bang signal. A clock signal synchronized with display scanning is generated over the entire display period of the teletext receiver by interpolating the above, and the received FPN is driven by the clock signal and read out from the memory device.
1. An FPN bit error rate measuring device, characterized in that the bit error rate is calculated by detecting erroneous pixels by comparing each pixel with a bang signal for bit error rate measurement.