SU1195345A1 - Device for displaying graphic information on televison receiver screen - Google Patents

Description

The invention relates to automation and computing and can be used to display information during training.

The purpose of the invention is to increase the speed and accuracy of the device.

FIG. 1 shows a block diagram of a device for displaying information on a television receiver screen; in fig. 2 - block diagram of 1 °, signal processing unit.

A device for displaying information contains a magnetic recorder 1, a signal processing unit 2, a register 3, a comparison unit 4, a buffer register 15, a switch 6, a memory block 7, a mixer 8, a carrier frequency generator 9, and a television receiver 10, a block 11 synchronization connected to the switch 20 6, block 7 RAM and mixer 8, register 12 connected to the buffer register 5, register 3 and

The block holds the lone spruce ',

ki, phase detector 16, second_ element 17 of delay · and selector 18 and 30 pulses of serially connected frequency multiplier 19, divider

unit 4 comparison.

2 signal processing sequentially, the first 13 and the second 14 first element 15 delay 2

20 frequency and shaper 21 clock pulses, shaper 22 pulse phase adjustment amplitude detector 23, the input of which is connected to the output of the first amplifier, and the output to the second input of the driver 21, the third input of which is connected to the second output of the multiplier 19 connected to the second input of the element 17 delays the output of which is connected to a first input of driver 22, a second input coupled to an output of the delay element 15 ·, a third input with the output of the phase detector 16, and an output - to a second house ⁷ vho- divider 20, a second output of which is connected to the second inputs of the phase detector 16 and the selector 18, the third input of which is connected to the output of the detector 16, while the output of the amplifier 14 <is connected to the input of the multiplier 19, the first output of which is connected to the second input of the element 15, the input of the amplifier 13 is the input of the unit, and the outputs of the shaper 21, the detector 16 and the selector 18 - the outputs of the block. ,

The device works as follows.

To play graphic and audio information on the tape recorder 1 is installed magnetic len3

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the one with sound and graphic information signals recorded on it. The soundtrack is recorded on one track of a magnetic tape, and on the other - a signal of graphic information in the form of a phase-shift keyed code sequence. The differences in the phase of the harmonic signal from "O" to "1" encode the coordinates of points of various patterns and graphical constructions displayed on the screen of the television receiver 10.

From the tape recorder '1, the signal enters the signal processing unit 2 of the graphic information, which serves 15 to extract the sequential code of the coordinates of the graphic information signal, the signal characterizing the beginning or end of the recording of coordinate numbers, and the synchronization signal of the same 20 pulses.

The selection of signals is as follows.

From the magnetic recorder 1, the graphic information signal arrives at the input 25 of the amplifier 13 of the signal processing unit 2 (FIG. 2). The amplifier 13 performs the correction at high and low frequency, i.e. correction of the signal in the required frequency range of the zone, which improves the accuracy of reproduction of the signal of graphic information. From the output of the amplifier 13, the signal enters the limiting amplifier 14 and then to the input of the frequency multiplier 19, where the phase shift keying is eliminated. From the output of the multiplier 19, the signal is fed to the input of the frequency divider 20, where a reference signal is generated for decoding the graphic information code ₄₀ . From the outputs of the multiplier 19 and divider 20, the signals are fed to the inputs of the driver .21 clock pulses, where the clock pulse signal is generated. In the absence of a graphic information signal, the input of the shaper 21 from the amplitude detector 23 is given a signal that prohibits the passage of the signal $ ₀ 'of the clock pulses. Amplitude detector 23 is designed to protect the device from noise interference.

The selection of the signal coordinates X and Y is as follows. 55

From the output of the amplifier 14, the signal is fed to the input of the element 15 delay, the second input of which is connected to the multiplier, 19 frequency. The signal from the output of the element 15 delay is on. one input of the phase detector 16, to the second input of which a reference signal is supplied from the output of the frequency divider 20. Thus, there is a transformation of the coordinate code with phase shift keying into a pulse signal.

On the element 17 of the delay and the selector 18 is the selection signal "End of the word". To the first input of the delay element 17, a signal is output from the output of the phase detector 16, and to the second input is a signal from the output of the frequency multiplier 19. C / output element 17 of the delay signal is fed to the first input of the selector 18, to the second input - the signal from the frequency divider 20, to the third non-delayed signal of graphic information from the phase detector 16.

To eliminate the jump-like change in the phase of the reference signal, which is caused by the action of various interferences and leads to "reverse operation",

those. Failure to decipher the signal during phase shift keying, in signal processing unit 2, the driver of 22 phase adjustment pulses is input, to one input of which a signal is output from the phase detector GB, and to the other inputs signals from delay elements 17. From the output of the shaper 22. Impulses phase adjustment signal arrives at the installation input of the divider frequency 20. Registers 3 and 12 are used to convert information from a sequential code into a parallel one. Recording into registers 3 and 12 is done using clock pulses from block 2. A word end pulse determines the write cycle to the register. In case of equality of two numbers recorded in registers 3 and 12 ^, comparison unit 4 generates a resolution command and information from register 12 is written into buffer register 5.

The use of two registers 3 and 12 and the comparison unit 4 increases the noise immunity of the device due to the accumulation of the signal in the unit and the comparison, i.e. confirm the signal twice.

To form a television

signal, control signals, switch 6 and operational memory5

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The device 7 is the synchronization unit 11.

The video signal is formed as follows.

During the passage of a television line, 256 memory cells of block 7 are sequentially polled; moreover, if “O” is recorded in the cell, the signal accepts the black level *, if it is “1”, then the white level.

At the end of the line is generated string sync pulse. To approximate the decomposition to the television standard, each line is polled twice during each half-frame. After a 256-line interrogation, a frame sync pulse is formed. Thus, the resulting image has a format of 256 x 256 pixels. The addressable memory cells are received in memory block 7 from synchronization block 11 via a commutator 6 during the straight-line horizontal sweep. The information is recorded in ”block 7 during the validity of the horizontal sync pulse. For the duration of this pulse, the switch 6 connects to the address inputs of block 7 information stored in buffer register 5 ..

Thus, the address of the cell in which the unit information is recorded is called: what appears on the screen of the television receiver 10 ₃₅

in the form of a luminous point.

Random access memory 7 (RAM) is a memory matrix with an information capacity of 64 debits. 40

. To ensure the required speed of RAM is divided into 4 modules. Information is read sequentially from each RAM module with time-shifted polling signals 45. From the output of the RAM data is fed into the mixer 8, to the other input of which the lowercase and personnel are fed

clock pulses. In mixer 8, data from RAM 7 is recorded with sync pulses and at its output ₅ a full television signal appears, which is fed to the input of a carrier frequency generator 9, tuned ¹ to one of the television channels. The harmonic signal of the generator 9 is modulated in amplitude by the full television signal and fed through the antenna input to the television receiver.

Phase detector 16 is made on the item EXCLUSIVE OR. The selector 18 is made on the logical element AND-NOT. The shaper 22 phase adjustment pulses are made on the elements EXCLUSIVE OR and NAND.

Technical and economic effect of the proposed device is to improve noise immunity, since electrical noise, frequency and phase distortions of the reproducing cycles of the device, which negatively affect the accuracy of reproduction of graphic information, are eliminated by passing through the signal processing unit 2.

The presence in the device of the second register 12, block 4 comparison and buffer register 5 allows the accumulation of the useful signal, i.e. confirms it twice, which leads to an increase in the noise immunity of the device and an increase in the reliability of the reproduced signal of graphic information.

Compared with the basic object, the teaching machine according to the schedule "ALA TOO - 4 - P", the proposed device for reproducing graphic information has enhanced didactic possibilities, since it is a means of multiple reproduction of graphic information with sound.

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Claims (2)

1.DESIGN FOR DISPLAYING INFORMATION ON SCREEN OF A TELEVISION RECEIVER, containing a magnetic recorder, serially connected synchronization unit and RAM, first and second connected in series, registers, carrier frequency generator, connected to a television receiver, characterized in that, for the purpose of raising performance and accuracy of the device, it contains a signal processing unit, the input of which is connected to a magnetic recorder, and the first, second and third outputs are connected to the corresponding inputs Dami first register, successively connected comparison unit, buffer register and switch, the output of which is connected to the second input of the RAM unit, and the second and third inputs respectively with the second and third outputs of the synchronization unit, the second output of the first register connected to the first input of the comparison unit, the mixer, the first input of which is connected to the output of the operating memory unit, the second input to the fourth output of the synchronization unit, and the output of the mixer to the input of the carrier frequency generator, the output of the second register RA is connected to the 'second inputs of the buffer register and the comparison unit. <Rie. / > eleven 2. The device according to claim 1, wherein the signal processing unit comprises a first amplifier connected in series, a second amplifier, a first delay element, a phase detector, a second delay element and a pulse selector connected in series by a frequency multiplier, a frequency divider and a clock pulse shaper, a phase trimmer shaper, an amplitude detector, whose input is connected to the output of the first amplifier, and an output to a second clock shaper input, the third input of which is connected with the second output of the frequency multiplier and the second input of the second delay element, the output of which is connected to, the first input of the phase adjustment pulse shaper, the second input of which is connected to the output of the first delay element, the third input - with the output of the phase detector, and the output - with the second input frequency divider, the second output of which is connected to the second inputs of the phase detector and pulse selector, the third input of which is connected to the output of the phase detector, the output of the second amplifier is connected to the input of a frequency multiplier, the first output which is connected to the second input of the first delay element, the input of the first amplifier is the input of the block, and the outputs of the clock generator, the phase detector and the output pulse selector of the block. one