JPS59115546A - Enclosure for semiconductor element - Google Patents

Enclosure for semiconductor element

Info

Publication number
JPS59115546A
JPS59115546A JP57225536A JP22553682A JPS59115546A JP S59115546 A JPS59115546 A JP S59115546A JP 57225536 A JP57225536 A JP 57225536A JP 22553682 A JP22553682 A JP 22553682A JP S59115546 A JPS59115546 A JP S59115546A
Authority
JP
Japan
Prior art keywords
mount
hole
solid
enclosure
state image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57225536A
Other languages
Japanese (ja)
Inventor
Shigeru Sato
滋 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP57225536A priority Critical patent/JPS59115546A/en
Publication of JPS59115546A publication Critical patent/JPS59115546A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To enable to mount a solid state image sensor without damaging the surface of the sensor in an enclosure which has a mount for mounting the sensor by providing a hole for attracting an element smaller than the sensor on the bottom of the mount. CONSTITUTION:An enclosure for a semiconductor element is composed of a ceramic package 1 and an optical window material 5 for covering the surface, and a hole 7 for attracting an element is opened at the center of a mount 6 for the package 1. The hole 7 is not necessarily formed in a circular shape, and may not be formed at the center of the mount 6, but the size of the hole is formed in such a manner to be smaller than the element 3 and in size capable of inserting vacuum pincers. The enclosure is thus constructed, the pincers are first inserted from the lower surface of the hole 7, the back surface of the element 3 is attracted, and the element 3 is secured with an adhesive to the mount 6 while pulling the element 3 to the mount 6. Subsequently, the electrodes of the element are connected to the electrodes of the package 1 via bonding wirings 4, and the hole 7 is blocked with low melting point glass. In this manner, the damage of the element 3 is avoided.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体素子をマウントする半導体素子用外囲器
に係り、特に固体撮像素子に適した外囲器に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an envelope for a semiconductor device that mounts a semiconductor device, and particularly to an envelope suitable for a solid-state image sensor.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

テレビジョンカメラ等に用いられるＣＣＤ、ＢＢＤなど
の固体撮像素子は、その素子表面に入力する光に応じて
発生した電荷を蓄積し、その電荷を出力信号として得る
ものであり、その素子表面が均一に保たれていることが
重要である。このような固体撮像素子をマウントする外
囲器として、従来は第１図に示すようなものが用いられ
ていた。Solid-state imaging devices such as CCDs and BBDs used in television cameras, etc., accumulate charges generated in response to light input to the surface of the device, and obtain the charges as output signals, and the surface of the device is uniform. It is important that the Conventionally, an envelope as shown in FIG. 1 has been used to mount such a solid-state image sensor.

これは通常の半導体素子用の外囲器と基本的には同じで
あり、セラミックパッケージｌを光が透過する光学窓材
Ｓでおおって形成する。固体撮像素子３はセラミックパ
ッケージｌに設けられたマウント部乙に接着剤コで固着
され、固体撮像素子３の電極はセラミックパッケージｌ
の電極とボンディングワイヤダで電気的に接続される。This is basically the same as an ordinary envelope for semiconductor devices, and is formed by covering a ceramic package I with an optical window material S through which light passes. The solid-state image sensor 3 is fixed to the mount part B provided in the ceramic package l with an adhesive, and the electrodes of the solid-state image sensor 3 are attached to the ceramic package l.
It is electrically connected to the electrode using a bonding wire.

このような外囲器に固体撮像素子３をマウントする場合
は、バキュームピンセット等で固体撮像素子３０表面を
吸着させて保持し、この状態で接着剤コを介してセラミ
ックパッケージ／のマウント部６に固体撮像素子３を押
しつけてマウントすることになる。このためマウント時
に固体撮像素子３の表面をバキュームピンセット等でキ
ズをつげる場合があり、特性劣化、歩留り低下の原因と
なっていた。When mounting the solid-state image sensor 3 on such an envelope, hold the surface of the solid-state image sensor 30 by adsorption with vacuum tweezers or the like, and in this state attach it to the mount part 6 of the ceramic package via adhesive. The solid-state image sensor 3 is pressed and mounted. For this reason, the surface of the solid-state image sensor 3 may be scratched with vacuum tweezers or the like during mounting, which causes deterioration of characteristics and reduction in yield.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情を考慮してなされたもので、半導体素
子の表面にキズなつけることなくマウントすることがで
きる半導体素子用外囲器を提供することを目的とする。The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide an envelope for a semiconductor element that can be mounted without damaging the surface of the semiconductor element.

〔発明の概要〕[Summary of the invention]

この目的を達成するために本発明による半導体素子用外
囲器は、マウント部の底部に半導体素子吸引用の孔が設
けられていることを特徴とする。In order to achieve this object, the semiconductor device envelope according to the present invention is characterized in that a hole for sucking the semiconductor device is provided at the bottom of the mount portion.

〔発明の実施例〕[Embodiments of the invention]

本発明を図示の実施例により説明する。 The present invention will be explained by means of illustrated embodiments.

第２図に示すように、本実施例による半導体素子用外囲
器も固体撮像素子をマウントするものであり、セラミッ
クパッケージ／と光学窓材Ｓとがらなっている。そして
セラミックパッケージ／のマウント部乙の中心に半導体
素子吸引用の孔７が設けられている。この孔りは必ずし
も円形である必要はなく、マウント部乙の中心に位置す
る必要もないが、少なくともバキュームピンセットを入
れるだけの大きさを有し、かつ突き抜けており、またマ
ウントする固体撮像素子より小さいことが必要である。As shown in FIG. 2, the semiconductor device envelope according to this embodiment also mounts a solid-state imaging device, and is made up of a ceramic package and an optical window material S. A hole 7 for sucking the semiconductor element is provided in the center of the mount part B of the ceramic package. This hole does not necessarily have to be circular, nor does it need to be located in the center of the mount part B, but it should be at least large enough to insert the vacuum tweezers, and should be penetrating through it, and should be closer to the solid-state image sensor to be mounted. It needs to be small.

このような半導体素子用外囲器に固体撮像素子３をマウ
ントするには次のようにしておこなう。The solid-state imaging device 3 is mounted on such a semiconductor device envelope as follows.

まず、セラミックパッケージｌの底の方から孔７を通し
て固体撮像素子３の裏面（すなわち受光面の反対側の面
）をバキュームピンセット等で吸引して保持する。そし
て接着剤コを介して固体撮像素子３をセラミックパッケ
ージのマウント部乙に引きつげてマウントする。次に、
固体撮像素子３の電極とセラミックパッケージｌの電極
をボンディングワイヤダで電気的に接続し、その後セラ
ミックパッケージ／の孔りを例えば樹脂等を用いて封止
する。この封止のための材料は低融点ガラスでもよい。First, the back surface (ie, the surface opposite to the light-receiving surface) of the solid-state image sensor 3 is sucked and held through the hole 7 from the bottom of the ceramic package 1 using vacuum tweezers or the like. Then, the solid-state image sensor 3 is pulled and mounted on the mount part B of the ceramic package via an adhesive. next,
The electrodes of the solid-state imaging device 3 and the electrodes of the ceramic package 1 are electrically connected using a bonding wire, and then the holes in the ceramic package are sealed using, for example, resin. The material for this encapsulation may be a low melting glass.

次にセラミックパッケージ上部を光学窓材Ｓによりシー
ルする。なお孔、７の封止は、固体撮像素子３のマウン
ト後であればよ（、マウント直後でも光学窓材Ｓによる
シールと同時またはシール後でもよい。場合によっては
孔７を封止せずそのままにしておいてもよい。Next, the upper part of the ceramic package is sealed with an optical window material S. Note that the hole 7 may be sealed after the solid-state image sensor 3 is mounted (it may be done immediately after mounting, at the same time as sealing with the optical window material S, or after sealing. In some cases, the hole 7 may be left unsealed. You can leave it there.

第３図に本発明の他の実施例による半導体素子用外囲器
を示す。先の実施例と基本的には同じであるが、異なる
ところはセラミックパッケージ／のマウント部乙の底面
の大きさを固体撮像素子３よりわずかに大きくし、その
位置は固体撮像素子３がマウントされたときにその中心
がセラミックパッケージ／の中心と合致するようになっ
ている。FIG. 3 shows an envelope for a semiconductor device according to another embodiment of the present invention. It is basically the same as the previous embodiment, but the difference is that the bottom surface of the mount part B of the ceramic package is slightly larger than the solid-state image sensor 3, and the solid-state image sensor 3 is mounted at that position. Its center is aligned with the center of the ceramic package.

さらにマウント部乙の内側面が外側に向かって傾斜して
おり、マウントしやすくなっている。孔７を通して固体
撮像素子３を吸着してマウントする場合は位置合せが難
かしいが、このような外囲器を用いることにより簡単に
位置合せをおこなうことができる。Furthermore, the inner surface of the mount part B is inclined outward, making it easier to mount. Although positioning is difficult when mounting the solid-state image sensor 3 by suction through the hole 7, the positioning can be easily performed by using such an envelope.

なお、半導体素子として固体撮像素子を例として説明し
てきたが、他の半導体素子の外囲器にも用いることがで
きるのはいうまでもない。Although the solid-state image sensing device has been described as an example of the semiconductor device, it goes without saying that the present invention can also be used as an envelope for other semiconductor devices.

〔発明の効果〕〔Effect of the invention〕

以上の通り、本発明によれば半導体素子をマウントする
ときに均一でかつキズがつかないことが必要とされる表
面を触れることなく、外囲器にマウントすることができ
、半導体素子の劣化防止、歩留り向上を実現することが
できる。As described above, according to the present invention, when mounting a semiconductor element, it is possible to mount the semiconductor element on the envelope without touching the surface that is required to be uniform and scratch-free, thereby preventing deterioration of the semiconductor element. , it is possible to realize an improvement in yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体素子用外囲器の断面図、第２図（
ａ）　ｌ　（ｂ）はそれぞれ本発明の一実施例による半
導体素子用外囲器の平面図およびＡ　−Ａ’断面図、第
３図は本発明の他の実施例による半導体素子用外囲器の
断面図である゛。 ／・・・セラミックパッケージ、コ・・・接着剤、３・
・・固体撮像素子、ダ・・・ボンディングワイヤ、Ｓ・
・・光学窓材、６・・・マウント部、７・・・孔。 出願人代理人　　猪　股　　　　清 第２図 第３図Figure 1 is a sectional view of a conventional envelope for semiconductor devices, and Figure 2 (
a) l (b) are respectively a plan view and a sectional view taken along the line A-A' of an envelope for a semiconductor device according to an embodiment of the present invention, and FIG. 3 is an envelope for a semiconductor device according to another embodiment of the present invention. This is a cross-sectional view of ゛. /...Ceramic package, Co...Adhesive, 3.
・・Solid-state image sensor, ・Bonding wire, S・
...Optical window material, 6...Mount part, 7...Hole. Applicant's agent Kiyoshi Inomata Figure 2 Figure 3

Claims (1)

【特許請求の範囲】 ／半導体素子をマウントするマウント部が設けられた半
導体素子用外囲器において、前記マウント部の底部に前
記半導体素子より小さい半導体素子吸引用の孔が設けら
れていることを特徴とする半導体素子用外囲器。 ２特許請求の範囲第１項記載の半導体素子用外囲器にお
いて、前記半導体素子は固体撮像素子であることを特徴
とする半導体素子用外囲器。[Claims] / In a semiconductor device envelope provided with a mount portion for mounting a semiconductor device, it is provided that a hole for sucking the semiconductor device smaller than the semiconductor device is provided at the bottom of the mount portion. Features: Envelopes for semiconductor devices. 2. The envelope for a semiconductor device according to claim 1, wherein the semiconductor device is a solid-state image sensor.
JP57225536A 1982-12-22 1982-12-22 Enclosure for semiconductor element Pending JPS59115546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57225536A JPS59115546A (en) 1982-12-22 1982-12-22 Enclosure for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57225536A JPS59115546A (en) 1982-12-22 1982-12-22 Enclosure for semiconductor element

Publications (1)

Publication Number Publication Date
JPS59115546A true JPS59115546A (en) 1984-07-04

Family

ID=16830828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57225536A Pending JPS59115546A (en) 1982-12-22 1982-12-22 Enclosure for semiconductor element

Country Status (1)

Country Link
JP (1) JPS59115546A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0300590A2 (en) * 1987-07-22 1989-01-25 Director General, Agency of Industrial Science and Technology Semiconductor device package structure
JP2006100497A (en) * 2004-09-29 2006-04-13 Kyocera Corp Package for housing electronic component and electronic apparatus
US7789334B2 (en) 2004-02-19 2010-09-07 Kabushiki Kaisha Kinki Shredding machine and shredding method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0300590A2 (en) * 1987-07-22 1989-01-25 Director General, Agency of Industrial Science and Technology Semiconductor device package structure
US7789334B2 (en) 2004-02-19 2010-09-07 Kabushiki Kaisha Kinki Shredding machine and shredding method
JP2006100497A (en) * 2004-09-29 2006-04-13 Kyocera Corp Package for housing electronic component and electronic apparatus

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