JPS59114868A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS59114868A JPS59114868A JP57224160A JP22416082A JPS59114868A JP S59114868 A JPS59114868 A JP S59114868A JP 57224160 A JP57224160 A JP 57224160A JP 22416082 A JP22416082 A JP 22416082A JP S59114868 A JPS59114868 A JP S59114868A
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- Prior art keywords
- impurity
- alloy film
- film
- semiconductor device
- doping
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、高融点金属硅化物をゲート電極材料として用
いたＭＩＳ型半導体装置及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a MIS type semiconductor device using a high melting point metal silicide as a gate electrode material and a method for manufacturing the same.
近時、ＭＩＳ型半導体装置のゲート電極材料として、多
結晶シリコンの代りにモリブデン（ＭＯ）やタングステ
ン（Ｗ）等の高融点金属の硅化物が使用されている。そ
の理由は、高融点金属硅化物の抵抗が多結晶シリコンの
抵抗に比し約１桁も低く、かつ硅化物であることから後
の酸化及びその他の熱処理工程で安定なためである。Recently, silicides of high-melting point metals such as molybdenum (MO) and tungsten (W) have been used instead of polycrystalline silicon as gate electrode materials for MIS semiconductor devices. The reason for this is that the resistance of high melting point metal silicide is about an order of magnitude lower than that of polycrystalline silicon, and since it is a silicide, it is stable during subsequent oxidation and other heat treatment steps.
一方、高融点金属硅化物はそのシリコン成分を過剰とす
るごとにより、絶縁膜を形成したシリコン基板との密着
性及び酸化に対する安定性が増すことが知られており、
高融点金属硅化物中のシリコン成分を過剰とするのが通
常である。On the other hand, it is known that increasing the silicon content of high melting point metal silicide increases its adhesion to the silicon substrate on which the insulating film is formed and its stability against oxidation.
Usually, the silicon component in the high melting point metal silicide is excessive.
しかしながら−シリコン成分が過剰な高融点金属硅化物
をＭＩＳ）ランジスタのゲート電極等に用いる場合、熱
処理工程で金属硅化物中のシリコンがゲート絶縁膜との
界面に析出し、ＭＩＳ構造のフラットバンド電圧が丘記
析出したシリコン層の仕事関数により決定される。した
がって、析出したシリコン中の不純物量によりフラット
バンド電圧ＶＦＲが変化することになり、その制御性は
極めて困難である。このため、ゲートシきい値電圧ＶＴ
Ｈの制御性も極めて悪いものであった。However, when a high melting point metal silicide with an excessive silicon content is used for the gate electrode of an MIS transistor, the silicon in the metal silicide precipitates at the interface with the gate insulating film during the heat treatment process, resulting in a flat band voltage of the MIS structure. It is determined by the work function of the deposited silicon layer. Therefore, the flat band voltage VFR changes depending on the amount of impurities in the deposited silicon, and its controllability is extremely difficult. Therefore, the gate threshold voltage VT
Controllability of H was also extremely poor.
そこで最近、上記問題を解決するものとして、Ｍｏ−８
ｉ合金膜に燐をドーピングする方法が提案されている（
Ｊ、 Ｅｌｅｃｔｒｏｃｈｅｍ、 Ｓｏｃ、 １２８
＋２４０２（１９８１） ）。この方法では、可動イ
オンのゲヅタリング等により、シリコン成分が過剰なＭ
ｏ−８ｉ合金膜をゲート電極として安定化することがで
きる。しかしながら、この方法：二お（する燐の導入法
は、Ｍｏ ８１合金膜の被着時に燐を混入するもので
あり、同レベルのゲート配線を用いている限りＭＯ８Ｐ
ランジスタのゲートしきい値電圧ＶＴＲを制御すること
は困難である。したがって、しきい値電圧ＶＴＲを制御
するにはチャネル領域の不純物濃度を変える必要がある
。Recently, as a solution to the above problem, Mo-8
A method of doping phosphorus into an i-alloy film has been proposed (
J, Electrochem, Soc, 128
+2402 (1981)). In this method, excessive M
It is possible to stabilize the o-8i alloy film by using it as a gate electrode. However, this method: Introducing phosphorus involves mixing phosphorus when depositing the Mo81 alloy film, and as long as the same level of gate wiring is used, MO8P
It is difficult to control the gate threshold voltage VTR of a transistor. Therefore, in order to control the threshold voltage VTR, it is necessary to change the impurity concentration in the channel region.
このように従来、ＭＯ８）ランジスタのしきい値電圧Ｖ
ＴＲを制御するにはチャネル領域の不純物濃度を変えな
ければならないが、この方法によるしきい値電圧ＶＴＨ
の制御性は良好とは云い難いものであった。In this way, conventionally, the threshold voltage V of MO8) transistor is
To control TR, it is necessary to change the impurity concentration in the channel region, but this method reduces the threshold voltage VTH.
The controllability was far from good.
本発明の目的は、集積回路内に複数のＭＩＳトランジス
タを含む場合等に、チャネル領域の不純物濃度を変える
ことなく−デートしきい値電圧を制御することができ、
かつその制御性の向丘を□はかり得る半導体装置及びそ
の製造方法を提供することにある。An object of the present invention is to be able to control the -date threshold voltage without changing the impurity concentration of the channel region, such as when a plurality of MIS transistors are included in an integrated circuit.
It is also an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can measure its controllability.
本発明の骨子は、ゲート電極材料としての高融点金属硅
化物に任意の実効的仕事関数を持たせることにより、し
きい値電圧ＶＴＲを制御することにある。The gist of the present invention is to control the threshold voltage VTR by giving a high melting point metal silicide as a gate electrode material an arbitrary effective work function.
シリコン成分が過剰な高融点金属硅化物ｊ二■Ａ族若し
くはＶＡ族の不純物をドーピングすると、そのフラット
バンド電圧が変化する。第１図は本発明者等の実験に基
づくＭｏ−８ｉ合金膜に不純物をドーピングした場合の
、Ｍｏ 、 Ｓ ｉの原子比とフラットバンド電圧との
関係を示す特性図である。実験条件としては、６〜８〔
Ω儂〕のＰ形（１００）Ｓ ｉ基板上に４００〔久〕の
ゲート酸化膜を形成し、このＪｌｌ：Ｍｏ−８ｉ合金膜
をスパッタ法で約３５００（Ｘ） 堆積し、ボロン或
いは燐をそれぞれ加速電圧２５（Ｋｅｙ）、６０＋６
−２
（Ｋｅｙ）、 ドーズ備１ｘｘｏ 〜ｌＸｌ０ （
ｃ＋ａ ）でイオン注入したのちＭｏ−８ｉ合金膜を
電極配線パターンに加工した。次いで、乾燥雰囲気中に
て１０００〔℃〕、 １０分の酸化を行い、Ｃ、Ｖ Ｄ
法により５０００（１） の５１０２膜を被着したの
ち、ＰＯ（：、１３を含む雰囲気中にて９００〔℃〕、
６０分の加熱処理を行い、その後１０〔％〕の水素を含
む窒素雰囲気中にて４５−０〔℃〕、１５分の熱処理を
行った。この状態での特性が第１図であり、図中○、△
１ロ印はボロンドープの場合、０、ム、■印は憐ドープ
の場合を示している。When a high melting point metal silicide with an excessive silicon component is doped with group A or group VA impurities, its flat band voltage changes. FIG. 1 is a characteristic diagram showing the relationship between the atomic ratio of Mo and Si and the flat band voltage when an impurity is doped into a Mo-8i alloy film based on experiments conducted by the present inventors. The experimental conditions were 6 to 8 [
A gate oxide film with a thickness of 400 μm is formed on a P-type (100) Si substrate of Ωme], and this Jll:Mo-8i alloy film is deposited with a thickness of approximately 3500× by sputtering, and boron or phosphorus is applied. Acceleration voltage 25 (Key), 60+6 respectively
-2 (Key), Doze 1xxo ~lXl0 (
After ion implantation in c+a), the Mo-8i alloy film was processed into an electrode wiring pattern. Next, oxidation was performed at 1000 [°C] for 10 minutes in a dry atmosphere to obtain C, V D
After depositing a 5102 film of 5000 (1) by the method, it was heated to 900 [℃] in an atmosphere containing PO (:,
Heat treatment was performed for 60 minutes, and then heat treatment was performed for 15 minutes at 45-0 [° C.] in a nitrogen atmosphere containing 10 [%] hydrogen. The characteristics in this state are shown in Figure 1, with ○ and △ in the figure.
The 1 RO mark indicates the case of boron dope, and the 0, MU, and ■ marks indicate the case of mercy dope.
第１図から明らかなように、Ｍｏ−８ｉ系で最もＳｉ成
分の多いＭＯ８Ｉ２よりもＳｉ成分が過剰なＭｏ−Ｓｉ
合金にボロン或いは燐をドープすることにより、熱処理
後ゲート酸化膜上に析出したＳｌにボロン若しくは燐が
ドープされ、多結晶Ｓｉにボロン若しくは燐をドープし
た場合と同じフラットバンド電圧ＶＦＢ となること
が判る。また、ボロンや燐等の注入量により、フラット
バンド電圧ＶＦＲが任意に制御されることも判る。As is clear from Fig. 1, Mo-Si has an excess of Si component compared to MO8I2, which has the largest amount of Si component in the Mo-8i system.
By doping the alloy with boron or phosphorus, the Sl deposited on the gate oxide film after heat treatment is doped with boron or phosphorus, resulting in the same flat band voltage VFB as when polycrystalline Si is doped with boron or phosphorus. I understand. It can also be seen that the flat band voltage VFR can be arbitrarily controlled by the amount of boron, phosphorus, etc. implanted.
本発明はこのような点に着目し、高融点金属と該金属に
対し原子比で２倍以上のシリコンとの合金膜からゲート
電極を構成したＭＩＳ型半導体装置において、上記合金
膜に■ＡＡ族不純物びＶＡ族不純物の少なくとも１種を
ドーピングし、かつ上記合金Ｈ便からなる少なくとも２
つのゲート電極で不純物ドーピング条件を変えるように
したものである。The present invention focuses on these points, and provides an MIS type semiconductor device in which a gate electrode is formed from an alloy film of a high melting point metal and silicon whose atomic ratio is more than twice that of the metal. At least two impurities doped with at least one of group VA impurities and consisting of the above alloy H
The impurity doping conditions are changed for each gate electrode.
また本発明は、Ｌ記構酸のＭＩＳ型半導体装置を製造す
るに際し、半導体基板−ヒにゲート絶縁膜を介して前記
合金膜を被着したのち、この合金膜にＩＩＩ Ａ族不純
物及びＶＡ族不純物の少なくとも１種をドーピングする
と共に、該合金膜の少なくとも２つのゲート電極形成予
定領域で不純物ドーピング条件を異ならせ−次いで上記
合金膜をゲート電極パターンに加工するようにした方法
である。Further, in manufacturing an MIS type semiconductor device of the L structure acid, the present invention provides that after the alloy film is deposited on the semiconductor substrate via a gate insulating film, the alloy film is coated with III-A group impurities and VA-group impurities. In this method, at least one kind of impurity is doped, and the impurity doping conditions are made different in at least two gate electrode formation regions of the alloy film, and then the alloy film is processed into a gate electrode pattern.
本発明によれば、シリコン成分が過剰な高融点金属硅化
物をＭＩＳトランジスタのゲート電極として用いる場合
、Ｎ 或いはＰ の多結晶シリコンを用いた場合と同程
度のしきい値電圧■ＴＨを制御性良く実現することがで
きる。また、チャネル領域の不純物濃度を変える方法に
比して、しきい値電圧ＶＴＨの制御性向Ｅをはかれる等
の利点がある。According to the present invention, when a high-melting point metal silicide with an excessive silicon content is used as the gate electrode of a MIS transistor, the threshold voltage ■TH can be controlled to the same degree as when N or P polycrystalline silicon is used. It can be well realized. Furthermore, compared to the method of changing the impurity concentration of the channel region, this method has advantages such as the ability to control the threshold voltage VTH.
第２図（ａ）〜（ｄ）は本発明の一実施例に係わるＣ−
ＭＯＳ ）ランジスタの製造工程を示す断面図である。FIGS. 2(a) to 2(d) show C-
FIG. 3 is a cross-sectional view showing the manufacturing process of a MOS transistor.
まず、第２図（ａ）に示す如く、燐を２×１０儂 ドー
プしたＮ形Ｓｉ基板ｌにボロ、ン濃度５Ｘ１０１５ｃｍ
’のＰウェル２を形成したのち、基板１上にフィールド
酸化膜３及び３００Ｘのゲート酸化膜４を形成した。続
いて、スパッタ法等を用いＳｉ成分過剰なＭｏ−８ｉ□
、５合金膜５を全面に約３５００〔久〕 堆積した。First, as shown in Fig. 2(a), an N-type Si substrate l doped with phosphorus at a concentration of 2 x 10 cm was coated with a boron concentration of 5 x 1015 cm.
After forming a P-well 2 of ', a field oxide film 3 and a gate oxide film 4 of 300X were formed on the substrate 1. Subsequently, using a sputtering method or the like, Mo-8i□ with an excessive Si content is
, 5 alloy film 5 was deposited on the entire surface for about 3,500 days.
次に、８２図（ｂｌに示す如くＰウェル領域２上のみを
レジスト６で覆い、露出している合金膜５に設定したし
きい値電圧ＶＴＨとなるべくボロンを加速電圧２５（Ｋ
ｅｙ）、 ドーズｔＪ５Ｘ１０”ＣＣｍ″〕でイオン注
入した。次いで、第２図（Ｃ）に示す如くレジスト６を
除去し、Ｐウェル領域２上以外を新たなレジスト７で覆
い、先と同様に露出している合金膜５に砒素を加速電圧
１２０［：ＫｅＶ）％ ドーズ量５Ｘ１０ Ｃｃｒｎ
］でイオン注入した。その後、熱処理を施し、合金
膜５に注入されたイオンを活性化した。Next, as shown in FIG. 82 (bl), only the top of the P well region 2 is covered with a resist 6, and boron is applied to the exposed alloy film 5 at an accelerating voltage of 25 (K
ey), ion implantation was performed at a dose of tJ5×10"CCm"]. Next, as shown in FIG. 2(C), the resist 6 is removed, areas other than the P well region 2 are covered with a new resist 7, and arsenic is applied to the exposed alloy film 5 at an accelerating voltage of 120 [: KeV)% Dose amount 5X10 Ccrn
] Ion implantation was performed. Thereafter, heat treatment was performed to activate the ions implanted into the alloy film 5.
次に、周知の技術を用い第２図（ｄ）に示す如く合金膜
５のパターニング、ソース・ドレイン１１．１２の形成
、絶縁膜１３の被Ｍ−コンタクトホール形成及びｌ配線
パターン１４の形成を行うことにより、Ｃ−ＭＯ８）ラ
ンジスタが完成することになる。かくして作成されたＣ
−ＭＯＳトランジスタは、Ｐチャンネルトランジスタ
においてそのしきい値電圧ＶＴ Ｈカー０．２５〔Ｖ〕
となり、ｎチャンネルトランジスタにおいてそのし
きい値電圧ＶＴＲが、−０，２０〔Ｙ）となり、所望す
るＶＴＲに一致させる事が可能となった。Next, using well-known techniques, as shown in FIG. 2(d), the alloy film 5 is patterned, the source/drain 11 and 12 are formed, the M-contact hole is formed in the insulating film 13, and the l wiring pattern 14 is formed. By doing this, a C-MO8) transistor is completed. Thus created C
-The threshold voltage of the MOS transistor is 0.25 [V] in the P channel transistor.
Therefore, the threshold voltage VTR of the n-channel transistor becomes -0.20 [Y], which makes it possible to match the desired VTR.
なお、本発明はと述した実施例に限定されるものではな
い。例えば、前記合金膜中のＭＯの代りには、ＶＢ族や
ＶＩＢ族の高融点金属を用いてもよい。また、合金膜中
の８１成分は、高ＶＡ族であればよい。また、Ｃ−ＭＯ
Ｓ）ランジスタに限らず、各種のＭＩＳ型半導体装置に
適用できるのは勿論のことである。その他、本発明の要
旨を逸脱しない範囲で、種々変形して実施することがで
きる。Note that the present invention is not limited to the embodiments described above. For example, instead of MO in the alloy film, a VB group or VIB group high melting point metal may be used. Further, the 81 component in the alloy film may be of a high VA group. Also, C-MO
S) Of course, the present invention is applicable not only to transistors but also to various MIS type semiconductor devices. In addition, various modifications can be made without departing from the gist of the present invention.
第１図は本発明の詳細な説明するためのものでＳ ｉ
７Ｍ ｏ原子比とフラットバンド電圧との関係を示す特
性図、第２図（ａｌ〜（ｄ）は本発明の一実施例に係わ
るＣ−ＭＯＳトランジスタの製造工程を示す断面図であ
る。
ｌ・・・シリコン基板１．？−Ｐウェル、３・・・フィ
ールド酸化膜、４°°°ゲート酸化膜、５・・・Ｍｏ
−８１合金膜、６，７・・・レジスト、１１．１２・・
・ソース自ドレイン。FIG. 1 is for detailed explanation of the present invention.
A characteristic diagram showing the relationship between the 7Mo atomic ratio and the flat band voltage. FIGS. ...Silicon substrate 1.?-P well, 3...Field oxide film, 4°°°gate oxide film, 5...Mo
-81 alloy film, 6,7...resist, 11.12...
・Source self-drain.
Claims (6)
のシリコンとの合金膜からゲート電極を構成したＭＩＳ
型半導体装置において、前記合金膜はＩＩＩ Ａ族不純
物及び ゛ＶＡＶＡ族不純物なくとも一種
がドーピングされたものであり、かつと配合金膜からな
る少なくとも２つのゲート電極で不純物ドーピング条件
が異なり該電極の実効的仕事関数が異なるものであるこ
とを特徴とする半導体装置。(1) High melting point metal and more than twice the atomic ratio of the metal
MIS whose gate electrode is made of an alloy film with silicon.
In the type semiconductor device, the alloy film is doped with at least one type of group IIIA impurity and VAVA group impurity, and the impurity doping conditions for at least two gate electrodes made of the mixed gold film are different. A semiconductor device characterized by having different effective work functions.
前記合金膜からなる少なくとも２つのドーピング領域で
不純物種或いは不純物ドーピング量を変えるものである
ことを特徴とする特許請求の範囲第１項記載の半導体装
置。(2) The means for varying the impurity doping conditions include:
2. The semiconductor device according to claim 1, wherein the type of impurity or the amount of impurity doped is changed in at least two doped regions made of the alloy film.
１Ｊ：のシリコンとの合金膜からゲート電極を構成した
ＭＩＳ型半導体装置を製造する方法において、半導体基
板ｔにゲート絶縁膜を介して前記合金膜を被着したのち
、上記合金膜にＴＩＩＡ族不純物及びＶＡ族不純物の少
なくとも１種をドーピングすると共に、該合金膜の少な
くとも２つのゲート電極形成予定領域で不純物ドーピン
グ条件を異ならせ、次いでＬ配合金膜をゲート電極パタ
ーンに加工することを特徴とする半導体装置の製造方法
。(3) Twice the atomic ratio of the high melting point metal and the metal 32
1J: In a method for manufacturing an MIS type semiconductor device in which a gate electrode is formed from an alloy film with silicon, the alloy film is deposited on a semiconductor substrate t via a gate insulating film, and then a TIIA group impurity is added to the alloy film. and at least one type of VA group impurity, and the impurity doping conditions are made different in at least two gate electrode formation regions of the alloy film, and then the L-blended gold film is processed into a gate electrode pattern. A method for manufacturing a semiconductor device.
前記合金膜の少なくとも２つのゲート電極形成予定領域
で不純物種或いは不純物ドーピング量を変えることであ
る特許請求の範囲第３項記載の半導体装置の製造方法。(4) The step of varying the impurity doping conditions @
4. The method of manufacturing a semiconductor device according to claim 3, wherein the type of impurity or the amount of doping of the impurity is changed in at least two regions of the alloy film where gate electrodes are to be formed.
記合金膜に不純物をイオン注入したのち、該合金膜を加
熱処理することである特許請求の範囲第３項又は第４項
記載の半導体装置の製造方法。(5) @The step of doping the compounded gold film with impurities is 1.
5. The method of manufacturing a semiconductor device according to claim 3, wherein the alloy film is heat-treated after ion-implanting impurities into the alloy film.
配合金膜りに不純物を含む絶縁膜を被着したのち、この
絶縁膜及び合金膜を加熱処理して絶縁膜中の不純物を合
金膜中に拡散せしめることである特許請求の範囲第３項
又は第４項記載の半導体装置の製造方法。(6) @The process of doping impurities into the blended gold film is L
Claim 3 or 3, which comprises depositing an insulating film containing impurities on the compounded gold film, and then heat-treating the insulating film and the alloy film to diffuse the impurities in the insulating film into the alloy film. 5. The method for manufacturing a semiconductor device according to item 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57224160A JPS59114868A (en) | 1982-12-21 | 1982-12-21 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57224160A JPS59114868A (en) | 1982-12-21 | 1982-12-21 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59114868A true JPS59114868A (en) | 1984-07-03 |
| JPH053146B2 JPH053146B2 (en) | 1993-01-14 |
Family
ID=16809466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57224160A Granted JPS59114868A (en) | 1982-12-21 | 1982-12-21 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59114868A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0442930A (en) * | 1990-06-06 | 1992-02-13 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| WO2002073700A1 (en) * | 2001-03-02 | 2002-09-19 | National Institute For Materials Science | Gate and cmos structure and mos structure |
| US7098120B2 (en) | 2003-10-30 | 2006-08-29 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices |
-
1982
- 1982-12-21 JP JP57224160A patent/JPS59114868A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0442930A (en) * | 1990-06-06 | 1992-02-13 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| WO2002073700A1 (en) * | 2001-03-02 | 2002-09-19 | National Institute For Materials Science | Gate and cmos structure and mos structure |
| US7091569B2 (en) | 2001-03-02 | 2006-08-15 | National Institute For Materials Science | Gate and CMOS structure and MOS structure |
| US7098120B2 (en) | 2003-10-30 | 2006-08-29 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH053146B2 (en) | 1993-01-14 |
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