JPS59114819A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59114819A
JPS59114819A JP22367482A JP22367482A JPS59114819A JP S59114819 A JPS59114819 A JP S59114819A JP 22367482 A JP22367482 A JP 22367482A JP 22367482 A JP22367482 A JP 22367482A JP S59114819 A JPS59114819 A JP S59114819A
Authority
JP
Japan
Prior art keywords
mark
groove
semiconductor substrate
forming
protective film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22367482A
Other languages
Japanese (ja)
Other versions
JPH0544174B2 (en
Inventor
Hidetake Suzuki
鈴木 秀威
Kinshiro Kosemura
小瀬村 欣司郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22367482A priority Critical patent/JPS59114819A/en
Publication of JPS59114819A publication Critical patent/JPS59114819A/en
Publication of JPH0544174B2 publication Critical patent/JPH0544174B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electron Beam Exposure (AREA)

Abstract

PURPOSE:To prevent the positioning mark from etching even if the protective film on that mark is thin by filling the groove for a mark pattern formed on the semiconductor substrate with a first material of large atomic weight and by forming the protective film consisting of a second material of small atomic weight on said first material in the groove and on the substrate around the groove thereby forming the positioning mark. CONSTITUTION:A photoresist layer 12 is formed on a semiconductor substrate 11 consisting of Si or GaAs and a hole 13 for a predetermined positioning mark pattern is formed by exposure and development. Next, a material of large atomic weight is stuck to the whole surface of the substrate by deposition or the like, thereby forming a mark 15 in a groove 14 and a film 16 on said photoresist layer 12. Then the photoresist layer 12 is removed by a proper solvent and simultaneously the film 16 on the layer 12 is removed. Next, a material of smaller atomic weight than that of the mark 15 is formed by coating or the like on the mark 15 and the substrate 11 around the mark 15, as a protective film 17.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明は、半導体装置の製造方法に関するものであシ、
より詳細に述べるならば、電子ビーム露光のだめの位置
合せマークの形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical field of the invention The present invention relates to a method for manufacturing a semiconductor device.
More specifically, the present invention relates to a method of forming alignment marks for electron beam exposure.

(2)技術の背景 半導体装置、特に、LSIなどにおいては高集積度化の
ためにパターン寸法の微細化が図られ、そのだめに電子
ビーム露光技術(電子ビームリソグラフィ技術)が採用
されるようになってきた。電子ビームで描画する際には
位置合せが非常に重要であり、位置合せマークの検出を
正確に行なう必要ある。一般的に位置合せマークにはウ
ェハマークとテップマークとがあり、比較的大きいウェ
ハマークは半導体ウェハの外周近くに形成され、ウェハ
の取付は誤差およびウェハの伸縮を測定するのに役立ち
、一方チツノマークは各チップごとに形成され、ビーム
とマークとの相対位置誤差および回転誤差を検出するに
役立っている。
(2) Background of the technology In semiconductor devices, especially LSIs, pattern dimensions have become smaller in order to increase the degree of integration, and as a result, electron beam exposure technology (electron beam lithography technology) has been adopted. It has become. When writing with an electron beam, alignment is very important, and it is necessary to accurately detect alignment marks. Generally, alignment marks include wafer marks and tip marks, relatively large wafer marks are formed near the outer periphery of the semiconductor wafer, and wafer mounting is useful for measuring errors and wafer expansion and contraction, while tip marks is formed for each chip and serves to detect relative positional errors and rotational errors between the beam and the mark.

(3)従来技術と問題点 位置合せマークからのSAのよい反射信号を得るために
、原子量の比較的大きな材料でできたマークを半導体基
板(ウェハ)上に形成することが行なわれている。この
場合の位置合せマークの形成工程を第1図ないし第4図
を参照して説明すると、まず、第1図に示すようにSi
又はGaAsの半導体基板1の上にマークパターンを有
するホトレノスト層2を形成する。次に、マーク材料で
ある金属、例えばチタン(TI)および金(Au) 、
を(連続)蒸着などで全面に付着させて金層マーク3お
よび金属膜4を形成する。有機溶材を用いてホトレジス
ト層2を除去すると同時にその上の金属膜4を除去(リ
フトオフ)して、第2図に示すように金属マーク3を半
導体基板l上に形成する。
(3) Prior Art and Problems In order to obtain a reflection signal with good SA from an alignment mark, marks made of a material with a relatively large atomic weight are formed on a semiconductor substrate (wafer). The process of forming alignment marks in this case will be explained with reference to FIGS. 1 to 4. First, as shown in FIG.
Alternatively, a photorenost layer 2 having a mark pattern is formed on a GaAs semiconductor substrate 1. Next, the metal that is the mark material, such as titanium (TI) and gold (Au),
The gold layer mark 3 and the metal film 4 are formed by (continuous) depositing the metal on the entire surface by evaporation or the like. The photoresist layer 2 is removed using an organic solvent and at the same time the metal film 4 thereon is removed (lifted off) to form a metal mark 3 on the semiconductor substrate l as shown in FIG.

そして、この金属マーク3がその製造工程におけるエツ
チング処理でエツチングされないように保護膜5、例え
ばCVD法による二酸化珪素(Si0,2)膜によって
このマーク3を覆う(第3図)。このような場合保護膜
5を金属マーク3上に形成する際に、段差部での形状(
ステップカバレジ)が問題となシ、第4図に示すように
ピーンホール6あるいは金属マークに達する接触面7が
生じることがある。後工程でエツチング処理を行なった
ときにエツチング剤がピーンホール又は接触面を通して
金属マーク3に達してこの金属マーク3をエツチングす
ることになる。そのだめに、金属マーク3の一部が除さ
れてエツジ形状が変化してしまいマーク検出信号のS/
Nが低下したり、マーク検出位置がずれてしまうことに
彦る。
Then, to prevent the metal mark 3 from being etched in the etching process in the manufacturing process, the mark 3 is covered with a protective film 5, for example, a silicon dioxide (Si0,2) film formed by the CVD method (FIG. 3). In such a case, when forming the protective film 5 on the metal mark 3, the shape (
Step coverage (step coverage) is a problem, and a contact surface 7 reaching a peen hole 6 or a metal mark may occur as shown in FIG. When an etching process is performed in a subsequent process, the etching agent reaches the metal mark 3 through the peenhole or the contact surface and etches the metal mark 3. Unfortunately, part of the metal mark 3 is removed and the edge shape changes, causing the S/S of the mark detection signal to change.
This may result in a decrease in N or a shift in the mark detection position.

電子ビームによる位置合せマークの反射信号を明瞭に得
るためにはマークを厚くするが良く、また反射信号を低
下させないためにはマーク上の保護膜を薄くしたほうが
良い。しかしながら、保護膜を薄くすると段差部にてピ
ーンホールなどの欠陥が保護膜に発生して・マーク形状
がエツチングによシ変化してしまうことがある。
In order to clearly obtain a signal reflected from the alignment mark by the electron beam, it is better to make the mark thicker, and in order not to reduce the reflected signal, it is better to make the protective film on the mark thinner. However, if the protective film is made thinner, defects such as peen holes may occur in the protective film at the stepped portions, and the mark shape may change due to etching.

(4)発明の目的 本発明の目的は、位置合せマーク上の保護膜が薄くても
そのマークがエツチングされないようにすることである
(4) Purpose of the Invention The purpose of the present invention is to prevent the mark from being etched even if the protective film on the alignment mark is thin.

本発明の別の目的は、正確かつ良好なSAの反射信号を
得ることのできる位置合せマークを有する半導体装置の
製造方法を提供することである。
Another object of the present invention is to provide a method for manufacturing a semiconductor device having alignment marks that can obtain accurate and good SA reflection signals.

(5)発明の構成 上述の目的は、電子ビーム露光を行なう前に、工程(7
)〜汐):半導体基板にマークツリーンの溝を形成する
工程;(イ)この溝を原子量の大きな第1の材料で埋め
る工程;および(つ)この溝内の第1の材料およびその
周囲の半導体基板の上に第1の材料より原子量の小さな
第2の材料からなる保護膜を形成する工程;によって位
置合せマークを形成する工程を有する半導体装置の製造
方法によって達成される。
(5) Structure of the invention
)~shio): A process of forming a mark tree groove in a semiconductor substrate; (a) a process of filling this groove with a first material having a large atomic weight; and (ii) a process of filling the first material in this groove and its surroundings. forming a protective film made of a second material having a smaller atomic weight than the first material on a semiconductor substrate; and forming an alignment mark.

(6)発明の実施態様 以下、添付図面を参照して本発明の実施態様例によって
本発明の詳細な説明する。
(6) Embodiments of the invention Hereinafter, the present invention will be described in detail by way of embodiments of the invention with reference to the accompanying drawings.

第5図に示すように、Sl又はGaA、sの半導体基板
(ウェハ)11上にホトレジスト層12を形成し、露光
・現像により所定の位置合せマークパターンの孔13を
形成する。このホトレジスト層12の孔13内に表出し
た半導体基板11をエツチングしてマークツ4ターンの
溝14(例えば、深さ0.4〔μm))を形成する。次
に、原子量の大きな材料、例えば、チタン、タングステ
ン、モリブデン、白金、金又はこれらのシリサイドを蒸
着、スノ4 ツタリングなどで第6図のように全面に付
着させて、溝14内にマーク15をそしてホトレジスト
層12上に膜16を形成する。例えば、0.1μm厚の
チタン層および0.3μm厚の金層を連続蒸着すること
で溝14を埋めてマーク15を形成する。
As shown in FIG. 5, a photoresist layer 12 is formed on a semiconductor substrate (wafer) 11 of Sl, GaA, or S, and holes 13 having a predetermined alignment mark pattern are formed by exposure and development. The semiconductor substrate 11 exposed in the hole 13 of the photoresist layer 12 is etched to form a groove 14 with four turns of marks (for example, depth 0.4 μm). Next, a material with a large atomic weight, such as titanium, tungsten, molybdenum, platinum, gold, or a silicide thereof, is deposited on the entire surface by vapor deposition or slatting, as shown in FIG. 6, and a mark 15 is formed in the groove 14. A film 16 is then formed on the photoresist layer 12. For example, the grooves 14 are filled and the marks 15 are formed by successively depositing a titanium layer with a thickness of 0.1 μm and a gold layer with a thickness of 0.3 μm.

そして、ホトレジスト層12を適切な溶剤で除去すると
、同時にその上の膜16を除去(リフトオフ)すること
ができる(第7図)。このようにして半導体基板11に
マーク15を埋め込むのでほぼ平坦となる。マーク15
が多少の凹みあるいは出つ張シとなっても、従来の場合
と比べると、半導体基板11からの高低差ははるかに小
さくすることができる。保護膜17(第8図)としてマ
ーク15の材料よυも原子量の小さい材料、例えば二嘴
化珪素、多結晶シリコン、窒化珪素、アルミナイドライ
ド又はポリイミド樹脂を、化学的気相成長法(CVD法
)、塗布などによってマーク15上およびその周囲の半
導体基板11上に形成する。
Then, when the photoresist layer 12 is removed with a suitable solvent, the film 16 thereon can be removed (lifted off) at the same time (FIG. 7). Since the marks 15 are embedded in the semiconductor substrate 11 in this manner, the semiconductor substrate 11 becomes substantially flat. mark 15
Even if there is some dent or protrusion, the difference in height from the semiconductor substrate 11 can be made much smaller than in the conventional case. As the protective film 17 (FIG. 8), a material having an atomic weight smaller than that of the mark 15, such as diprotic silicon, polycrystalline silicon, silicon nitride, aluminide, or polyimide resin, is formed by chemical vapor deposition (CVD). ) is formed on the mark 15 and the semiconductor substrate 11 around the mark 15 by coating or the like.

例工ば、CVD法による二酸化珪素(厚さ0.1μm)
の保護膜17を形成すれば、マークに段差部がないので
ビーンホールなどの欠陥が生じることもなく後工程での
エツチング処理時にマーク15がエツチングされること
はない。このように形成したマーク15を電子ビーム露
光前に検出して位置合せを行なってから電子ビーム露光
を行ない、所定の微細パターンを得ることができる。そ
して通常の製造にしたがって半導体装置を作る。
For example, silicon dioxide (thickness 0.1 μm) made by CVD method
If the protective film 17 is formed, there will be no step portion in the mark, so defects such as bean holes will not occur, and the mark 15 will not be etched during the etching process in the subsequent process. The mark 15 thus formed is detected and aligned before electron beam exposure, and then electron beam exposure is performed to obtain a predetermined fine pattern. Then, a semiconductor device is manufactured according to normal manufacturing.

(7)発明の効果 本発明に係る製造方法では、位置合せマークの厚さを半
導体基板に形成する溝の深さおよびマーク材料の付着厚
さによって適切に決めることができ、しかもマークおよ
び半導体基板表面を平坦にすることができるので保護膜
に段差に基因する欠陥がなく膜厚を薄くすることができ
る。したがって、マーク厚さが適切であり、保護膜の厚
さは薄くかつ、マーク形状は所定通りであるので、正確
でS/[’Jの良い反射信号が得られる。本発明に係る
製造方法で形成した位置合せマークは電子ビーム描画で
微細加工を行なう半導体装置(MO8IC、バイポーラ
I C、GaAs FETおよびそのIC,ローノイズ
HEMT 、 HEMTICなど)の製造に利用される
(7) Effects of the Invention In the manufacturing method according to the present invention, the thickness of the alignment mark can be appropriately determined by the depth of the groove formed in the semiconductor substrate and the thickness of the mark material adhered to the mark and the semiconductor substrate. Since the surface can be made flat, there are no defects in the protective film due to steps, and the film thickness can be reduced. Therefore, since the mark thickness is appropriate, the protective film is thin, and the mark shape is as specified, an accurate reflection signal with good S/['J can be obtained. The alignment marks formed by the manufacturing method according to the present invention are used in the manufacturing of semiconductor devices (MO8 ICs, bipolar ICs, GaAs FETs and their ICs, low-noise HEMTs, HEMTICs, etc.) that are microfabricated by electron beam lithography.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第3図は従来の位置合せマーク形成工程を説明
する半導体装置の部分断面図であり、第4図は、従来の
位置合せマーク形成での欠陥を説明する半導体装置の部
分断面図であり、第5図〜第8図は本発明に係る半導体
装置の製造方法での位置合せマーク形成工程を説明する
半導体装置の部分断面図である。 1・・・半導体基板、3・・・金属マーク、5・・・保
護膜、11・・・半導体基板、12・・・ホトレジスト
層、14・・・溝、15・・・マーク、17・・・保護
膜。 特許出願人 富士通株式会社 特許出願代理人 弁理士 青 木   朗 弁理士西舘和之 弁理士 内 1)幸 男 弁理士 山 口 昭 之 第1図 第4百!
1 to 3 are partial sectional views of a semiconductor device illustrating a conventional alignment mark forming process, and FIG. 4 is a partial sectional view of a semiconductor device illustrating defects in conventional alignment mark formation. FIGS. 5 to 8 are partial cross-sectional views of a semiconductor device for explaining the alignment mark forming step in the semiconductor device manufacturing method according to the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 3... Metal mark, 5... Protective film, 11... Semiconductor substrate, 12... Photoresist layer, 14... Groove, 15... Mark, 17... ·Protective film. Patent applicant Fujitsu Limited Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney 1) Yukio Patent attorney Akira Yamaguchi Figure 1 Figure 400!

Claims (1)

【特許請求の範囲】 1、 電子ビーム露光を行なう前に、下記工程(7)〜
り); (7)半導体基板にマークパターンの溝を形成する工程
; (イ)この溝を原子量の大きな第1の材料で坤める工程
;および (つ) この溝内の第1の材料およびその周囲の前記半
導体基板の上に前記第1材料より原子量の小さな第2の
材料からなる保護膜を形成する工程;によって位置合せ
マークを形成する工程を有することを特徴とする半導体
装置の製造方法。 2、前記第1の材料がチタン、タングステン、モリブデ
ン、白金、金又はこれらのシリサイドであることを特徴
とする特許請求の範囲第1項記載の製造方法。 3、前記第2の材料が二酸化珪素、多結晶シリコン、窒
化珪素、アルミナイドライド又はポリイミド樹脂である
ことを特徴とする特許請求の範囲第1項記載の製造方法
[Claims] 1. Before performing electron beam exposure, the following steps (7) to
(7) Forming a mark pattern groove in the semiconductor substrate; (A) Filling this groove with a first material having a large atomic weight; and (1) Filling the groove with the first material and forming a protective film made of a second material having a smaller atomic weight than the first material on the semiconductor substrate surrounding the semiconductor substrate; forming an alignment mark; a method for manufacturing a semiconductor device; . 2. The manufacturing method according to claim 1, wherein the first material is titanium, tungsten, molybdenum, platinum, gold, or a silicide thereof. 3. The manufacturing method according to claim 1, wherein the second material is silicon dioxide, polycrystalline silicon, silicon nitride, aluminide, or polyimide resin.
JP22367482A 1982-12-22 1982-12-22 Manufacture of semiconductor device Granted JPS59114819A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22367482A JPS59114819A (en) 1982-12-22 1982-12-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22367482A JPS59114819A (en) 1982-12-22 1982-12-22 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS59114819A true JPS59114819A (en) 1984-07-03
JPH0544174B2 JPH0544174B2 (en) 1993-07-05

Family

ID=16801864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22367482A Granted JPS59114819A (en) 1982-12-22 1982-12-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59114819A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58128A (en) * 1981-06-11 1983-01-05 ウエスタ−ン・エレクトリツク・カムパニ−・インコ−ポレ−テツド Method of producing integrated circuit
JPS5856334A (en) * 1981-09-29 1983-04-04 Fujitsu Ltd Positioning mark

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58128A (en) * 1981-06-11 1983-01-05 ウエスタ−ン・エレクトリツク・カムパニ−・インコ−ポレ−テツド Method of producing integrated circuit
JPS5856334A (en) * 1981-09-29 1983-04-04 Fujitsu Ltd Positioning mark

Also Published As

Publication number Publication date
JPH0544174B2 (en) 1993-07-05

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