JPS5911458A - Logical simulator - Google Patents

Abstract

PURPOSE:To reduce the simulation time, by classifying a logical device to be tested into logical blocks in the order of operation, performing the pipeline processing for the simulation of the logical blocks and attaining the classification with serial processing in the order of operation. CONSTITUTION:The operation of IC simulation classified with level numbers consists of four operations. An input pin data is read out from a status memory (SM) 7 in the 1st operation, and the simulation is attained at an IC simulator (SIM) 9 and the output pin data change position information is formed. The 2nd operation is an operation forming an output pin number from the output pin data change position information. The 3rd operation is an operation reading out the connected input pin number and the output pin number of itself from a connected memory (CM) 21 out of the output pin number. The 4th operation is an operation to revise the input pin data and output pin data corresponding to the input and output pin number. These operations are done in parallel at the same time.

Description

[Detailed description of the invention] The present invention relates to logic simulators.

When developing a logic device that uses a large number of integrated circuits of various types, if you discover a logic design error bt after actually manufacturing the logic device and conducting an operation test, it will be difficult to modify the circuit. This will result in significant development delays and increased costs. LSI.

With the use of custom LSIs and the increasing scale of logic devices, early detection of the logic design unit υ has become an even more urgent issue.

Logic simulators have traditionally been used for early detection of the above-mentioned logic design problems.The logic simulator is used to perform the same operation as the logic device to be tested, and before manufacturing the logic device. The objective is achieved by inspecting the logical design.

However, with conventional logic simulators, most of the work is done by software, and as the logical scale of the logic device to be tested becomes large, sequential processing by software requires 100% of simulation time. The disadvantage is that it is too large to be put to practical use.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic simulator that eliminates the drawbacks of the above-mentioned conventional devices and significantly reduces simulation time.

The device of the present invention is a logic simulator that performs a device operation consisting of a plurality of logic blocks each given a predetermined level number and classified according to the number. a first storage means for storing logic state values at input terminals and output terminals and logic block type information; and a logic state value at an input terminal of a logic block specified from the first self-storage means and logic block type information. individual logic block simulation means for reading type information, simulating a logical operation specified by the type information of the logic block, and outputting a logic state value at an output terminal of the logic block in response; and the individual logic block simulation means. A comparison end signal is generated by comparing the logic state value at the output terminal of the designated logic block supplied from the output terminal with the logic state value at the output terminal of the designated logic block stored in the first storage means. Output logic state value change terminal number generation means for generating a terminal number of an output terminal of the specified logic block whose logic state value has changed at the same time as the logic state value has changed;
and the input terminal number of the logic block to which the terminal corresponding to the output terminal number is connected, according to the output terminal number of the specified logic block supplied from the terminal number generation means, and the input terminal number of the logic block to which the terminal corresponding to the output terminal number is connected. connection destination reading means for reading out the output terminal number of the logic block from the second storage means; and the input terminal number of the connection destination logic block supplied from the connection destination reading means and the output of the specified nine logic blocks. updating means for updating a logic state value at a corresponding input terminal of the connected logic block of the first storage means and a corresponding output terminal of the specified logic block according to a terminal number; and supplying the comparison end signal. a detection delay means for detecting the comparison end signal corresponding to a predetermined logic block in response to the signal, and delaying the comparison end signal by a predetermined time only when the comparison end signal is detected, and simply passing the comparison end signal at other times; and address generation means for generating a designation signal for designating a logic block whose logic state value is to be read from the first storage means in the order of the level numbers in response to a comparison end signal supplied from the means.

Next, the present invention will be explained in detail with reference to the drawings.

An example will be explained in which a total of n integrated circuits (hereinafter referred to as ICs) of m types (m is a natural number) are used in a logic device to be tested (n is a natural number).

Numbers (hereinafter referred to as IC position numbers) are assigned to the ICs used in order from No. 1 to No. 1 according to the signal flow of the logic device. That is, the signal always flows from the IC with the smaller IC position number to the IC with the larger IC position number.

The input signal of each IC is determined by the input signal to the logic device being supplied via several ICs, and the maximum value of the number of ICs through which each input signal to one IC has passed. Considering k (hereinafter referred to as a level number) as an index when determining the input signal to the IC, all ICs in the logic device are classified according to this level number.

That is, all ICs in a logical device are specified by IC position numbers, the order of operation is defined by level numbers, and the functions are defined by types.

FIG. 1 is a block diagram of an example of a logic device to be tested.

The logic device 1 uses eight ICs ranging from IC100 to IC800, and performs logical operations using the wiring connections shown in the figure. The IC position number is prefixed with a number from 100 to 800 according to the signal flow. Also, the level numbers are IC100 and IC2
00 and IC300 are 1°IC400! and IC50
0 is 2. IC600 and IC700 are 3. IC800
becomes 4. The type of IC cannot be determined just from the wiring, but Figure 1 shows IC100, IC500, and IC.
200 and IC400, IC300 and IC700, IC6
00 and IC800 are the same type of ICs, and a total of four types of logic devices using Ct- are illustrated.

Figure vX2 is a block diagram of one embodiment of the present invention.

One embodiment of the present invention is an IC whose input data has changed.
A first-in, first-out buffer (FIFO) 2 that temporarily stores the C position number and the pin number where the input data has changed as data and outputs the stored data in order, and a switching circuit (MPX) 5 that selects an address signal. , status data that uses the IC position number as an address and indicates the state of the IC at that address, i.e., the type of IC and the logical value of the pin at the bit position corresponding to the pin number (for example, the first
The logical value of the bin is “1”, the logical value of the second bin is “0”, etc.
・The 11th bit of the data is “1”.

The 12th bit is "o" (old, etc.), and a flag (F) indicating the position of the IC among the ICs with the same level number (the highest IC among the ICs belonging to the same level number). “1” if the position number is large; otherwise “0”)
a state memory (SM) 7 for storing the data, and an inverting circuit (REV) 4 for inverting the state data of the specified nine capins;
A latch circuit that temporarily stores read data from 8M7 (
LAT) 8, and an IC simulator (SIM) 9 that gives a logic value to each input bin and outputs a logic value to each output bin for each of the ICs included in the logic device to be tested.
Latch circuit (DAT) 1 that temporarily stores output bin data
0, the output bin data that has changed in response to the change in the input bin data, and the output bin data before the change in the input pin data are compared for each corresponding bin, and output bin data change position information,
That is, a logic "1" is output to the pit position corresponding to the bin where the data has changed, a logic "0" is output to the pit position corresponding to the bin that has not changed, and when the comparison is completed, a logic "1" is output as the comparison end signal. A comparison circuit (C, -0, M
) 12, a detection circuit 11 that delays and outputs a logic "1" input signal supplied when F=1 is detected by inspecting the IC state data, and a drive supplied from the detection circuit 11. At the signal! l) An address signal generation circuit (CTR) 13 that generates an address signal (IC position number) to 8M7 and is initialized when the number of drive signal receptions reaches a preset constant value, and an IC position number. a first-in, first-out buffer (FIFO) 15 that temporarily stores and output bin data change position information as data and outputs the data stored first in order; and an inversion circuit (REV) that inverts the output bin data change position information of a designated output bin. )16
and 2 supplied from FIFOl 5 and gEvi6
Switching circuit (MPX) 17 for selecting one of the two input signals
and a latch circuit (LAT) that temporarily stores input data.
18, a bin number generation circuit (EDR) 19 that generates a corresponding output pin number from the output bin data change position information, temporarily stores the IC position number and the output bin number as data, and stores the IC position number and the output bin number in order from the first stored data. A first-in first-out buffer (FIFO) 20 to output, an IC position number and the corresponding output bin number are used as address signals, and at that address, other IC position numbers connected to the corresponding output bin, their bin numbers, and the corresponding IC position numbers are output. It includes a connection memo IJ (CM) 21 that stores a bin number, a switching circuit (MPX) 22 that selects an address signal to 0M21, and a switching circuit (MPX) 23 that selects output data from 0M21. Next, the operation of this embodiment will be explained from the initial setting.

, 8M7 are initialized with the data of each IC used in the logic device under test, that is, the flag F, the type of IC, the initial logic value f of each bin, and the I of the IC from MPX6.
The C position number is input as an address signal and stored in 8M7. The address corresponding to IC position number 0 stores the output logic value of the logic device under test.

The SIM 9 is also initialized so that all types (m types in this case) of ICs constituting the logic device under test can be shimmy-rated. For this purpose, m types of ICs themselves may be prepared, a general-purpose logic circuit may be used that uses a gate array to simulate each IC, or an input/output pin for each IC may be used. Ping memory can also be used. In any case, perform these initial settings.

0M21 is initialized based on the connection between each IC bin of the logic device under test. In other words, the IC position number, the output pin number of the IC, and the total address signal include the position number of another IC that is connected to the output bin, its input bin number, the IC position number, and the output pin number at that address. is stored as data. Considering the case where there are multiple input pins of other ICs connected to the output pin, 0M21
Two pieces of data are retrieved with one access to , the first data is used for the pin number, and the second data is used for the pin number or next address pointer.

Therefore, there are three types of combinations of data retrieved by one access to 0M21: 1 connection, 2 connections, and 1 connection + next address pointer. ”,“
11''. Also, connection data for the data input terminal of the logic device under test is stored corresponding to IC position number 0.

The CTRI 3 is initially set to a value equal to the number of ICs (n in this case) used in the logic device under test as the above-mentioned constant value.

Next, an explanation will be given of the operation of simulating data at the data output terminal of the logic device under test that corresponds to the data applied to the data input terminal of the logic device under test.

The data given to the data input terminal of the logic device under test is compared for each terminal with the data of the same manual terminal currently stored at the address corresponding to IC position number 0 of SM7, and the data is compared for the large sword terminal whose data has changed. input the IC position number 0 and the corresponding input terminal number to the FIFO 20 in order to rewrite the data stored in 8M7.

The IC position number 0 supplied to FIFO20 and the terminal number where the data changed are MPX22'! r is supplied to the CM 21 as an address signal, and the IC position number and input bin number of the terminal to which the data has changed, as well as the IC position number and input terminal number, are read out and supplied to the FIFO 2 via the MPX 23.

The IC position number supplied to FIFO2 is MPX6t-
Then, it is supplied to 8M7 as an address signal, and the data stored in the corresponding address is read out and sent to REV.
4. In REV4, the input terminal number of the logic device under test supplied from FIFO2 and the I
The terminal corresponding to the input bin number of C inverts the bit information of the bin data and stores it in the corresponding address of 8M7, and performs the above operation on all the data stored in 6FIF02 and inputs it to the logic device under test. Can write data and corresponding input data of the connected IC.

“Level O operation” that continues the previous operation to the initial setting
It is called. Due to the operation at level O, the input data of the IC with novel number 1 is determined by the change in the input data to the logic device under test.

A manually supplied activation signal then causes the CTR 13 to
The address signal corresponding to C position number 1 is supplied to MPX6f and then to 8M7, and the status data of the IC position number stored at the address is read out and temporarily stored in LAT8. The IC type and power bin data stored in LAT8 are supplied to SIM9, and the IC type information is transferred to SIM9.
The simulation of the IC corresponding to position number 1 is SIM
9 and the resulting output bin data is SI
It is supplied from M9 to LATIO and temporarily stored. L.A.T.
The output bin data of IO is fed to C0M12 and C0M
In step 12, each bin is compared with the pre-simulation output bin data supplied from LAT8, and a logic "1" is assigned to a bin position where the data has changed, and a logic "0" is assigned to a bin position where the data has not changed. The mold/data change position information is generated and stored in the FIFO 15 together with the IC position number from the CTR 13. For example, the output bin data before simulation is "0110001010" and the output bin data after simulation is "1011110".
100”, the output bin data change position information is 11
01111110''.

COMI 2 is output bin data change position information IPIFO
At the same time, the detection circuit 11 is supplied with the logic "1" which is the comparison end signal.

Now, suppose that the data stored in LAT8 is F~1 (if F=1, which will be explained later), the logic "1" supplied from C0M12 is immediately supplied to CTR13, and CTR1
3 generates the next address signal, that is, the address signal corresponding to IC position number 2, and supplies it to 8M7 through MPX5=i, reads out each data of the IC of IC position number 2, and similarly to the IC of the above-mentioned IC position number. Perform shimmy reciprocation with SIM9 and output bin data change position information as PIFO
15. In this way, when the shimmy target of the last IC belonging to the group with level number 1, that is, the IC with the largest IC position number (F=1) is completed, logic "1" is supplied from C0M12 to the detection circuit 11. Then, the detection circuit 11 has already detected that F of the data stored in LAT8 is 1, so C
The supply of logic "1" to TR13 is delayed for a certain period of time.

During this time, the input pin data of these connection destinations and the own output bin data are updated in response to changes in the output pin data of the IC with level number 1, which will be described below.

The IC position number and output pin data change position information stored in FIFO15 are temporarily stored in LAT13 via Δ(PX17, and the first logic ``'1'' bit position in the output pin data change position information is detected in EDRI9. death,
An output pin number corresponding to the changed data is generated from the position information, and the IC position number and output bin number are stored in the FIFO 20 as data. On the other hand, the output pin data change position information of LAT18 is supplied to REVI 6, which inverts the information at the position specified by the output bin number supplied from EDRI9 to REVI6, and this data = iMPX
17 to the LAT 18, and the EDRI 9 generates an output bin number corresponding to the changed data in the same manner as described above. All output bin numbers whose output data has changed are generated and stored in the FIFO 20.

Thereafter, similar operations are performed for the ICs belonging to level number l until there is no more data stored in the FIFO 15.

The IC position number and output pin number stored in the FIFO 20 are supplied as an address signal to 0M21 via MPX22, and from 0M21, the IC position number and input pin number of other ICs connected to the output pin and The IC
The position number and blade pin number are read out and supplied to the MPX23. Two sets of data are supplied from 0M21 to MPX23 via connection lines 75 and 76, respectively. F3
When is “01”, that is, when there is one connection destination, MP
X23 connects connection lines 75 and 77 and supplies the IC position number, input pin number, and eFIFo 2, and F3 is "10".
In other words, when there are two connection destinations, the MPX 23 connects the connection lines 75 and 77 and supplies the first set of IC position number, input pin number, and t-FIFO 2, and then connects the connection lines 76 and 77. and supplies the second set of IC position number and input pin number to FIFO2, and when F3 is "11", that is, when the read data is one connection destination and next address pointer, MPX23 connects 875 and 77. Connect the IC position number, input pin number and '1F
Supply to IF02, then connect to MPX22 via connection line 7
6 and 74 are connected to create the next address pointer kcM.
21 to continue reading the connection destination data. The I
The same applies to the C position number and output bin number.

Thereafter, similar operations are performed for the ICs belonging to level number 1 until there is no more data stored in the FIFO 20.

The IC position number stored in FIFO2 is supplied to 8M7 as an address signal via MPXG, and the input pin data of the IC stored at the specified address of 8M7 is read out and supplied to REV4. The information on the position specified by the input pin number supplied from the 8M7 is inverted and supplied to the 8M7 to update the input pin data of the IC. The output bin data of the IC position number simulated by the IC simulator is updated in the same way. Hereafter, the above operation is repeated until there is no data stored in FIFO2, and the data of the IC belonging to the group with level number 1 changes, and the data of all the connection destinations of the ratio output pin and the IC of the group with level number 1 are changed. Update the output bin data of.

The operations up to this point are referred to as "level 1 operations" following the "level O operations." 6 level 1 operation” is a simulator for all ICs belonging to the level number 1 group!
1) is performed and according to the connection destination information obtained from CM21, f
The output bin data of the IC in i8M7 and the input pin data of the connection destination are also updated.

COMI for the last IC in the group with level number 1
After a certain period of time sufficient to complete the above-mentioned "level 1 operation" after receiving the logic "1" from the CTTiB2, the detection circuit 11 supplies the logic "1" to the CTTiB2 and outputs the logic "1" to the next IC.
The address signal 'fcMPX6'fc corresponding to the position number (IC belonging to the group of level number 2) is supplied to 8M7. Thereafter, the same operation as the above-described "level 1 operation" performed on the level number 1 group is performed on the level number 2 group. This is "level 2 operation."

In this way, level swamp operations are performed from level 2, and at the end of the final level p operation, all ICs are simulated in response to changes in the input signal to the logic device under test, and the results are shown in 8M7. The input/output data of the logic device under test is stored at the address corresponding to IC position number 0 of 8M7. CTRL3 receives the last logic "1" from the detection circuit 11, and the logic "1" is applied to CTRL3.
'' reaches the preset value n (the number of ICs used in the aforementioned logic device under test), the initial settings are made and preparations are made for the next simulation.

The above explanation is a simulation of changes in the input data of the logic device under test. However, for testing purposes, a simulation is performed in which only the input bin data or output bin data of the IC with the logic device under test is changed. In this case, in this embodiment, in response to a change in input bin data, it is sufficient to input the relevant IC position number and power bin number to FIFO 2, and in response to a change in output bin data, input the relevant IC position number in FIFO 20. The simulation can be performed by inputting the number and the output bin number.

The above-mentioned level k (k=1-p) operation consists of the following four operations. The first operation is to read input bin data from 8M7 and perform simulation with SIM9 to create output bin data change position information.The second operation is to create an output bin number from output bin data change position information. The third operation is the operation of reading out the connected input bin number and the own output bin number 'icM21 from the output bin number, and the fourth operation is the operation of reading the corresponding input bin data and output pin data from the input bin number and output bin number. This is an update operation.

In this embodiment, these four operations are performed in parallel. In other words, although there is a slight time lag, for example, considering a certain point in time, the first action is for the IC at position number p of 10, and the second action is for the IC at position number C.
For the IC at p-1), the third operation is to change the IC position number (
For the IC of p-2), the fourth operation is the IC position number (
FIFO2, 8M7. There are FIFO15 and FIFO20. So-called pipeline processing is performed. Therefore, the processing time can be reduced to a certain extent compared to a logic simulator that performs serial processing.

The simulation of ICs belonging to the same level number is performed by pipeline processing as described above, and in order to move on to the simulation of ICs belonging to the next level number, the above-mentioned detection of F is performed, and the simulation of ICs belonging to the next level number is performed. IC
Since the simulation operation is performed after all of the input data has been determined, erroneous simulations due to uncertain input data will not occur.

In this embodiment, an ICi is used as a logical configuration unit. However, the present invention is not limited to this, and the present invention can be applied by dividing a logical device under test into several logical blocks including a plurality of ICs. In the case of a logic device under test such as a custom LSI, a custom LSI can be used.
The present invention can also be applied by dividing the logical blocks into one Cf and a plurality of logical blocks.

In this embodiment, the level number to which an IC belongs is set to the maximum value among the number of next ICs through which the input signal to the IC is passed, but the present invention is not limited to this. After the input signal is determined, the relevant I
It is only necessary to carry out the process within the minimum time required for all input signals of any one of the ICs to which the output signal of C is to be determined.

In other words, the level number of the IC is greater than or equal to the maximum value of the number of C's that the input signal to the IC passes through, and the level number of the IC is
It is sufficient if the number is less than or equal to the minimum value among the maximum values of the number of ICs through which the input signal of each IC to which the output signal is directed has passed. Using this, I that belong to the same level number
It is possible to equalize the number of C's.

As described above, in the present invention, a logic device under test is divided into a plurality of logic blocks, each logic block is classified in the order of operation according to the determination of the input signal or output signal of each logic block, and the logic within each classification is divided into multiple logic blocks. Pipeline processing is performed for block simulation, and each classification is serially processed in the order of operation, which has the effect of significantly shortening the simulation time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a logic device, and FIG. 2 is a block diagram of an embodiment of the present invention. In the figure, =h=;=6. 17. 22. 23
...Switching circuit (MPX), 2, 15.20...
...First-in first-out buffer (FIFO), 4.16
...Reversing circuit (REV), 7...State memory (SM), 8,10゜18...Latch circuit (LAT), 9...IC Simulator (S
IM), 11...detection circuit, 12...
Comparison circuit (COM), 13...address signal generation circuit (CTR), 19...bin information generation circuit (ED), 21...connection memory (CM), 1
00-800...IC, l-Satte-...Logic device. Figure 2

Claims (4)

[Claims] (1) In a logic simulator device consisting of a plurality of logic blocks each given a predetermined level number and classified according to the number, at least one input terminal and an output terminal provided in each logic block. a first storage means for storing logic state values and logic block type information at the input terminals of the next logic block specified from the first storage means; individual logic block simulation means 717 for simulating the logic operation specified by the type information of the logic block v-} and outputting the logic state value at the output terminal of the logic block in response; a logic state value at the output terminal of the designated logic block stored in the first storage means and a logic state value at the output terminal of the designated logic block stored in the first storage means to generate a comparison end signal; Output logic state value change terminal number generation means for generating a terminal number of an output terminal of the designated logic block whose logic state value has changed; and second storage means for storing connection information between the respective logic blocks; According to the output terminal number of the specified logic block supplied from the terminal number generation means, the input terminal number of the logic block to which the terminal corresponding to the output terminal number is connected and the output terminal of the specified logic block. connection destination reading means for reading out the number from the second storage means; and the input terminal number of the connection destination logic block and the output terminal number of the specified logic block supplied from the connection destination reading means. updating means for updating a logic state value at a corresponding input terminal of the connected logic block of the first storage means and a corresponding output terminal of the specified logic block; a detection delay means for delaying the comparison end signal by a predetermined time only when the comparison end signal corresponding to the logical block is detected, and for otherwise simply passing the comparison end signal; and a comparison end signal supplied externally or from the detection delay means. 1. A logic simulator characterized in that the logic simulator further comprises address generation means for generating all designation signals in the order of the level numbers for specifying a logic block whose logic state value is to be read from the first storage means. (2) The level number given to each logic block is determined by the maximum (maximum number of routes) of the number of logic blocks (number of routes) through which each human input signal that arrives at each input child of the logic block goes through. (1) above, and less than or equal to the minimum of the maximum number of passes of each logic block to which each output signal from the corresponding logic block is supplied. logic simulator. (3) Assign a unique number (logic block number) to each logic block, use the logic block number and the terminal number of the output terminal of the logic block as an address signal, and output the logic b° lock at the address indicated by the address signal. Claim 1 or 2, characterized in that the logic block number of the logic block to which the terminal is connected and the input terminal) number box includes a second storage means for storing a pointer indicating the address of the connection destination. The logic simulator described in paragraph (2). (4) Assign a unique number (logical block number) to each logical block, use the logical block number as an address signal, and store the logical state value of the logical block and type information of the logical block at the address indicated by the address signal. a first storage means; reading the logic state value of the logic block to be updated from the first storage means according to the logic block number; and writing the logic state value of the logic block to be updated to the terminal according to the terminal number; and updating means for setting corresponding information and writing the updated logical state value into the first storage means. Logic simulator described in section.