JP2003185705A - Method for presuming failure position in logical circuit, and program for presuming failure position in logical circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To presume a failure position in a short time on a function level on the basis of circuit blocks. <P>SOLUTION: In a step 14, for each fail presuming circuit block, a circuit description part of the fail presuming circuit block is displayed as data flow by means of nodes and wire connection on a data processing basis and a determination graph is prepared for determining operations for all the conditions. On a step 16, by using nodes corresponding to a fail output port and to a fail presumption output port as starting points, output of each node is presumed by going back to the past in the input direction based on a fail vector. By making comparison with an expected value on each node, each fail propagation route is presumed. Based on correspondence of fail propagation origin node of the fail propagation route with an input port, information of non- corresponding nodes is registered as failure position presuming information. Information of corresponding input port is registered as the failure propagation presuming information. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for estimating a failure location of a logic circuit, and more particularly to estimating a failure location of a logic circuit based on fail information obtained from a test result of the logic circuit. Regarding the method.

[0002]

2. Description of the Related Art Conventionally, in this kind of logic circuit failure location estimation method, in order to estimate the logic circuit failure location, a logic circuit failure location estimation program is installed in a computer having a general configuration and each command is input. It is carried out according to the above.

For example, FIG. 5 is a flow chart showing a schematic process of a conventional fault location estimating method for a logic circuit. In this conventional fault location estimation method for a logic circuit, first, in step 51, a fault simulator is used to perform a function or logic simulation assuming a fault inside the logic circuit, and the simulation result is compared with an expected value. A fault dictionary is created by associating the assumed fault location with the test vector that detected the fault, and in step 52, fail information is acquired from the actual test result of the logic circuit. Next, in step 53, the failure dictionaries are respectively searched in correspondence with the fail pins and the fail vectors of the fail information to find a hypothetical failure point, and in step 54, a plurality of hypothetical failure points are given priority. Prioritize failure points by ranking them.

As another conventional method of estimating a failure point of a logic circuit, for example, an electron beam tester is used to estimate the failure point from the upper hierarchy of the logic circuit, observe the internal signal at the hierarchy boundary, and detect the failure point. There is also a method of sequentially narrowing down to the lower hierarchy of the logic circuit.

Further, as another conventional method for estimating a failure point of a logic circuit, as described in Japanese Patent Laid-Open No. 8-146093, the logic circuit is divided into a latch and a combinational circuit, and the failure point is detected at the gate level. There is also a method of estimation. In this method, a combinational circuit that has the possibility of propagating a fault to the failure output is dynamically extracted, the logical state and the path of propagation of the fault are estimated for each combinational circuit, and the fault location is estimated by tracing in the input direction. To do. Here, the logical state of the combinational circuit means not only the logical value of one signal line,
All nodes inside the circuit, that is, signal lines, gates, gate terminals, and input / output terminals are 0/1 / X "Don't Car".
e ”/ Z“ high impedance ”/ U“ undefined ”.

[0006]

In the conventional method of estimating a failure location of a logic circuit by a failure simulator, it is necessary to create a failure dictionary in advance, but the creation of the failure dictionary requires a great deal of failure simulation time. However, there has been a problem that as the scale of the LSI becomes larger, the calculation time becomes huge and the file of the failure dictionary becomes very large.
In addition, since the fault model used in the fault simulation is generally a single stuck-at fault, multiple faults such as bridging faults may not match the actual situation. Moreover, if the fault simulation model is expanded to multiple faults, the fault simulation The problem is that it is not practical in terms of processing time.

Further, the conventional method for estimating a failure point of a logic circuit using an electron beam tester is an effective means for narrowing down the failure point while sequentially observing from the upper layer to the lower layer of the logic circuit. When the LSI-based logic circuit becomes large in scale and has a multilayer wiring structure, there is a problem that the potential of the lower layer wiring cannot be observed.

Further, the conventional fault location estimation method at the gate level is an effective means because the fault location can be estimated for each combinational circuit. Accuracy and processing time are problems.

Therefore, the present invention has been made in view of the above problems, and its main purpose is to reduce the function level of each circuit block with respect to a logic circuit having a large scale and multilayer wiring. It is to estimate the failure point in time.

[0010]

Therefore, according to the present invention, there is provided a method of estimating a fault location of a logic circuit, wherein the fault location of the logic circuit is estimated based on fail information obtained from a test result of the logic circuit. From the description information functionally described in a hardware description language in circuit block units, based on the fail information or fail propagation estimation information, a fail output port or a fail estimation circuit block having a fail estimation output port is extracted, and the fail estimation circuit block A circuit graph is displayed as a data flow in the data processing unit node and a connection, and a decision graph for determining the operation for all the conditions is created, and the node corresponding to the fail output port and the fail estimation output port is used as a starting point to fail. Output estimation of each node based on the vector Fail estimation of each node is performed in the input direction by comparing the expected value with the expected value, and the fail propagation path is estimated. Based on the correspondence between the fail propagation source node and the input port of this fail propagation path, the information of the non-corresponding node is estimated as the failure location. Register as information, register the corresponding input port information as the fail propagation estimation information, repeat these processes until all the fail propagation source nodes do not correspond to the input port, and output the failure location estimation information as a list. ing.

Further, a step of performing a functional simulation based on the description information to obtain expected values of input / output ports or latches of all circuit blocks for a test input,
An extraction step of searching the fail output port or the fail estimation output port of the connection source from the description information based on the fail information or the fail propagation estimation information to extract the fail estimation circuit block, and each of the fail estimation circuit blocks. A step of creating each of the decision graphs, and a step of performing a functional simulation based on expected values of input / output ports or latches of the fail estimation circuit block using the decision graphs to obtain expected values of all nodes of the decision graph, respectively. Then, the node corresponding to the fail output port and the fail estimation output port is used as a starting point, and the fail estimation of each node is performed in the input direction by the output estimation of each node and the expected value comparison based on the fail vector, and the fail propagation path is estimated. ,this Based on the correspondence between the fail propagation source node and the input port of the fail propagation path, the information of the non-corresponding node is registered as the failure point estimation information, and the estimation step of registering the information of the corresponding input port as the fail propagation estimation information, It is determined whether all the fail propagation source nodes do not correspond to the input port, and if there is a fail propagation source node corresponding to the input port, a determination step of returning to the extraction step, and an output step of outputting a list of the failure location estimation information. Is included.

Further, the creating step assigns states to the circuit description part of the fail estimation circuit block in accordance with the processing order, and creates a state table composed of a current state, a state transition condition, a next state and an operation. A process of creating and reading the input port, latch, and state variable or value described in the state table is set as a read node, and the logical operator, arithmetic operator, and comparison operator described in the state table are set. Each process is set as an operation node, and corresponding to the assignment of the output port, the latch, and the state described in the state table to the variables,
A process of selectively allocating and writing one of the outputs of the read node or the operation node by binary control of the other output is set as an allocation determination node and a write node, respectively.

In the estimating step, the output of each node is estimated by tracing back the time in the input direction based on the fail vector starting from the fail output port and the write node corresponding to the fail estimation output port, Compare the expected value of each node, perform fail estimation of each node, estimate the fail propagation path, based on the correspondence between the fail propagation source node of this fail propagation path and the input port, It is registered as failure location estimation information, and the information of the corresponding input port is registered as the failure propagation estimation information.

Further, the output step converts the failure location estimation information into description information in a hardware description language and outputs it as a list.

According to the present invention, a computer is caused to execute an estimation process for estimating a failure location of the logic circuit based on the fail information obtained from the test result of the logic circuit.
In a failure location estimation program for a logic circuit, the estimation process estimates a failure output port or a failure from the description information in which the logic circuit is functionally described in a circuit block unit in a hardware description language based on the failure information or the failure propagation estimation information. A fail estimation circuit block having an output port is extracted, a circuit description part of the fail estimation circuit block is displayed as a data flow by a node and a connection of a data processing unit, and a decision graph for determining an operation for all conditions is created. From the fail output port and the node corresponding to the fail estimation output port as a starting point, the fail estimation of each node is performed in the input direction by the output estimation of each node and the expected value comparison based on the fail vector, and the fail propagation path is estimated. Propagation path Based on the correspondence between the failure propagation source node and the input port, the information of the non-corresponding node is registered as the failure point estimation information, the information of the corresponding input port is registered as the failure propagation estimation information, and all the failure propagation source nodes are registered. These processes are repeated until the input ports do not correspond to each other, and the failure location estimation information is output as a list.

[0016] Further, the estimation processing obtains expected values of input / output ports or latches of all circuit blocks with respect to a test input by performing a functional simulation based on the description information, and the fail information or the fail propagation estimation information. An extraction step of searching the fail output port or the fail estimation output port of the connection source from the description information to extract the fail estimation circuit block based on the description information; and a creation step of creating the decision graph for each of the fail estimation circuit blocks. A step of functionally simulating based on expected values of input / output ports or latches of the fail estimation circuit block using the decision graph to obtain expected values of all nodes of the decision graph, the fail output port and the fail estimation output The node corresponding to the node is used as the starting point, and the fail estimation of each node is performed in the input direction by the output estimation and the expected value comparison of each node based on the fail vector, the fail propagation path is estimated, and the fail propagation source node of this fail propagation path is estimated. Based on the correspondence between the input port and the input port, the information of the non-corresponding node is registered as failure location estimation information, and the estimation step of registering the information of the corresponding input port as the fail propagation estimation information, and all the fail propagation source nodes are input. Determine if it does not correspond to the port,
When there is a fail propagation source node corresponding to the input port, the method includes a determination step of returning to the extraction step and an output step of outputting a list of the failure location estimation information.

Further, the creating step assigns states to the circuit description part of the fail estimation circuit block in accordance with the processing order, and creates a state table composed of a current state, a state transition condition, a next state and an operation. A process of creating and reading the input port, latch, and state variable or value described in the state table is set as a read node, and the logical operator, arithmetic operator, and comparison operator described in the state table are set. Each process is set as an operation node, and corresponding to the assignment of the output port, the latch, and the state described in the state table to the variables,
A process of selectively allocating and writing one of the outputs of the read node or the operation node by binary control of the other output is set as an allocation determination node and a write node, respectively.

In the estimating step, the output of each node is estimated by tracing back the time in the input direction based on the fail vector starting from the write output node corresponding to the fail output port and the write estimation output port, Compare the expected value of each node, perform fail estimation of each node, estimate the fail propagation path, based on the correspondence between the fail propagation source node of this fail propagation path and the input port, It is registered as failure location estimation information, and the information of the corresponding input port is registered as the failure propagation estimation information.

Further, the output step converts the failure location estimation information into description information in a hardware description language and outputs it as a list.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. The method for estimating a failure point of a logic circuit according to the present invention estimates the failure point of the logic circuit as in the conventional method. It is carried out by executing.

FIG. 1 is a flow chart showing an embodiment of a method for estimating a fault location of a logic circuit according to the present invention. Referring to FIG. 1, in the method of estimating a failure location of a logic circuit according to the present embodiment, first, in step 11, fail information is acquired from the test result of the logic circuit. The fail information includes information on determination / non-determination of each pin, a fail pin, and a fail vector.

In step 12, Verilog
Functional simulation is performed on the basis of description information in which a logic circuit is functionally described in circuit block units in a hardware description language such as HDL or VHDL, and expected values of input / output ports or latches of all circuit blocks with respect to a test input are acquired.

In step 13, based on the fail information or the fail propagation estimation information, the connection source fail output port or fail estimated output port is searched from the description information, and the fail output port or the fail estimated circuit block having the fail estimated output port is searched. To extract.

In step 14, for each fail estimation circuit block, the circuit description portion of the fail estimation circuit block is displayed as a data flow by the node and connection of the data processing unit, and a decision graph for determining the operation for all conditions is created.

As this decision graph, for example, technical report, department of information end computer science, university of california, 1992 "Technica"
l Report, Dartment of Com
"Putter Science, 1992" Assignment Decision Diagram for High Level
Synthesis "Assingmentment Discisio
n Diagram for High-Level
A published in a paper titled "Synthesis"
DD "Assignment Decision Di
agram ”.

At this time, states are assigned to the circuit description part of the fail estimation circuit block in accordance with the processing order, and a state table composed of the current state, the state transition conditions, the next state and the operation is created. Set the input node, the latch, and the process of reading the variable or value of the state described in the state table as read nodes,
Set the processing of logical operators, arithmetic operators, and comparison operators described in the state table as operation nodes.
Also, output ports, latches, and
Corresponding to the assignment of the state to the variable, the process of selectively allocating and writing one of the outputs of the read node or the operation node by binary control of the other output is set as the allocation deciding node and the writing node, respectively.

In step 15, the decision graph is used to perform a functional simulation based on the expected values of the input / output ports or latches of the fail estimation circuit block, and the expected values of all the nodes of the decision graph are acquired.

In step 16, for each decision graph, starting from the fail output port and the write node corresponding to the fail estimation output port, the time is traced back in the input direction based on the fail vector, and the output of each node is estimated. Then, the fail estimation of each node is performed by comparing with the expected value of each node to estimate the fail propagation path. Further, based on the correspondence between the fail propagation source node and the input port of the fail propagation path, information of the non-corresponding node is registered as the failure location estimation information, and information of the corresponding input port is registered as the failure propagation estimation information.

In step 17, it is determined whether all fail propagation source nodes do not correspond to the input port. If there is a fail propagation source node corresponding to the input port, the process returns to step 13.

In step 18, the failure location estimation information is output as a list.

Next, the creation of the decision graph in steps 14 and 16 and the failure propagation estimation in the method for estimating the fault location of the logic circuit according to the present embodiment described above will be additionally described by using concrete circuit block examples.

For example, FIG. 2 shows HLSync89.
"Fourth International Wor
kshop on High-Level Synth
Benchmark circuit used in "esis"
It is explanatory drawing which shows the VHDL description example of r. Referring to FIG. 2, the description of this benchmark circuit counter is as follows.
Write a 4-bit counter circuit, clock, co
unt, up, countin are variables or signals of the input port, countout are variables or signals of the output port, and i is a variable or signal of the internal latch (hereinafter, "variable or signal" is referred to as "variable"). ). In some cases, "variable i" or the like is abbreviated as "i" or the like for convenience. When clock becomes "1", i is assigned to countout, and then cou
If nt = '1' and up = '1', then 4-bit low or i + 1 depending on whether i is 4-bit high or not.
To count up and up! = '1',
Count down by substituting 4-bit high or i-1 depending on whether i is 4-bit low, count =
In the case of "0", countin is substituted for i.

In step 14 of FIG. 1, VH of FIG.
A decision graph is created based on the DL description example.

First, the benchmark circuit co shown in FIG.
According to the processing order of the VHDL description of unter, the state S
T0 to ST3 are assigned to create a state table composed of the current state, state transition conditions, next state and operation. FIG. 3 is an explanatory diagram showing an example of this state table.

In the state ST0, if clock = '1', the state transits to the next state ST1, and if clock = '1' does not transit to the state ST3. In state ST1, i is assigned to countout, and the state transits to the next state ST2. In the state ST2, if count = '1', up
= “1” is determined. When up = '1', i =
It is determined whether it is “1111”. i = '111
In the case of 1 ', substituting' 0000 'for i, i =' 111
If not 1 ', i + 1 is substituted for i. Also, up =
If it is not '1', it is determined whether i = '0000' or not. If i = '0000', '1111' is substituted for i, and if i = '0000', i- Substitute 1 If count is not “1”, cou
Substitute ntin for i. Next, the state transits to ST3. In the state ST3, the state transits to the next state ST0.

Next, a decision graph is created corresponding to this example of the state table. FIG. 4 is an explanatory diagram showing an example of a decision graph created corresponding to the example of the state table of FIG.

Input port variables clock, count, up and countin described in the state table,
Latch variable i, state variable STATE, and value ST
0, ST1, ST2, ST3, '1', '1111',
The process of reading "0000" is set as a read node. Also, the AN described in the state table
Processing of logical operators such as D, OR, NOT, and +,-,
X, = ,! The processing of arithmetic operators such as (NOT EQUAL) and the processing of comparison operators such as <,>, = <, => are set as operation nodes. Also, the variable countout of the output port described in the state table,
Corresponding to the assignment to the variable i of the latch and the variable STATE of the state, the process of selectively allocating and writing one of the outputs of the read node or the operation node by the binary control of the other output is performed on the allocation deciding node and the writing node, respectively. Set as a built-in node.

Although not included in the node of the example of the decision graph of FIG. 3, a process of writing / reading a multidimensional variable such as a two-dimensional storage device corresponding to an index can be set as a node.

Further, in step 16 of FIG.
The fail propagation path is estimated using the example decision graph of

Now, S at times t-1, t, t + 1, t + 2
At TATE = ST0, clock = '1' and time t
Then, assume that countout = '0011' is output.

In order for countout to be '0011', the allocation decision node before the write node of countout and the connection destination node of its input are traced back to STAT.
Since the output of the read node of i is assigned and determined at E = ST1, the output of the read node of i is estimated to be '0011', that is, STATE = ST1 and i = '00.
It is estimated to be 11 '. Further, in order for STATE = ST1, the write node of STATE and the connection destination node of its input are traced back in order, and clock = '1' and STAT
It is estimated that E = ST0.

Similarly, in order to have STATE = ST0, STAT is obtained at time t-1 one clock before.
It is estimated that E = ST3. At this time, since the write node of i is not determined to be allocated, STATE = ST3 and i
= '0011' is estimated. Furthermore, STATE = S
To become T3, clock! = '1' and STA
It is estimated that TE = ST0 or STATE = ST2. Here, at STATE = ST0 at time t-1, cl
ock = '1', that is, the state is waiting for the next time t, so the time is traced back to the STATE at time t-1.
= ST2 is estimated.

In STATE = ST2, the following 5 patterns of conditions and operations are candidates for estimation by going back to the allocation decision node in the preceding stage of the write node of i and the connection destination node of its input. Pattern 1 Under the conditions of "STATE = ST2", "count = '1'", "up = '1'" and "i = '1111'", the allocation decision node before the write node of i is' 000.
Allocation decision pattern 0 is assigned to 0 '. Under the conditions of "STATE = ST2", "count =' 1 '", "up =' 1 '" and "i! =' 1111 '", the assignment decision of the write node before i is determined. Node is "i + 1"
Allocation decision pattern 3 Under the conditions of "STATE = ST2", "count = '1'", "up! = '1'" and "i = '0000'", '111
Allocation decision pattern 4 of 1'allocation under the condition "STATE = ST2", "count = '1'", "up! = '1'" and "i! = '0000'" The decision node is "i-
1 ”allocation determination pattern 5“ STATE = ST2 ”and“ count! = '1' ”
Under the condition of, the allocation decision node in the previous stage of the write node of i is co
Untin is assigned and determined Here, since STATE = ST3 and i = '0011' have been estimated, the cases of patterns 1 and 3 are not established. In the case of pattern 2, it is estimated that "STATE = ST2", "count = '1'", "up = '1'", and "i = '0010'". In the case of pattern 4, "STATE = ST2" and "count =
'1'"and" up! = '1'"and" i = '010 "
0 '"is estimated. In the case of pattern 5, "STAT
E = ST2 "and" count! = '1'"and" co
It is estimated that "untin = '0011'".

Furthermore, at time t-1, STATE = ST2
Therefore, at time t−1, STATE = ST1 is estimated, and in the state ST1, the allocation decision node before the write node of countout makes an allocation decision of i, and the write node outputs it. That is, the time t-1 one clock before
Is output.

Through the above processing, the output of each node at time t-1 is estimated from the output of the write node corresponding to the output port at time t, and at STATE = ST1 at time t-1, "count = '. 1'and up = '1' and i =
'0010'"," count = '1' and up! =
'1' and i = '0100'"or" count
!! = “1” and countin = “0011” ”.

As described above, the output of each unestimated read node is sequentially estimated while estimating the output of each node of the decision graph, starting from the node and vector corresponding to the fail output port or the fail estimated output port. It is possible to estimate the fail propagation path by comparing the estimation result with the fail information or the expected value and performing the fail estimation of each node. Further, based on the correspondence between the fail propagation source node and the input port of this fail propagation path, the information of the non-corresponding node is registered as the failure location estimation information,
Information on the corresponding input port is registered as fail propagation estimation information.

In the subsequent steps, the fail estimation circuit block of the failure propagation is extracted until all the failure propagation source nodes do not correspond to the input ports, and the additionally described decision graph creation and the failure propagation path estimation are repeated to find the failure location. Output estimated information as a list.

For this reason, the method of estimating a fault location of a logic circuit according to the present embodiment performs decision graph creation and failure propagation path estimation using the decision graph for each fail estimation circuit block extracted from the description information of the logic circuit. , It is possible to estimate the failure point at the functional level of each circuit block,
Compared with the fault estimation at the gate level, since the number of basic elements is smaller, the number of estimation processes is smaller and the estimation processing time can be shortened.

In the logic circuit fault location estimating method of the present embodiment, it has been described that the information of the node of the decision graph corresponding to the fail estimating circuit block is registered as the fault location estimating information and is output as a list. As a modified example, the information of the node of the decision graph registered as the failure location estimation information can be converted into the description information of the hardware description language and output as a list. This facilitates the feedback of the failure location estimation result to the functional design.

[0050]

As described above, the method of estimating a fault location of a logic circuit according to the present invention extracts a fail estimation circuit block from description information in which the logic circuit is functionally described in a circuit block unit in a hardware description language. For each extracted fail estimation circuit block, a decision graph is created and a fail propagation path is estimated using the decision graph, and the failure location can be estimated at the functional level of each circuit block.
Compared with the fault estimation at the gate level, the number of basic elements is reduced, so that the number of estimation processes is reduced and the estimation processing time can be shortened.

[Brief description of drawings]

FIG. 1 is a flowchart showing an embodiment of a method for estimating a failure location of a logic circuit according to the present invention.

FIG. 2 is an explanatory diagram showing a VHDL description example of a benchmark circuit counter.

FIG. 3 is an explanatory diagram showing an example of a state table for the VHDL description example of FIG.

FIG. 4 is an explanatory diagram showing an example of a decision graph created corresponding to the example of the state table of FIG.

FIG. 5 is a flowchart showing a schematic process of a conventional method of estimating a failure location in a logic circuit.

[Explanation of symbols]

11-18, 51-54 steps

Continued front page    (72) Inventor Kazuki Shigeta             5-7 Shiba 5-1, Minato-ku, Tokyo NEC Corporation             Inside the company F term (reference) 2G132 AA01 AB02 AC03 AL00 AL09                       AL12                 5B048 AA01 DD16 FF02

Claims (10)

[Claims] 1. A fault location estimating method for a logic circuit, which estimates a fault location of the logic circuit based on fail information obtained from a test result of the logic circuit, wherein the logic circuit is in a circuit block unit in a hardware description language. A fail estimation circuit block having a fail output port or a fail estimation output port is extracted from the description information describing the function based on the fail information or the failure propagation estimation information, and the circuit description part of the fail estimation circuit block is a node of a data processing unit. And make a decision graph for deciding the operation for all conditions by displaying the data flow by the connection, and estimate and expect the output of each node based on the fail vector starting from the node corresponding to the fail output port and the fail estimation output port. The value of each node is Fail estimation is performed in the input direction to estimate the fail propagation path, and based on the correspondence between the fail propagation source node and the input port of this fail propagation path, the information of the non-corresponding node is registered as failure location estimation information,
The information of the corresponding input port is registered as the fail propagation estimation information, and these processes are repeated until all the fail propagation source nodes do not correspond to the input ports, and the failure location estimation information is output as a list. , Failure estimation method of logic circuit. 2. A step of performing a functional simulation based on the description information to obtain expected values of input / output ports or latches of all circuit blocks for a test input, and from the description information based on the fail information or the failure propagation estimation information. An extraction step of searching the fail output port or the fail estimation output port of the connection source to extract the fail estimation circuit block; a creation step of creating the decision graph for each of the fail estimation circuit blocks; and the decision graph. A step of performing functional simulation based on expected values of input / output ports or latches of the fail estimation circuit block to obtain expected values of all nodes of the decision graph, respectively, corresponding to the fail output port and the fail estimated output port. node Based on the fail vector, the output of each node is estimated and the expected value is compared to perform the fail estimation of each node in the input direction, the fail propagation path is estimated, and the correspondence between the fail propagation source node and the input port of this fail propagation path Based on the above, an estimation step of registering information of unsupported nodes as failure location estimation information and registering information of corresponding input ports as the failure propagation estimation information, and determining whether all of the failure propagation source nodes do not correspond to input ports However, when there is a fail propagation source node corresponding to the input port, the step of returning to the extraction step and the step of outputting the list of the failure point estimation information are output, and the failure point of the logic circuit according to claim 1. Estimation method. 3. The creating step assigns states to the circuit description part of the fail estimation circuit block in accordance with the processing order, and creates a state table composed of a current state, a state transition condition, a next state and an operation. make,
The process of reading the input port, the latch, and the state variable or value described in the state table are set as read nodes, and the processes of the logical operator, arithmetic operator, and comparison operator described in the state table are respectively performed. It is set as an operation node, and one of the outputs of the read node or the operation node is controlled by binary control of the other output corresponding to the substitution of the output port, the latch, and the state variable described in the state table. 3. The method of estimating a failure location in a logic circuit according to claim 2, wherein the processing for determining and writing selective allocation is set as an allocation determination node and a writing node, respectively. 4. The estimating step estimates the output of each node by tracing back the time in the input direction based on the fail vector starting from the write output node corresponding to the fail output port and the write estimation output port, Fail estimation of each node is performed by comparing with the expected value of each node,
Estimating the fail propagation path, based on the correspondence between the fail propagation source node and the input port of this fail propagation path, the information of the non-corresponding node is registered as the failure point estimation information, and the information of the corresponding input port is propagated to the fail propagation. The method for estimating a failure location of a logic circuit according to claim 3, wherein the method is registered as estimation information. 5. The method of estimating a fault location of a logic circuit according to claim 2, 3 or 4, wherein the output step converts the fault location estimation information into description information of a hardware description language and outputs the list. 6. A logic circuit fault location estimating program for causing a computer to execute an estimation process for estimating a fault location of the logic circuit based on fail information acquired from a test result of the logic circuit, A fail estimation circuit block having a fail output port or a fail estimation output port is extracted based on the fail information or the failure propagation estimation information from the description information in which the function of the logic circuit is described in a circuit block unit in the hardware description language, and the fail estimation is performed. The circuit description part of the circuit block is displayed as a data flow with a node and a connection in a data processing unit to create a decision graph for determining the operation for all conditions, and the nodes corresponding to the fail output port and the fail estimated output port are used as starting points. Based on the fail vector Based on the correspondence between the fail propagation source node and the input port of the fail propagation path, the fail propagation path of the node is estimated in the input direction by the output estimation of each node and the expected value comparison. Information is registered as failure point estimation information, information of the corresponding input port is registered as the fail propagation estimation information, and these processes are repeated until all fail propagation source nodes do not correspond to the input port, and the failure point is registered. A fault location estimating program for a logic circuit, which outputs a list of estimation information. 7. The step of performing a functional simulation on the basis of the description information to obtain expected values of input / output ports or latches of all circuit blocks with respect to a test input, the estimation processing including the fail information or the fail propagation estimation information. An extraction step of searching the fail output port or the fail estimation output port of the connection source from the description information to extract the fail estimation circuit block based on the description information; and a creation step of creating the decision graph for each of the fail estimation circuit blocks. A step of functionally simulating based on expected values of input / output ports or latches of the fail estimation circuit block using the decision graph to obtain expected values of all nodes of the decision graph, the fail output port and the fail estimation Output port Based on the fail vector, the output corresponding to each node is used as the starting point and the fail estimation of each node is performed in the input direction by comparing the expected values, the fail propagation path is estimated, and the fail propagation source node of this fail propagation path is input. Based on the correspondence with the port, register the information of the non-corresponding node as failure location estimation information,
An estimation step of registering information of the corresponding input port as the fail propagation estimation information, determining whether all the fail propagation source nodes do not correspond to the input port, and if there is a fail propagation source node corresponding to the input port, the extraction is performed. The fault location estimating program for a logic circuit according to claim 6, further comprising: a determination step of returning to the step; and an output step of outputting a list of the fault location estimating information. 8. The creating step assigns states to a circuit description part of the fail estimation circuit block in accordance with the processing order, and creates a state table composed of a current state, a state transition condition, a next state and an operation. make,
The process of reading the input port, the latch, and the state variable or value described in the state table are set as read nodes, and the processes of the logical operator, arithmetic operator, and comparison operator described in the state table are respectively performed. It is set as an operation node, and one of the outputs of the read node or the operation node is controlled by binary control of the other output corresponding to the substitution of the output port, the latch, and the state variable described in the state table. The fault location estimating program for a logic circuit according to claim 6, wherein the process of deciding and allocating selective allocation is set as an allocating node and a write node, respectively. 9. The estimating step estimates the output of each node by tracing back the time in the input direction based on the fail vector starting from the write output node and the write node corresponding to the fail estimation output port, Fail estimation of each node is performed by comparing with the expected value of each node,
Estimating the fail propagation path, based on the correspondence between the fail propagation source node and the input port of this fail propagation path, the information of the non-corresponding node is registered as the failure point estimation information, and the information of the corresponding input port is propagated to the fail propagation. The fault location estimating program for a logic circuit according to claim 8, which is registered as estimation information. 10. The logic circuit fault location estimating program according to claim 6, 7, 8 or 9, wherein said output step converts said fault location estimation information into description information in a hardware description language and outputs the list.