JPS59112735A - Optical multiplex transmission system - Google Patents

Abstract

PURPOSE:To eliminate the need to use one channel for an identification signal by composing a serial signal a synchronizing bit, bits of plural channels, and the identification signal for a specific number of frames within one frame. CONSTITUTION:Sound signals of plural channels from terminals 1a-1p are passed through LPFs 2a-2p and A/D-converted 3a-3p. Those signals are time- divided into a specific number of channels CH by a multiplexer (MPX)6 under the control of a mode switching circuit 4, and those signals are latched 7 and inputted to a shift register 16. The register 16 adds the identification signal for a specific number of frames from a control signal generating circuit 17 to specific-bit digital signals of plural CHs or digital signals obtained by dividing bits of a 1/n CH by (n) within one frame to generate a serial digital signal. The output signal of the register 16 is converted 18 into a biphase NRZ signal, which is transmitted by driving a light emitting element 20.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application The present invention relates to a wireless optical multiplex transmission system suitable for use in front of simultaneous interpretation equipment at international conference venues.

BACKGROUND TECHNOLOGY AND INTERMEDIATION - In general, a device for transmitting audio signals of multiple channels, for example, a simultaneous interpretation device at an international venue, wirelessly transmits audio signals in languages of a plurality of different countries. In this case, it was necessary to use one of the plurality of channels for control data in order to inform the receiving side of the transmission mode, the audio being sent, and the contents of the data.

However, it is uneconomical to use one channel for this control data, and if there is a case where the transmission quality differs between the signal channel and the control data channel, the signal There was an inconvenience that normal reception was not possible even though the channel was good.

OBJECTS OF THE INVENTION In view of the above, an object of the present invention is to enable control data to be efficiently transmitted without using one channel for control data when transmitting a plurality of channels.

Summary of the Invention The present invention converts audio signals of multiple channels from analog to digital, time-division multiplexes the digital signals, and converts synchronized bits within 17 frames, digital signals of predetermined bits of the integer channels, or digital signals of the plurality of channels. A serial digital signal consisting of a digital signal in which the bits of the π channel are shuffled by n minutes mlj and a unit code forming a discrimination signal in a predetermined number of frames is generated, and a light emitting element is driven by this serial digital signal. According to the present invention, the discrimination signal can be transmitted satisfactorily without using one channel.

Embodiment An embodiment of the optical multiplex transmission system of the present invention will be described below with reference to the drawings.

FIG. 1 shows as a whole a transmission device according to the invention. 1st
In the figure, (la), (Ib) - (lp) are 1
It shows 16 channels of audio signal input terminals to which audio signals of the proverbs of six countries are supplied separately, and the audio signals are supplied to the audio signal input terminals (la), (lb), . . . (1p), respectively. A variable low-pass filter (2a) is applied to each audio signal.
(2b) A consisting of, for example, a delta transformer that converts an analog signal into a digital signal via (2p)
-D conversion circuit (3a), (3b)... (3p)
supply each. In this case, the variable low-pass filter (2a
), (2b)... (2p) is a control signal from the through mode switching circuit (4), which will be described later.When 16 channels are created by the %-dos selection switch (5), it is cut off. If the frequency is, for example, 5 KHz and 18 channels are selected, the cutoff frequency is, for example, 10 K.
Hz, and when 4 channels are selected, the cutoff frequency is set to, for example, 15 KHz.

These A-D conversion circuits (3a), (3b)-=
The output signals of (3p) are supplied to the respective latch circuits (7) via multiplexer circuits (6) constituting switches. In this case, when the mode switching circuit (5) has 16 channels, the multiplexer circuit (6) has 16 A-D converter circuits (3a), (3b)... (3
Each output signal of p) is supplied to a radio circuit (power), and when this mode is 8 channels, eight A-D converter circuits (3a) and (3b) up to the 8th channel are supplied.
)...-(3h) are supplied to the latch circuit (7), and when this mode is 4 channels, the four A-D converter circuits up to the fourth are supplied to the latch circuit (7). (
The respective output signals of 3a), (3b), (3c), and (3d) are supplied to the latch circuit (7).

Further, (8) shows a clock signal generation circuit that generates a clock signal of, for example, 4-3215 MHz, and the output side of the clock signal generation circuit (8) shown in FIG. 2A and the side shown in FIG. A pulse signal (9d) as shown in FIG. As shown in B, C, and D, the pulse signal (9
a), (9b) and (9c) are obtained, respectively.

A pulse signal (10a) as shown in FIG. 2F obtained at the output side of the hundred counter (10) is supplied to a pulse shaping circuit circle, and a pulse signal as shown in FIG. 2G is supplied to the output side of this pulse shaping circuit αυ. (10a) Pulse signal synchronized with the trailing edge (
lla). Also, a clock signal generation circuit (8
) is the clock signal (8a) obtained at the output side of the signal (1
1a) is supplied as a reset signal. The pulse signals obtained at the output side of this hundred counter (12) as shown in FIG. 2 I, J, K and L obtained at the respective output sides of the circuit shown in FIG. Tekota α4)
Supplied to and (15) respectively. This decoder (14) is constructed so as to sequentially generate clock signals with time shifts, and the output terminal at which the clock signal is generated is switched by a mode signal from a mode switching circuit (4).

That is, when the mode of the mode switching circuit (4) is 16 channels, the first . Second...
・16th output terminal (14a), (i4b)・
...(14p) 31st WA, B...P
16 clock signals sequentially shifted in time are obtained as shown in FIG. The repetition frequency of the clock signal in this case is, for example, 62.5 KHz.

Also, when the mode of the mode switching circuit (4) is 8 channels, the first . Second...Eighth output terminal (14a), (14b) ---(1
4h) in Figure 4A.

B...H clock signals of eight clock signals sequentially shifted in time are obtained.

The repetition frequency of the clock signal in this case is, for example, 16
The frequency is 125 KHz, twice that of the channel.

Also, when the mode of the mode switching circuit (4) is 4 channels, the first . Second. Third and fourth output terminals (14a), (14b), (14c)
And (14d), four clock signals sequentially shifted in time as shown in FIGS. 5A, B, C and D are obtained. The repetition frequency of the clock signal in this case is, for example, 25, which is four times that of 16 channels.
0 KHz.

The first . 2nd...16th output terminal (14a), (14b)---(14
1) ) respectively as A-D conversion circuits (3a), (3b)...
. . . (3p) is connected to each clock signal input terminal.

Also, the decoder Q5) has four output terminals shown in FIG.

R, 8, T, Figure 4 I, J, L and Figure 5 E,
As shown in F', .G, and H, four clock signals are obtained by sequentially shifting the four clock signals at equal time intervals in one frame.

The four output terminals of this decoder (15) are connected to a latch circuit (
The output clock signal is supplied to each input terminal. In addition, the latch circuit (16 output terminals of the output power) is connected to the input terminal of a shift register (16) that converts a parallel signal into a serial signal. The synchronizing signal supplied to the terminal (16s) is supplied to this shift register α6).

Further, the output signal of the mode switching circuit (4) is supplied to the control signal forming circuit αD. In this control signal forming circuit 07), in the 16 channel mode, for example, a repeating digital signal of l'-0111J is generated,
In the 8 channel mode, for example, a signal repeating ``0OIIJ'' is generated, and in the 4 channel mode, for example, a signal repeating ``0001 J'' is generated. This shift register a6)
and parity check signal input terminal (16p)
The parity check signal P supplied to the shift register (16) is supplied to the shift register (16). A clock signal (9b) obtained by setting the clock signal (8a) obtained at the output side of the second flip-flop circuit of the m counter (9) to 1 is supplied as a clock signal to this shift register α6), and the pulse shaping circuit The pulse signal (lla) obtained at the output side of (11) is used as a load signal and this shift register (1
6), one frame is composed of 20 bits as shown in FIG.
In the 16 channel mode, as shown in FIG. 6A, the first 2 bits are used as a synchronization signal S, the next 16 bits are used as 16 different data signals D, D2, . . . Dl, and the last 2 A time-division serial digital signal is obtained by sequentially converting bits into a control signal C and a parity check signal P. In this case, the control signal C forms a discrimination signal in four frames, that is, as shown in FIG. 6B, the unit code is "0" in the first frame F1, and the unit code is "0" in the second frame F1.
Third and fourth frames F2. F8. F, the unit code is set to "1". Repeat this step by step. Also, when in 8 channel mode, this shift register (16
), the first 2 bits are used as a synchronizing signal S, and the next 16 bits are divided into two to produce 8 data signals D1, D, . The final two bits are used as a control signal C and a parity check signal P in order to obtain a time-division serial digital signal. In this case, as shown in FIG. 6C, the control signal C is applied to the first and second frames F1 and F2.
Then, the unit code is set to "0", and the nest position code is set to "1" in the third and fourth frames F8 and F4, and this is sequentially repeated. Furthermore, in the 4-channel mode, the first 2 bits of the output G of this shift register (16) are used as the synchronizing signal S, as shown in Figure 6, the next 16 bits are divided into 4, and each 4 bits is divided into 4 different signals. Data signal, D2
D3 and D4, and the last two bits are sequentially used as a control signal C and a parity check signal P to obtain a time-division serial digital signal.

In this case, as shown in Figure 6, the control signal C is
．． In the second and third frames F, , F2 and F8, the unit code is set to "0", and in the fourth frame F4, the unit code is set to "1P", and this is repeated sequentially.On the output side of this shift register (L6) The obtained serial signal ν digital signal is supplied to an NRZ-piphase conversion circuit (18) that converts the NRZ signal into a biphase signal suitable for transmission.This NRZ-piphase conversion circuit 08) also includes a clock signal generation circuit. The clock signal (8a) obtained at the output side of (8) and the first 7 of the counter (9)
The clock signal obtained at the output side of the lip-flop circuit (
8a) and a clock signal (9a) of one hundred frequencies, respectively. For example, in the 16 channel mode, a pie-phase signal as shown in FIG. 6E is obtained on the output side of the NFI, Z-pi-phase circuit α8). In FIG. 6E, the synchronizing signal S has a pattern in which 1°5T is a 7-E level and 0.5T is a low level when 2 bits are in a 2T interval. In this bi-phase signal, this 1°5
The high level of T (1 does not appear, so it is easy to extract the synchronization signal on the receiving side. Also, the 2 bits of the synchronization signal (“0”)
1”), data signal, ,D,...D
16. If even parity is used including the control signal C, the edge of the synchronizing signal S will always rise from a low level to a high level. The same applies to the 8-channel mode and the 4-channel mode. The pi-phase serial digital signal as shown in FIG. 6E obtained at the output side of this NRZ-pi-phase conversion circuit (L8i) is supplied to the light emitting diode device M (20) via the LED driver circuit (I9). .This light emitting diode 'J
M (20) is, for example, 10 in order to obtain a sufficient amount of light.
Uses 0 light emitting diodes.

In Fig. 1, the mode selection switch (1
When 6 channel mode is selected, decoder α→)
16 output terminals (14a), (14b)--
- At (14p), clock signals sequentially shifted in time as shown in FIG. Song (3p)
16 audio signal input terminals (la),
(lb)...The audio signal from (1p) is LouD
transformed and variable low-pass filters (22), (2
b) The cutoff frequency of (2p) is, for example, 5 KJ (z), and the discrimination signal for this 16 channel mode is formed by the control signal forming circuit (171), and this control signal 10111j A repeating signal is supplied to the shift register (16).Therefore, at this time, the output side of the shift register (06), that is, the LED
The driver circuit (19) receives synchronous bits S, 16 channels of data signals in one frame as shown in FIGS. 6A and 6H, and digital signals of 16 channels.

A serial digital signal consisting of a control signal C and a parity check signal P is obtained, and this serial digital signal is optically transmitted.

Also, when the 8 channel mode is selected by the mode selection switch (5), the 8 output terminals (
14a), (14b)--(14h), clock signals whose time is sequentially shifted as shown in FIG. (3a), (3b)... (3h), respectively, and eight audio signal input terminals (Ia), (Ib)...
...(1h) are respectively subjected to A-I)ffi and variable low-pass filters (2a).

The cutoff frequency of (2b)... (2h) is set to 10KHz, for example, and a signal for determining the 8-channel mode is formed by the control signal forming circuit 07), and this controller/1/signal "0011'1"
A repetitive signal of is supplied to the shift register (16). Therefore, at this time, the output side of the shift register (16), that is, the LED driver circuit α9), contains the synchronization bit S and the 8-channel data signal D□lD2...D8 within one frame as shown in FIG. 6C. A serial digital signal consisting of a twice-repeated digital signal, a control signal C, and a parity check signal P is obtained, and this serial digital signal is optically transmitted.

Also, when the 4-channel mode is selected by the mode selection switch (5), the four output terminals (14
a), (14b), (14c) and (1
4d), time-shifted clock signals as shown in FIG. 3d), and four audio signal input terminals (la) and (lb
), (Ic) and (1d) are respectively A-D.
transformed and variable low-pass filters (2a), (2
The cutoff frequency of b), (2c) and (2d) is set to, for example, 15KH2, and a signal for determining the 4-channel mode is formed in the control signal forming circuit (17), and this control signal 1-0001 j A repetitive signal of is supplied to the shift register (16).

Therefore, at this time, on the output side of the shift register (16), that is, the LED driver circuit (19), the synchronization bit S, 4 channels of data signals D, D2. A serial digital signal consisting of a digital signal D3 and D3 repeated four times, a control signal C, and a parity check signal P is obtained, and this serial digital signal is optically transmitted.

As described above, in the example shown in FIG. 1, the number of channels to be transmitted can be selected from 16, 8, and 4, and the frequency band of the audio signal to be transmitted can be changed. Therefore, it is conceivable to use it as a 16-channel simultaneous interpretation device during normal times, and use it as a 4-channel device during breaks, that is, to widen the transmission frequency band and transmit stereo signals and the like.

Also, this 16 channel mode, 8 channel mode, 4
Since the discrimination signal for discriminating the channel mode is provided in unit bits in each frame, there is no need to use one channel in particular, and since the transmission quality of the data signal and control signal of each channel is equal, the transmission of each channel is Normal reception is always possible when each is normal.

Next, an example of a headphone receiver that receives this optically transmitted serial digital signal will be explained with reference to FIG. In this FIG. 7, the front end circuit CI! 2)
The output signal of this front end circuit (22) is supplied to a clock recovery circuit (24) that regenerates a clock signal, and the output signal of this clock recovery circuit (24) is supplied to the waveform shaping circuit (23) via The clock signal obtained by the waveform shaping circuit (23) is supplied to the waveform shaping circuit (23), and the waveform-shaped pi-phase digital signal obtained at the output side of the waveform shaping circuit (23) is converted into a pi-phase No. 100 by Nf.
Bi-Fenize N-Z conversion circuit (2) that converts to tZ signal
5), and also supplies the output signal of this waveform shaping circuit (23) to a synchronization signal extraction circuit (2G), and the synchronization signal obtained at the output ' side of this synchronization signal extraction circuit (25) is It is supplied to the conversion circuit 05). The NRZ digital signal obtained at the output side of this pi-phase-NRZ conversion [al circuit 5) is supplied to a demultiplexer (27) that uses a predetermined channel, and the pi 7
The output signal of the AZN Bz g fM circuit I25) is supplied to the control signal extraction circuit 1 (23a) that extracts the control signal C.

The control signal C obtained at the output side of this control signal extraction circuit (28a) is supplied to a 4-bit shift register Hsb) that converts a serial signal into a parallel signal, and a synchronization signal extraction circuit is connected to this 4-bit shift register Hsb). )) is supplied as a clock signal, and the first and second output terminals of the four output terminals of this 4-bit shift register (28b) are connected to the two inputs of the NAND circuit N,5 (28c). The third and fourth output terminals are connected to the two input terminals of the NAND circuit (28e) and connected to the two input terminals of the exclusive-or circuit (28d). Connected to the two input terminals of the I/O circuit (28f), and also connected to the two input terminals of the NAND circuit (28c) and (28e).
) are connected to the two input terminals of the NAND circuit (28g), and the exclusive live-or circuit (28g) is connected to the two input terminals of the
d) and (28f) are connected to the two input terminals of the exclusive live OR circuit (28h), and the output signal of this NAND circuit (28g) and the exclusive live OR circuit (28h) are connected. The output signals are respectively supplied to the discrimination circuit bI4:+(28i). In this case, 16 channel mode is l'-0111J and Nando times b'i28g
) and the exclusive live OR circuit (28h) are both “1”, and the 8 channel mode is [
At 0011J, the output signal of the NAND circuit (28g) is “0”.
”, and the 4 channel mode is [0001J, the output signal of the NAND circuit (28g) is “1”, and the output signal of the exclusive OR circuit (28h) is “
0", and each mode is discriminated from this. A control signal according to the discrimination of this discriminator circuit (28i) is supplied to the demultiplexer (2η), and the demultiplexer (2η) is output according to the channel mode. 2η. Also, 9) indicates a channel selection switch that arbitrarily selects a desired channel, and supplies the selection signal from the channel selection switch marked c to the demultiplexer eη, and the demultiplexer □□□ Determine the channel to be selected.The output signal of this demultiplexer η is supplied to a D-A conversion circuit (30) that converts a digital signal into an analog signal.
The audio signal obtained at the output side of this DA conversion circuit (30) is supplied to the audio amplification circuit (3z) via a variable low-pass filter Gl). This variable low-pass filter C3υ
The cutoff frequency is switched by the output signal of the discrimination circuit (28i). For example, when the output signal of the discrimination circuit (28i) is in 16 channel mode, it is 5KH.
z.

The frequency is set to 10 KHz in 8 channel mode and 15 KHz in 4 channel mode. The audio signal obtained at the output side of the audio amplification circuit C34 is supplied to the headphones O2.

In such a headphone receiver, the light receiving element (21) receives a synchronization bit S within one frame as shown in FIG. 6E.

Biphase valence channel digital signal.

A serial digital signal of control signal C is received, this signal is converted into an NRZ digital signal by a biphase-NRZ conversion circuit (25), and a desired channel of this serial digital signal is converted according to the channel mode. Demultiplexer (select by 2-way, connect this to D-A
Since it is converted into an audio signal by the conversion circuit (3Q), the desired audio signal selected by the channel translation switch (29) can be listened to through the headphones (33).

Further, FIGS. 8 and 9 respectively show other examples of determining the control signal C of the headphone receiver. In FIGS. 8 and 9, parts corresponding to those in FIG. 7 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

That is, in FIG. 8, the output side of the control signal extraction circuit (28a) is grounded through a series circuit of a resistor (28j), a capacitor (28k), and a parallel circuit of a resistor (281) to obtain an average pressure. , connect the connection point of resistors (28j) and (281) to "1" in 4 bits of digital signal.
” is 2 bits or more, the output terminal becomes high level ``1'' (28m), and when there are 3 or more ``1'' bits among the 4 bits of the digital signal, the output terminal becomes high level ``1''. Comparison circuit (28n) whose terminal becomes high level “1”
) to their respective input terminals. In this Figure 8, in the 16 channel mode, the discrimination signal is l'-011.
1J, the output sides of the comparator circuits (28m) and (28n) are both at high level "DE", and in the 8 channel mode, the discrimination signal is "0011J", and the output sides of the comparator circuits (28m) and (28n) are "0011J".
The output side of m) becomes high level “1” and the comparator circuit (
The output side of the comparison circuits (28m) and (28n) becomes a low level "0°", and in the 4-channel mode, the discrimination signal is JQOOIJ, and the output sides of the comparison circuits (28m) and (28n) both become a low level "0".

In addition, FIG. 9 shows that the four output terminals of the 4-bit shift register (28b) are respectively supplied to the latch circuit j% (28o), and the output signal of the control signal extraction circuit (28a) is applied to the falling edge of the control signal C. is detected and supplied to a latch signal forming circuit M (28p) that forms a latch pulse,
The latch signal obtained at the output side of this latch signal forming circuit jM (28p) is supplied to the latch circuit (28o), and the first . The second and third output terminals are connected to a decoder (28q). (26a) is a synchronization signal input terminal to which a synchronization signal from the synchronization signal extraction circuit (26j) is supplied.

In FIG. 9, in the 16 channel mode, the discrimination signal is "0111 J," so the three output terminals of the latch circuit (28o) are at high level "1'," and in the 8 channel mode, the discrimination signal is "0111 J." is l'-00
11'J, the two output terminals of the latch circuit (28o) become high level "1", and in the 4 channel mode, the discrimination signal is "0001", so the latch 115 (280
) becomes a high level "1", and the like can be determined.

In the above-mentioned embodiments, an example was described in which the present invention was used in a simultaneous interpretation device, but it goes without saying that the present invention can also be used in the case of optically transmitting other data signals.

Further, in the above embodiment, the control signal C is provided as a discrimination signal in 4 frames, but it is of course possible to provide it periodically or intermittently in any frame of 2y-) or more. be. Further, the present invention is not limited to the above-described embodiments, and it goes without saying that various other modifications can be made without departing from the gist of the present invention.

Effects of the Invention According to the present invention, good control data can be transmitted without using one channel for control data when performing optical transmission with a plurality of channels.

In this case, since the data signal and control signal are transmitted on the same channel, the transmission quality is the same, and when the transmission on each channel is normal, there is an advantage that normal reception can be achieved. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an optical multiplex transmission device according to the present invention, and FIGS. 2, 3, 4, 5, and 6 are diagrams for explaining the present invention, respectively. , FIG. 7 is a block diagram showing an example of a headphone receiver according to the present invention, and FIGS. 8 and 9 are block diagrams showing other main parts of FIG. 7. (la), (lb)... (1p) are respectively audio signal input terminals, (3a), (3b) - (3p) are A
-D conversion circuit, (4) is a mode switching circuit, (5) is a mode selection switch, (6) is a multiplexer, (7) is a latch circuit, (8) is a clock signal generation circuit, 04 is a decoder, (1G ) is a shift register, (17) is a control signal forming circuit, (20) is a light emitting diode device,
(282) is a control signal output circuit, 1" 1LI
FB and F4 are respectively 1st. Second. These are the third and fourth frames. Fig. 3 O 1゜

Claims (1)

[Claims] The audio signal of the ah channel is A-D converted, and the digital No. 18 is time-division multiplexed, and synchronization bits,
Generates a serial digital signal consisting of a digital signal of predetermined bits of the plurality of channels, or a digital signal obtained by dividing the bits of one channel of the plurality of channels into n, and a signal that forms a discrimination signal using a predetermined number of frames. A transmission system characterized in that the serial digital signal is used to drive the light-emitting element for transmission.