JPS59112736A - Optical multiplex transmission system - Google Patents

Abstract

PURPOSE:To select a channel of transmission optionally by converting sound signals of plural channels from analog to digital, and driving a light emitting element by a serial digital signal generated within one frame by time-division multiplexing. CONSTITUTION:The sound signals of plural channels CH are inputted to A-D converters 3a-3p through variable LPFs 2a-2p and converted there into digital signals, which are inputted to a multiplexer (MPX)6. The MPX6 multiplexes the input signals to the numbers of CHs corresponding to a mode by a control signal from a switching circuit 4 selected with a mode selection switch 5. Further, a clock from a clock signal generator 8 is frequency-divided to generate the serial signal consisting of a synchronizing bit, specific-bit digital signals of plural CHs or signals obtained by dividing 1/nCH bits of plural CHs by (n), and a control and a parity signal by a serial register 16. Then, the light emitting diode 20 is driven by the signal obtained by converting 18 the serial signal into the biphase signal, which is appropriated for an NRZ signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a wireless optical multiplex transmission system suitable for use in simultaneous interpretation equipment in international conference halls.

BACKGROUND TECHNOLOGY AND PROBLEMS Generally speaking, in devices for transmitting audio signals of multiple channels, such as simultaneous interpretation devices in international conference halls, it is no longer possible to wirelessly transmit audio signals in languages of multiple different countries. In this case, a plurality of frequency-divided carrier signals are frequency-modulated in the languages of different countries, and multiplex transmission is performed using this frequency modulation. However, in this case, the number of channels, the audio frequency band, etc. are fixed and cannot be selected arbitrarily as needed, which is disadvantageous and uneconomical.

OBJECTS OF THE INVENTION In view of these points, the present invention allows the number of transmission channels to be arbitrarily selected and the transmission audio frequency band to be changed.

Summary of the Invention The present invention converts audio signals of multiple channels from analog to digital, time-division multiplexes the digital signals, and converts synchronized bits, digital signals of predetermined bits of the multiple channels, or units of the multiple channels into one frame. channel bits n
According to the present invention, a serial digital signal consisting of a divided digital signal and a determination signal of predetermined bits is generated, and a light emitting element is driven and transmitted by the serial digital signal. The number of channels through which audio signals are transmitted can be arbitrarily selected, and the transmission frequency band can be changed.

Embodiment Hereinafter, one embodiment of the optical multiplex transmission system of the present invention will be explained with reference to the drawings.

FIG. 1 shows as a whole a transmitting device according to the invention. 1st
In the figure, (la), (lb)... (1p) indicate audio signal input terminals of 16 channels to which, for example, audio signals of 16 languages are separately supplied, and this audio signal input terminal (la) ), (lb)...(lp) K
Each supplied audio signal is passed through a variable low-pass filter (
2a).

(2b)...(2p) are supplied to A-D converter circuits (3a), (3b)...(3p), each of which is composed of, for example, a delta modulator, which converts an analog signal into a digital signal. In this case a variable low-pass filter (2a),
(2b)...(2p) is a mode switching circuit (4) which will be described later.
) When 16 channels are selected by the mode selection switch (5), the cutoff frequency is set to, for example, 5 KHz, and when 8 channels are selected, the cutoff frequency is set to, for example, 10 KHz, and the cutoff frequency is set to 4 channels. is selected, the cutoff frequency is set to, for example, 15 KHz.

A-D conversion circuit (3a), (3b) ・= (
3p) is supplied to each latch circuit (7) via a multiplexer circuit (6) constituting a switch.

In this case, this multiplexer circuit (6) has 16 A channels when the mode of the mode switching circuit (5) is 16 channels.
The output signals of the -D conversion circuits (3a), (3b), . . . (3p) are respectively supplied to the latch circuit (7), and when this mode is 8 channels, the Two A-D conversion circuits (3a), (3b) ・
(3h) are supplied to the latch circuit (7), and when this mode is 4 channels, the output signals of the four A-D converters (3a) (3b) are supplied to the latch circuit (7).
) (3c) The respective output signals of (3d) are supplied to the latch circuit (power).
A clock signal generation circuit that generates a 3215 MHz clock signal is shown, and a pulse signal (9d) as shown in FIG. 2E obtained at the output side of FIG. 2A obtained at the output side of this clock signal generation circuit (8). is supplied to a counter (10) constituting a frequency divider. In this case, the output sides of the first, second and third flip-flop circuits of the four flip-flop circuits constituting the counter (9) are as shown in FIG.
Pulse signals (9a), (9b) and (9c) in which the dominant frequency is 1 as shown in C and D are obtained, respectively.

The cell signal (10a) as shown in FIG. 2F obtained at the output side of the appetizer counter aO) is supplied to the Norse shaping circuit 0υ, and the signal shown in FIG.
Synchronized with the trailing edge of the Gills signal (10a) as shown in
signal (11a). In addition, the clock signal (8a) obtained on the output side of the clock signal generation circuit (8)
) which constitutes a frequency divider (1 counter (1) is supplied to 5 and this counter 02 is supplied with a pulse shaping circuit 0])
A pulse signal (lla) is supplied as a reset signal. As shown in FIG. 2, the pulse signal (Ila) of the pulse shaping circuit 6aυ obtained at the output side of the I counter (12) is supplied as a reset signal to the upper counter 03). The four flips forming this counter (I, J) are obtained at each output side of the flip circuit.
, and L, which are successively set to 1, are supplied to the decoder (14) and (Iω), respectively.

This decoder (1 (a)
) The output terminal at which the cyclic clock signal is generated is often switched depending on the other mode signal. That is, when the mode of the mode switching circuit (4) is 16 channels, this decoder (14
) No. 1. 2nd...16th output terminal (14a).

In (14b)...(14p), 16 clock signals as shown in FIG. 3A, B...P, which are sequentially shifted in time, are obtained. The repetition frequency of the clock signal in this case is, for example, 62.5 KHz.

When the mode of the mode switching circuit (4) is 8 channels, the first . 4A to the second...eighth output terminal Q4a) (x4b)...(14h)
, B, . . ., eight clock signals sequentially shifted in time are obtained. The repetition frequency of the clock signal in this case is, for example, 125 KHz, which is twice that in the case of 16 channels.

Also, when the mode of the mode switching circuit (4) is 4 channels, the first . Second. 3rd and 4th
output terminals (14a), (14b), (14c
) and (14d), four clock signals sequentially shifted in time as shown in FIGS. 5A, B, C, and D, respectively, are obtained. In this case, the repetition frequency of the clock signal is, for example, 2 times four times that of 16 channels.
It becomes 50 KHz.

The first . Second. ...The 16th output terminals (14a), (14b) - (14p) are connected to the hA-D conversion circuits (3a), (3b)... (3p)
) to each clock signal input terminal. Also, the decoder (15) has its four output terminals Q, R, s in Figure 3.
':, , T, Figure 4 I, J', L and Figure 5 E,
4 at equal time intervals in one frame as shown in F, G, and HK respectively.
The clock signal is obtained by sequentially shifting the two clock signals in time.

The four output terminals of this decoder (15) are connected to a latch circuit (
The output clock signal is supplied to each input terminal. Furthermore, the 16 output terminals of the latch circuit (7) are respectively connected to the input terminals of a shift register (16) that converts the parallel signal into a serial signal. Further, (16s) indicates a synchronization signal input terminal, and the synchronization signal supplied to this synchronization signal input terminal (168) is supplied to this shift register (16). Also, the output signal of the mode switching circuit (4) is supplied to the control signal forming circuit 07), and this control signal forming circuit 0'
7) When in 16 channel mode, for example, ro
It generates a repeating digital signal of lllJ, for example, in 8-channel mode, it generates a repeating signal of I"0011j, and in 4-channel mode, it generates a repeating signal of, for example, ro.
A signal repeating oolJ is generated. The control signal C obtained at the output side of the control signal forming circuit (17) is supplied to this shift register α6), and the parity check signal P supplied to the parity check signal input terminal (16p) is supplied to this shift register t1.
6). This shift register (16) is connected to the clock signal (8a
) is supplied as a clock signal, and the pulse signal (ha) obtained at the output side of the pulse shaping circuit αυ is supplied as a load signal to this shift register (16), and this shift register (16) is supplied as a load signal. Register (16
), one frame is composed of 20 bits as shown in Figure 6A, C and D, and in the 16 channel mode, the first 2 bits are used as a synchronization signal as shown in Figure 6A, and the next 16 bits are 16 different data signals D1. D2・
... D16, and the last 2 bits are sequentially used as control signal C and /('retight check signal P) to obtain a time-division serial digital signal. Also, in 8 channel mode, this shift register αG) As shown in FIG. 6C, the first 2 bits are used as a synchronization signal sequence, and the next 16 bits are divided into two to produce eight data signals D1. D2...D8, and the last two bits are sequentially used as a control signal C and a parity check signal P to obtain a time-division serial digital signal. Furthermore, in the 4-channel mode, the first 2 bits are used as synchronization signals on the output side of this shift register (16) as shown in Figure 6, and the next 16 bits are divided into 4, and each 4 bits is divided into 4 different data signals. D1. D2. D3 and D4, and the last two bits are sequentially sent to the control signal C.
and a time-division serial digital signal as a parity check signal P. This shift register (1
6) The serial digital signal obtained at the output side j of
N to convert RZ signal into bi-phase signal suitable for transmission
It is supplied to the RZ-biphase conversion circuit (18). The clock signal (8a) obtained from the output side of the clock signal generation circuit (8) is connected to the NRZ-biphase conversion circuit α.
) and a clock signal (9a) having the same frequency as the obtained clock signal (8a) are supplied to the output side of the first Fritzno flop circuit of the B counter (9). This NR
For example, in the 16-channel mode, a pie-phase signal as shown in FIG. 6B is obtained on the output side of the Z-piphase circuit a. In this FIG. 6B, the synchronization signal S
When 2 bits are defined as a 2T interval, 1.5T is a high level and 0.5T is a low level. Since this high level of 1.5T does not appear in this biphase signal, it becomes easy to extract the synchronization signal on the receiving side.

Also, 2 bits of synchronization signal (regarded as "O"1#), data signal, D2...D16, control signal C
If an even number A IJ including , the edge of the synchronizing signal S always rises from low level to high level. The same applies to the 8-channel mode and the 4-channel mode. The pi-phase serial digital signal as shown in FIG. For example, 100 light emitting diodes are used as the light emitting diode device (20) to obtain a sufficient amount of light.

In FIG. 1, when the 16 channel mode is selected by the mode selection switch (5), the decoder 04
) 16 output terminals (14a), (14b) -
(14p), clock signals with sequential time shifts as shown in FIG. 3A, B...P are obtained, respectively, and
16 audio signal input terminals (la) (lb) are supplied to the conversion circuits (3a), (3b) - (3p), respectively.
The audio signal from ... (1p) is A-D converted and is also passed through variable low-pass filters (2a) (2b) ... (2
The cutoff frequency of r0111J is set to 5 KHz, for example, and a signal for determining the 16-channel mode is generated by the control signal forming circuit 0η, and a signal that repeats this control signal r0111J is sent to the shift register (
16). Therefore, at this time, the output side of the shift register (I6), that is, the LED driver circuit (synchronized pins are generated within one frame as shown in FIG. 6 at 19), the 16-channel data signal D1. A serial digital signal consisting of the i digital signals D2...D16, the control signal CNze integrity check signal P is obtained, and this serial digital signal is optically transmitted. Also, when the 98 channel mode is selected by the mode selection switch (5), the eight output terminals (14a) of the decoder (L4),
(14b) ・-(14h) Figure 4 A, B, respectively.
・Time shifts and lock signals as shown in H are obtained, and these are A-D conversion circuits (3a) and (3b), respectively.
- (3h) respectively, and the audio signals from the eight audio signal input terminals (la), (lb)...
), (2b)...('2h) is set to, for example, 10Kf(z), and this 8-channel mode discrimination signal is sent to the control signal forming circuit ('2h).
Iη, and a repetitive signal of this control signal rho11J is supplied to the shift register α6).

Therefore, at this time, the output side of the shift register (16), that is, the LED driver circuit (19) has a 1 value as shown in FIG. 6C.
Synchronous bits in a frame 818 channels of data signals Di l D2...D8 repeating digital signals twice, control signal 01 control signal P
A serial digital signal consisting of is obtained, and this serial digital signal is optically transmitted. When the 4-channel mode is selected by the mode selection switch (5), the four output terminals (14a) (14b) of the decoder (14)
) Figure 5A in (14,c) and (14d), respectively.

Clock signals whose time is sequentially shifted as shown in B, C and D are obtained, and these are respectively A-D converter circuits (3a).

(3b), (3C) and (3d), respectively;
4 audio signal input terminals (la), (lb),
The audio signals from (lc) and (1d) are respectively A-D converted and passed through variable low-pass filters (2a) and (2
b) The cutoff frequency of (2c) and (2d) is set to 15 KHz, for example, and a signal for identifying the 4-channel mode is formed on the control signal forming circuit, and the repeating cycle of this control signal "0001" A return signal is supplied to shift register αe. Therefore, at this time, the output side of the shift register (16), that is, the LED driver circuit (1, 814 channels of data signals D1, D2 of synchronous bits in one frame as shown in Figure 6)
．． A serial digital signal consisting of a digital signal of four repetitions of D3 and D4, a control signal C, and a integrity check signal P is obtained, and this serial digital signal is optically transmitted.

As described above, in the example shown in FIG. 1, the number of channels to be transmitted can be selected from 16, 8, and 4, and the frequency band of the audio signal to be transmitted can be changed. Therefore, under normal circumstances, it is used as a simultaneous interpretation device for 16 channels.
It is conceivable to transmit stereo signals and the like by using four channels, that is, by widening the transmission frequency band, during breaks and the like.

Next, with reference to FIG. 7, an example of a headphone receiver that receives this optically transmitted serial digital signal will be described. In FIG. 7, the ifal signal as shown in FIG. At the same time, the output signal of this front end circuit (24) is supplied to a clock recovery circuit (24) that regenerates a clock signal, and the clock signal obtained at the output side of this clock recovery circuit (24) is sent to a waveform shaping circuit (24). 23), and the waveform-shaped pi-phase digital signal obtained at the output side of this waveform shaping circuit (c) is supplied to a pi-phase-NRZ conversion circuit (25) that converts the pi-phase signal into an NRZ signal. At the same time, the output signal of this waveform shaping circuit (two senses) is supplied to the synchronization signal extraction circuit (3), and this synchronization signal extraction circuit (2)
6) The synchronization signal obtained on the output side of biphase-NR
Z conversion circuit (supplied to two. This biphase-NR
The NRZ digital signal obtained at the output side of the Z conversion circuit (251) is supplied to a demultiplexer (27) that selects a predetermined channel, and the output signal of this pie-phase-NRZ conversion circuit (25) is used to control the channel number mode. A mode detection circuit (09) which detects the signal C is supplied, and a detection signal of this mode detection circuit (28) is supplied to a demultiplexer (2), and the demultiplexer (09) is controlled according to the channel mode. A channel selection switch is shown for arbitrarily selecting a desired channel, and a selection signal from this channel selection switch (29) is supplied to a demultiplexer (27), which determines the channel to be selected. Supplying the output signal of the demultiplexer (27) to a D-A conversion circuit that converts the digital signal to an analog signal,
The audio signal obtained at the output side of the D-A converter circuit □□□ is supplied to the audio amplifier circuit G via a variable low-pass filter (3I). This variable low-pass filter (311) is configured to switch the cut-off frequency of the output signal of the mode detection circuit (28).
) when the output signal is in 16 channel mode, for example, 5
KHz, 10KHz in 8 channel mode,
In 4-channel mode, the frequency is set to 15 KHz. The audio signal obtained at the output side of this audio amplification circuit (32) is supplied to the headphones (c).

In such a headphone receiver, the light receiving element (6th
As shown in Figure B, multiple channels of differential signals with synchronization bits S1 and serial digital signal of control signal C are received within one frame, and these signals are converted to NRZ by the piephase-NB and Z conversion circuit (25). The desired channel of this serial digital signal is selected using a demultiplexer (2 inputs) while considering the channel mode, and this is converted into an audio signal by a D-A converter circuit (A). Therefore, a desired audio signal selected by the channel selection switch (29) can be listened to through the headphones (3□□□).

In the above-mentioned embodiments, an example was described in which the present invention was used in a simultaneous interpretation device, but it goes without saying that the present invention can also be used in the case of optically transmitting other data signals. Further, the present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations can be made without departing from the gist of the present invention.

Effects of the Invention According to the present invention, the number of channels for optical multiplex transmission can be arbitrarily selected, and the transmission audio frequency band can be changed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an optical multiplex transmission device according to the present invention, and FIGS. 2, 3, 4, 5, and 6 are diagrams for explaining the present invention, respectively. , FIG. 7 is a block diagram showing an example of a headphone receiver according to the present invention. (la) (lb)... (1p) are audio signal input terminals, (3a) (3b) ・= (3p) are A-
D conversion circuit, (4) is a mode switching circuit, (5) is a mode selection switch, (6) is a multiplexer, (7) is a latch circuit, (8) is a clock signal generation circuit, (14) is a decoder, (1) , 6) is a shift-resistor, and (20) is a light emitting diode device. L

Claims (1)

[Claims] The audio signals of multiple channels are A-D converted, the digital signals are time-division multiplexed, and the synchronization bits, the digital signals of predetermined bits of the multiple channels, or the bits of the U channels of the multiple channels are converted into n. An optical multiplex transmission system characterized in that a serial digital signal consisting of a divided digital signal and a discrimination signal of predetermined bits is generated, and a light emitting element is driven and transmitted by the serial digital signal.