JP2967705B2 - Frame synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division multiplex data transmission system, and more particularly to a frame synchronization system.

[0002]

2. Description of the Related Art In a case where data of a plurality of channels having a frame structure is converted from parallel / serial on the transmitting side and transmitted, and serial / parallel converted on the receiving side, if frame synchronization is not achieved at the time of serial / parallel conversion. , A channel exchange (circulation) occurs (for example, an equal channel shift occurs, in which channel 1 data is identified as channel 2 data).

As a method of using different fixed patterns as synchronization patterns of respective channels as a frame synchronization method, Japanese Patent Application Laid-Open No. H4-115734 (Title of Invention:
"Time-division multiplexing converter") is known.

FIG. 5 is a diagram for explaining a method of synchronizing frames in the time division multiplex conversion device described in the above publication. In FIG. 5, 13 is a synchronization pattern adding unit, 14 is a parallel / serial conversion unit (indicated by “P / S”), 15 is a serial / parallel conversion unit (indicated by “S / P”), and 16 is a synchronization pattern detection. Reference numeral 17 denotes a synchronization control unit.

In the method described in the above publication, the synchronization pattern adding section 13 on the transmitting side uses different synchronization patterns (SYN0 to SYN4) for a plurality of channels (ch0 to ch4) for each channel.
Is added, and the parallel / serial conversion unit 14 converts the parallel / serial data and transmits it.

[0006] On the receiving side, frame synchronization is performed with a different synchronization pattern for each channel.

If the serial / parallel converter 15 does not synchronize the frame, the synchronization pattern is not detected by the synchronization pattern detector 16 of each channel on the receiving side.
The synchronization control unit 17 establishes frame synchronization by shifting the frame phase of the serial / parallel conversion unit 15 by one bit until a synchronization pattern is detected in all channels.

[0008]

In the above-mentioned conventional method, frame synchronization can be achieved by using a different fixed pattern for each channel. However, the same number of different synchronization patterns as the number of channels is required. In addition, the circuit scale becomes large, so that the number of channels to be multiplexed is reduced, the power consumption is increased, the size of the device is increased, and the cost is increased.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve such a conventional problem, to reduce the circuit scale and ease the limitation on the number of channels to be multiplexed, to achieve low power consumption, a small device, and a low cost. To provide a frame synchronization method.

[0010]

In order to achieve the above object, the present invention provides a method for transmitting data of a plurality of channels (n channels, where n is a positive integer of n> 2) having a frame structure in parallel /
And transmits the serial conversion, the division multiplexed data transmission when serial / parallel conversion of the received data, dividing the two different frame synchronization pattern for the plurality of channels
The two different frames for each channel
There is provided a frame synchronization method characterized by performing frame synchronization by adding any one of synchronization patterns .

In the present invention, it is preferable that each channel has the above-mentioned structure so that there is no recursiveness among the plurality of channels.
Wherein the allocating the frame synchronization pattern.

[0012] In the present invention, preferably characterized in that the addition of only one channel different frame the <br/> life pattern of the plurality of channels.

Further, according to the present invention, on the transmitting side, a group is constituted by a predetermined number of channels, and a plurality of groups (n groups, where n: n>
2 of the data of a positive integer) a material obtained by adding the pattern <br/> down frame synchronization respectively each further parallel / serial conversion,
The data of a plurality of channels is time-division multiplex-transmitted, the received signal is converted from serial to parallel, a frame synchronization pattern is detected for each of the plurality of groups output in parallel, and the data of the plurality of groups is further processed. serial / parallel conversion to with obtaining data of a plurality of channels, allocated to two different frame synchronization pattern for the plurality of groups, before
The two different frame synchronization patterns for each group
A frame synchronization method characterized by performing frame synchronization by adding any one of the above.

In the present invention, preferably characterized in that allocating the frame the <br/> life patterns in each group so no cyclicity among the plurality of groups.

[0015]

According to the present invention, data obtained by adding two different synchronization patterns to a plurality of channels is transmitted after being subjected to parallel / serial conversion. The receiving side performs serial / parallel conversion of the received data, detects a synchronization pattern, controls the serial / parallel conversion unit based on the detection signal, and achieves frame synchronization.

When the frame synchronization of the serial / parallel conversion is normally performed, the synchronization pattern appearing on each channel on the receiving side is the same as that added on the transmitting side. Channel switching (circulation) occurs (for example, data of channel 0 is changed to channel 1
And so on).

In the present invention, when there is no cyclicity in the allocation of two types of synchronization patterns, the synchronization patterns are detected in all channels only when frame synchronization is normally performed. Accordingly, the frame synchronization of the serial / parallel conversion can be established by shifting the frame phase of the serial / parallel conversion one bit at a time until the synchronization pattern is detected in all the channels.

As described above, according to the present invention, frame synchronization is realized by assigning two types of different patterns as synchronization patterns for each of a plurality of channels. It is sufficient that the pattern detection unit has two types of patterns, and even if the number of channels increases, the number of synchronization patterns is fixed, thereby preventing an increase in circuit scale. In addition, since the increase in the circuit scale is suppressed, the limitation on the number of achievable channels is also eased, and low power consumption, easy downsizing of the device, and cost reduction are achieved.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

[0020]

Embodiment 1 FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In FIG. 1, 1 is a synchronous pattern adding unit, 2 is a parallel / serial converter, 3 is a serial / parallel converter,
Denotes a synchronization pattern detection unit, and 5 denotes a synchronization control unit.

In this embodiment, on the transmitting side, the parallel / serial converter 2 converts 5 channels of data at a transmission speed of 200 Mb / s (200 megabits per second) into 5: 1 parallel / serial, and transmits the data. The data is transmitted as data (serial data) at a speed of 1 Gb / s (1 gigabit per second). On the receiving side, the serial / parallel converter converts the data to 1: 5 serial / parallel and converts 5 channels of 200 Mb / s data Output.

The synchronization pattern adding section 1 generates SY as a synchronization pattern for the 0th, 2nd, and 4th channels ch.0, ch.2, and ch.4.
N0 (“1010”) is added, and the first and third channels ch.
SYN1 (“1100”) is added as the ch.3 synchronization pattern.

The data to which the synchronization pattern is added is subjected to 5: 1 parallel / serial conversion by the parallel / serial conversion unit 2 and transmitted as 1 Gb / s data.

On the receiving side, the received 1 Gb / s data is subjected to 1: 5 serial / parallel conversion by the serial / parallel converter 3 into five channels of 200 Mb / s data, and the synchronous pattern detector 4 detects the synchronous pattern. In accordance with the detection signal, the synchronization controller 5 controls the serial / parallel converter 2 to perform frame synchronization.

In the state where the frame synchronization of the serial / parallel conversion is normally achieved, the synchronization pattern appearing on each channel on the receiving side is the same as that added on the transmitting side, but if the frame synchronization is not achieved, Since the channel exchange (circulation) occurs, as shown in FIG. 2, the appearing pattern is circulated. Fig. 2 shows "normal" with frame synchronization.
It shows a list of patterns detected in each channel in the state and patterns detected when frame synchronization is not achieved.

As can be seen from FIG. 2, in this embodiment, since the allocation of two types of synchronization patterns has no cyclicity, the synchronization pattern detection unit 4 detects the synchronization patterns in all the channels. Is only when frame synchronization is normally achieved. That is, FIG.
As shown in the figure, one channel tour (ch.0 is ch.1 and ch.1 is c.
h.2, ch.4 shifts to ch.0, and so on.
In this embodiment, the frame is not synchronized with any other channel when the ch.1 shifts to the ch.0 and the ch.2 shifts to the ch.1). Is shifted, the channel identification is not performed assuming that frame synchronization is maintained.

Therefore, the synchronization control unit 5 until the synchronization pattern is detected in all the channels by the synchronization pattern detection unit 4.
The frame synchronization of the serial / parallel conversion can be established by shifting the frame phase of the serial / parallel conversion unit 3 bit by bit through the interface (the synchronization pattern shown in the “normal” state in FIG. 2 is detected). Is done).

[0028]

Embodiment 2 FIG. 3 is a diagram for explaining another aspect of the first embodiment. The synchronization pattern of the first embodiment differs from that of the first embodiment in that only one channel out of a plurality of channels is different. This is a description of channel cycling when allocation is performed so as to have a pattern.

Referring to FIG. 3, in the present embodiment, the synchronization pattern added to ch.0 by synchronization pattern adding section 1 is SYN0.
(“1010”), and the synchronization pattern to be added to the other channels ch.
0 ”).

Also in this embodiment, since the synchronization pattern is not cyclically allocated, the synchronization pattern is detected in all channels only when frame synchronization is normally performed. Accordingly, the frame synchronization of the serial / parallel conversion can be established by shifting the frame phase of the serial / parallel converter 3 one bit at a time until the synchronization pattern is detected in all the channels by the synchronous pattern detector 4. .

[0031]

Embodiment 3 FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention. In FIG. 4, 6 is a parallel / serial converter, 7 is a synchronous pattern adding unit, 8 is a parallel / serial converter,
Reference numeral 9 denotes a serial / parallel converter, 10 denotes a synchronous pattern detector, 11 denotes a serial / parallel converter, and 12 denotes a synchronous controller.

In the present embodiment, the parallel / serial converter 6 converts data of a transmission rate of 50 Mb / s for 20 channels (ch. 0 to ch. 19) every four channels (four channels form one group). 4: 1 parallel / serial conversion, ie, 20: 5 parallel / serial conversion and transmission speed
200Mb / s serial data, synchronous pattern adding unit 7
To add a synchronization pattern.

The synchronization pattern adding section 7 converts the 0th channel group ch.0 to ch.3 from parallel / serial to # 0 (0th group),
Channel group ch.8 to ch.11 are converted from parallel / serial to # 2 (second
SYN0 (“1010”) as the synchronization pattern of # 4 (fourth group) obtained by parallel / serial conversion of the fourth channel group ch.16 to ch.19
And # 1 (first group) obtained by parallel / serial conversion of the first channel groups ch.4 to ch.7, and # 3 (first group) obtained by parallel / serial conversion of the third channel groups ch.12 to ch.15 In group 3), SYN1 (“1100”) is added.

The data of 200 Mb / s to which the synchronization pattern is added is converted by the parallel / serial converter 8 to 1 Gb / s at a ratio of 5: 1 parallel / serial and transmitted. On the receiving side, the received 1 Gb / s data is subjected to 1: 5 serial / parallel conversion by the serial / parallel converter 9 to 200 Mb / s, and the synchronous pattern detector 10 detects the synchronous pattern.

In this embodiment, as in the first embodiment, there is no cyclicity in the allocation of two types of synchronization patterns, so that the synchronization pattern detection unit 10 detects the synchronization patterns in # 0 to # 4. Only when the serial / parallel converter 9 normally synchronizes the frames. Therefore, the synchronization control unit 12 shifts the frame phase of the serial / parallel conversion unit 9 by one bit at a time until the synchronization pattern is detected at # 0 to # 4 by the synchronization pattern detection unit 10 to obtain 1 Gb / s.
Frame synchronization for serial-to-parallel conversion from Mbps to 200 Mb / s can be established.

In the synchronous pattern detecting section 10, # 0 to # 0
By resetting the serial / parallel converter 11 once at the timing when the synchronization pattern is detected in # 4, the channel ch.
~ Ch.19 frame synchronization can be achieved.

According to the above embodiment, it has been described in detail that the frame synchronization at the time of serial / parallel conversion can be achieved by using two different patterns as the synchronization pattern of each channel. It is not limited only to the embodiment. For example, in the above embodiment, the case where the transmission speed of the parallel input data is 200 Mb / s has been described, but the transmission speed of the parallel input data is 100 kb / s or 1 Gb / s, regardless of the transmission speed of the parallel input data. The invention is applicable.

In the above embodiment, the frame synchronization in the case of five channels has been described.
The present invention is applicable regardless of the number of channels, even if the number of channels is 20. Further, in the above embodiment, the case where the transmission speed of the parallel / serial converted data is 1 Gb / s is described. However, the present invention can be applied regardless of the transmission speed of the serial data at 10 Mb / s or 10 Gb / s. It is.

In the above embodiment, the 4-bit patterns "1010" and "1100" are used as the synchronization patterns. However, when the synchronization patterns are "10101" and "11100",
Even in the case of “100001” or “101010”, the present invention can be applied without depending on the pattern and the number of bits.

The present invention is applicable to transmission lines not only electric cables such as coaxial cables and paired cables, but also to optical fiber cables and wireless transmissions regardless of the transmission path.

Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the above embodiment, but includes various embodiments according to the principle of the present invention.

[0042]

As described above, in the present invention,
By using two different patterns as the synchronization pattern of each channel, frame synchronization at the time of serial / parallel conversion can be achieved, so that the circuit scale is small, the limitation on the number of multiplexed channels is relaxed, low power consumption and small size The apparatus can realize a low-cost frame synchronization system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of one embodiment of the present invention.

FIG. 3 is a diagram illustrating an operation of a modification of the embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration example of a conventional frame synchronization method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Synchronization pattern addition part 2 Parallel / serial conversion part 3 Serial / parallel conversion part 4 Synchronization pattern detection part 5 Synchronization control part 6 Parallel / serial conversion part 7 Synchronization pattern addition part 8 Parallel / serial conversion part 9 Serial / parallel conversion part 10 Synchronization pattern detector 11 Serial / parallel converter 12 Synchronization controller 13 Synchronization pattern adder 14 Parallel / serial converter 15 Serial / parallel converter 16 Synchronization pattern detector 17 Synchronization controller

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04J 3/06 H04L 7/08

Claims (5)

(57) [Claims] 1. Time-division multiplexing in which data of a plurality of channels (n channels, where n is a positive integer satisfying n> 2) having a frame structure is converted from parallel / serial and transmitted, and received data is converted into serial / parallel. in data transmission, two different frame synchronization for said plurality of channels
Assign the use pattern, the two said each channel
A frame synchronization method characterized by performing frame synchronization by adding any one of different frame synchronization patterns . 2. A frame synchronization method of claim 1, wherein the allocating the frame synchronization pattern in each channel so no cyclicity among the plurality of channels. 3. A frame synchronization method of claim 1, wherein the only added different frame synchronization pattern 1 channel among the plurality of channels. 4. A plurality of groups (n groups, where n> 2), on the transmitting side, forming a group with a predetermined number of channels, performing parallel / serial conversion for each group, and serially outputting. positive integer) data and each further parallel / serial conversion those obtained by adding a frame synchronization pattern each transmits time division multiplexed data of a plurality of channels, the receiving side, the received signal series / parallel conversion, parallel detecting a frame synchronization pattern <br/> emissions for each of the output plurality of groups, together with obtaining the data of a plurality of channels and further serial / parallel conversion of data of a group of plurality of, against the plurality of groups Two different types of frame synchronization patterns, and for each group, the two different types of frame synchronization .
A frame synchronization system characterized in that any one of frame synchronization patterns is added to perform frame synchronization. 5. A frame synchronization method according to claim 4, wherein the allocating the frame synchronization pattern in each group so no cyclicity among the plurality of groups.