KR960009901B1 - Signal transmission apparatus for multi-channel system - Google Patents

Abstract

an analog switch unit(1); multiplexers(2,3); A/D converters(4,5); a parallel/serial converter(6); a control unit(7); a differential transmitting unit(8) for data transmission; a synchronization clock generating unit(9); a differential transmitting unit(10) for clock transmission; a reference clock generator(11); a frequency demultiplicating circuit(12); a channel selector(13); a frame detector(14); a delay circuit(15); a reset circuit(16). Wherein A/D converters are alternatively operated in order to speed up transmission rate of the system.

Description

Multi Channel Signal Transmitter

1 is a circuit diagram of the present invention.

2 is a time chart according to the invention.

* Explanation of symbols for main parts of the drawings

1: Analog Switch 2, 3: First, Second Multiplexer

4, 5: first and second analog / digital converters (A / D converters)

6: parallel / serial conversion unit 7: control unit

8: differential transmitter for data transmission 9: sync clock generator

10: differential transmitter for clock transmission 11: reference clock generator

12: frequency divider circuit 13: channel selector

14 frame detection unit 15 delay circuit

J ₀ to J ₁₆ : Jack CH ₁ to CH ₁₆ : Each channel signal

AD ₀ : Multiplexer selection signal AD ₁ ~ AD ₃ : Channel selection signal

BF ₁ : Buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-channel signal transmission apparatus, and more particularly, to a multi-channel signal transmission apparatus for converting several analog signals into digital signals and then transmitting them in a time division manner using PCM communication.

In general, train passenger information system, express bus passenger information system, language education system, guard room interphone, music listening system such as rest room or sauna, and aircraft passenger information system send signals output from multiple signal sources through multiple channels. In addition, the user was to select the desired channel to receive the necessary information from among them to listen to the information.

For example, the signal source is composed of announcement broadcasts, various information, broadcast signals of various broadcasting stations, separate music broadcasts, voice multiple broadcasts, language broadcasts, etc., which are to be transmitted according to the system. It was intended to be output simultaneously through the channel.

However, when the analog transmission method is selected when transmitting a plurality of signals simultaneously through several channels as described above, impedance matching with the load side is essential, there is a transmission loss on the output line, and is directly affected by external noise of the line. Of course, there is a problem in that the circuit configuration is complicated and the output characteristics are not good as the transmission source is doubled when the signal source is increased because two lines are required for each channel during transmission.

In addition, when the modulation / demodulation method is adopted, only the increase and decrease of the signal are distinguished, thereby reducing the transmission speed per unit time and complicating the peripheral circuit.

The present invention has been invented to improve the above-mentioned problems, and in order to simplify the circuit configuration and increase the transmission speed, convert an analog signal input from several signal sources into a digital signal and convert it into an 8-bit serial data signal. In order to provide a multi-channel signal transmission device to transmit a 4-bit channel information signal that can distinguish each channel with the serial data signal, that is, the audio signal during transmission to select each channel in a two-line state The other purpose is to increase the transmission speed by adopting the multi conversion method when converting the analog signal into the digital signal, and the other purpose is to provide emergency guidance through each channel in case of emergency announcement broadcasting. The purpose is to provide a multi-channel signal transmission device for transmitting a broadcast. All.

Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the accompanying drawings.

An analog switch unit 1 and first and second multiplexers 2 and 3 are respectively connected to the input jacks J ₀ to J ₁₆ of each signal source, and the first and second multiplexers 2 and 3 are respectively connected. The parallel / serial converter 6 is connected to the output terminal of the first and second A / D converters 4 and 5, and the first and second A / D converters 4 and 5 The control unit 7 is connected to the A / D conversion completion signal output terminal INT of the control unit via an OR gate OR ₁ , and the data of the parallel-to-serial conversion unit 6 is connected to the inverting output terminal Q of the control unit 7. The load terminal S / L is connected to the differential transmission unit 8 for data transmission via the buffer BF ₁ , and the synchronization clock generation unit 9 and the buffer () are connected to the output terminal Q of the control unit 7. The differential transmission unit 10 for clock transmission is connected through the BF ₁ , while the first and second multiplexers 2 are connected to the frequency division circuit 12 and the channel selector 13 which are sequentially connected to the reference clock generator 11. (3) is connected and the frame detection unit 14 and the delay circuit 15 in sequence A transmitter (8) 10 is connected and the clear terminal of the synchronization clock generating unit 9 and the frequency divider circuit 12 and a channel selection unit 13 has been attached to the structure initialization reset circuit 16.

Reference numeral 16 denotes a reset circuit, 17 denotes a T-flip flop, and 18 and 19 denote counters.

1 shows a circuit diagram of the present invention. Here, the jack J ₀ , which is a signal input terminal of one of several signal sources, is an emergency announcement broadcast input terminal, and the jacks J ₁ to J ₁₆ are terminals to which an output signal from a signal source can be input. Is indicated so that it can be input, but this can be increased or decreased within the scope of the present invention without changing the subject matter, if necessary, two jacks are used, for example, jack (J ₁ ) The left signal is input to Jack (J ₉ ), and the right signal is input to jack (J ₉ ), and the analog signal of each channel (CH ₁ to CH ₁₆ ) input to jack (J ₀ to J ₁₆ ) corresponds to the data bus. It is connected to be input to the multiplexer (2) (3).

The multiplexer 2 and 3 are selected when the multiplexer selection signal AD ₀ output from the channel selector 13 is at a low level. The multiplexer 2 and 3 are input to an input terminal of the second multiplexer 3 through an inverter IV ₁ . The first multiplexer 2 and the second multiplexer 3 are configured to be alternately selected, and each multiplexer 2 and 3 are each 8 according to the channel selection signals AD ₁ to AD ₃ . Each channel signal CH ₁ to CH ₁₆ composed of bits is sequentially outputted to each of the first and second A / D converters 4 and 5 alternately.

The parallel-to-serial converter 6 converts 8-bit parallel data signals of each channel input from each of the first and second A / D converters 4 and 5 into serial data signals for data transmission through a buffer. The differential transmitter 8 is used for long-distance transmission, which transmits an input signal through its output stage (Q), but through its inverted output stage (Q). By inverting and outputting the signal, the receiving unit can accurately receive the original signal using these two signals.

On the other hand, the division circuit 12 is configured to output the clock signal output from the reference clock generator 11 to the channel selector 13 by 12 minutes, which is an 8-bit data signal and a 4-bit channel separation signal. Are combined to form one channel signal as 12 bits, and 16 channels signals (CH ₁ to CH ₁₆ ) are combined to form one frame. One channel signal is transmitted per reference clock signal.

In addition, in the present invention, after transmitting ₁₆ channel signals CH ₁ to CH ₁₆ , one frame signal is transmitted, which is transmitted once to each channel signal CH ₁ to CH ₁₆ and then again the first channel signal ( In order to transmit the data from CH ₁ ), when 16 channels are selected once in the channel selector 13 having a 16-bit counter, the data signal from the frame detector 14 to the 8th reference clock of the 16th channel is received. Delayed circuit 15 outputs a frame signal of one square wave pulse to the differential transmission unit 8 for data transmission through delay circuit 15 at the 9th reference clock time of the 16th channel. The frame signal before it is outputted to the differential transmission unit 10 for clock transmission.

Here, the delayed frame signal is transmitted through the differential transmission unit 8 for data transmission and the frame signal before the delay is transmitted through the differential transmission unit 10 for clock transmission in the multi-channel signal receiving apparatus of the present invention. In order to accurately identify the frame and channel, the identification method is beyond the scope of the present invention, and thus will be omitted here.

Referring to the operation of the present invention made as described above in more detail based on the time chart of FIG.

First, when the power is turned on, the counter 19 of the frequency dividing circuit 12 and the counter of the channel selector 13 and the synchronous clock generator according to the reset signal output from the output terminal Q (Q) of the reset circuit 16 ( After the counter 18 of FIG. 9 is reset, the operation starts according to the reference clock (the OSC output of FIG. 2) output from the reference clock generator 11. In the division circuit 12, one clock is input to the clock terminal CK of the channel selector 13 whenever 12 reference clocks are input.

Accordingly, the channel selector 13 counts one bit per 12 bits of the reference clock, counts up to 16 bits, and counts again from the beginning. At this time, the output terminal Q ₀ repeats 0 and 1 as shown in AD ₀ of FIG. The first and second multiplexers 2 and 3 which are operated when the signal is at the low level are alternately selected, and are outputted at the output terminals Q ₁ to Q ₃ of the channel selector 13. The channels are sequentially selected according to the channel selection signals AD ₁ to AD ₃ . Thus, the first channel CH _{1 as} the first channel of the first multiplexer 2, the ninth channel CH _{9 as} the first channel of the second multiplexer 3, and the second channel as the second channel of the first multiplexer 2. The second channel CH ₂ is sequentially selected to the sixteenth channel CH ₁₆ , which is the last channel of the second multiplexer 3. The channel signal selected in this way is input to the A / D converter 4 (5) when the recording terminal WR of the A / D converter 4 (5) is low and the recording terminal WR is switched high. Is converted from an analog signal to a digital signal.

That is, when the AD ₀ signal is low, the channel signal output from the first multiplexer 2 is input to the first A / D converter 4, and when the AD ₀ signal is turned high, the first A / D converter ( In 4), the first inputted channel signal is converted into a digital signal. At this time, since the low signal is inputted by the inverter IV ₁ from the recording terminal WR of the second A / D converter 5, the second multiplexer 3 The channel signal output from is input.

When the AD ₀ signal goes low again, the first channel signal is input by the first A / D converter 4 and the second multiplexer 3 converts the first channel signal into a digital signal.

In this way, the signal converted from the analog signal to the digital signal is output from the parallel-serial converter 6 to the differential transmitter 8 for data transmission through the buffer BF ₁ according to the clock signal input thereto. As described above, the differential transmitter 8 transmits the serial voice signal input from the parallel-serial converter 6 through the output terminal Q as it is, and the parallel-serial conversion through the inverted output terminal Q. The serial audio signal input from the unit 6 is inverted and transmitted.

Meanwhile, the A / D conversion completion signals outputted from the terminals INT of the first and second A / D converters 4 and 5 are the first and second A / D converters as shown in FIG. (4) (5) Occurs when A / D conversion is completed, that is, one pulse is output per 12 bits of the reference clock and input to the data terminal A of the controller 7 through the ORA gate OR ₁ . The output terminal Q is then input to the terminal S / L of the parallel-to-serial conversion section 6 so that the parallel-to-serial conversion section 6 can be used for the first and second A / D conversion sections 4 and 5 respectively. By converting the parallel signal input from the serial signal into a serial signal to the differential transmission unit 8 for data transmission through the buffer (BF ₁ ) and at the same time the signal output from the output terminal (Q) of the control unit 7 is synchronized The input of the output terminal Q of the T-flop flop 17 is made high through the orifice OR ₂ of the clock generator 9 to make the output of the AND gate AND high. there is outputted a ₁₎ At this time, the gate of the AND (AND ₁₎ Since one input terminal of the reference clock from the reference clock generation unit 11 is input to the output of the AND gate (AND1), the reference clock is output.

The reference clock is outputted to the receiver along with the data transmitted from the differential transmitter 10 for clock transmission through the buffer BF2 to the receiver and at the same time, the coefficient increasing terminal UP of the 16-bit counter 18 is output. The counter 18 increases by increasing the counter 18.

The output terminals Q ₀ to Q ₂ of the counter 18 are tied to the AND gate AND ₂ , and are connected to the clock terminal of the T-flip flop 17 through the ora gate OR ₂ , and thus the AND gate AND ₁ . When eight reference clocks are sent to the buffer (BF ₂ ), the outputs (Q ₀ to Q ₂ ) of the counter 18 are all high, and the T through the AND gate (AND ₂ ) and the OR gate (OR ₂ ) in turn. One pulse is input to the clock end of the flip flop 17.

As a result, the output terminal of the T-flip flop 17 drops low so that the clock transmitter 10 does not transmit any more clocks through the buffer BF ₂ .

Then, when one channel is finished from the controller 7 and the generated pulse is inputted to the clock through the OR gate OR ₂ , the output terminal of the T-flop flop 17 becomes high again and the reference clock is applied to the AND gate AND ₁ . The reference clock input from the generation unit 11 is sent to the differential transmission unit 10 for clock transmission through the buffer BF ₂ . This operation is repeated while all 16 channels are transmitted once, that is, during one frame period as shown in FIG.

The following describes the operation of transmitting a frame signal after the transmission of one frame as described above.

Since the channel selector 13 is composed of a 16-bit counter, it counts up to 16, i.e., 0 is output from the output terminals Q ₀ to Q ₃ at the 16th channel. Accordingly, a high signal is output from each of the NOR gates NOR ₁ and NOR ₂ , and a high signal of the second gate is output from the AND gate AND ₃ . The synchronous clock generating section 9, the output terminal (Q ₃₎ of the counter 18 in the output, the following high signal as the second assist the end of the data transmission period of the up to 16 channels of the ninth bit, i.e., 8-bit-and- It is input to the gate AND ₄ and remains high until the next first channel is started. Thus, the high signal of the AND gate AND ₄ is transmitted to a separate receiver through the differential transmitter 10 for clock transmission.

At the same time, the high signal output from the AND gate AND ₄ is slightly delayed by the inverter IV ₂ (IV ₃ ) (t time in FIG. 2), and then the differential transmitter for data transmission through the AND gate AND ₅ ( 10) is sent out. As such, the frame signal detected by the frame detector 14 is immediately transmitted through the differential transmission unit 10 for clock transmission, while being delayed for 5 hours and then transmitted through the differential transmission unit 8 for data transmission. It is used to classify frames in a receiving apparatus for receiving a voice signal transmitted from a signal transmitting apparatus, and the detailed description is omitted since the present invention does not belong to the scope.

The following describes the emergency guidance function.

Normally, different analog audio signals are inputted to each channel input, but in case of emergency or uninterested broadcasting, press the switch (SW) connected to the analog switch unit (1) for emergency guidance broadcast input jack on all channels of the analog switch unit (1). The analog switch unit 1 is operated to output the emergency announcement broadcast inputted from J ₀ .

As described above, since the present invention can transmit a multi-channel signal in a time division manner, the circuit configuration is simplified and the transmission speed is high.

Claims (2)

An analog switch unit 1 and first and second multiplexers 2 and 3 are respectively connected to the input jacks J ₀ to J ₁₆ of each signal source, and the first and second multiplexers 2 and 3 are respectively connected. The parallel-to-serial converter 6 is connected to the output terminal of the first and second A / D converters 4 and 5, and the first and second A / D converters 4 and 5 The control unit 7 is connected to the conversion completion signal output terminal INT via an OR gate OR ₁ , and the parallel-to-serial conversion unit 6 is connected to the inversion output terminal Q of the control unit 7. S / L is connected to the differential transmission unit 8 for data transmission through the buffer BF ₁ , and the synchronization clock generation unit 9 and the buffer BF ₂ are connected to the output terminal Q of the control unit 7. The differential transmission unit 10 for clock transmission is connected via the first and second multiplexers 2 and 3 to the frequency division circuit 12 and the channel selector 13 which are sequentially connected to the reference clock generator 11. ) Is connected and through the frame detection unit 14 and the delay path 15 in order The differential transmitters 8 and 10 are connected, and the initialization reset circuit 16 is connected to the clear terminal of the synchronous clock generator 9, the frequency divider circuit 12 and the channel selector 13. Channel signal transmitter. The multi-channel signal transmission apparatus according to claim 1, wherein the first and second A / D conversion units (4) (5) are alternately A / D converted to increase transmission speed.