JPS59111532A - Data sorting method - Google Patents

Abstract

PURPOSE:To increase the data quantity to be handled without increasing the processing capacity of a central processor by using a means which reads out in parallel the memory contents of a memory every plural data names and decodes the contents of the memory. CONSTITUTION:The contents of a memory are read out in parallel every plural data names, and the contents of the memory are decoded to detect an address where the data is stored. For instance, the address signals sent from a counter 22 are supplied in parallel to memories 141-156, and the memory contents of the areas corresponding to the supplied address signals are supplied to a priority encoder 157. The output of the encoder 157 is supplied to a memory 13 as well as decoder 158. Then an enable signal is supplied to the decoder 158 from a central processor 23, and the output signals of the decoder 158 are supplied to memories 141-156 to perform writing corresponding to the address signal. When the memories 141-156 deliver plural signals, an output corresponding to the terminal of the youngest number is delivered from the encoder 157.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data sorting method for arranging a large number of numerical data in the order of the largest value or the smallest value represented by the data, and is applicable to a simulated visibility generating device for pilot training, etc. It is suitable for use.

Generally, a simulated visual field generating device reads data stored in a memory and displays it on a display screen of a monitor. In this case, as shown in FIG. 1, when two triangle figures are to be displayed, the data of left corner figure 1 and triangle figure 2 are read out from memory separately and stored in a frame memory, and the contents of this frame memory are Display is performed by reading out in synchronization with scanning. In this case, the data for displaying the image on scan 11!3 in FIG. 1 needs to be stored in the frame memory in the order of 1m, 2m, 2b, and 1b. However, data for each figure is written in the memory that stores the figures, so in order to store this data in the frame memory, the data read from the memory must be rearranged in address order.
It is necessary to store it in frame memory. Data sorting is performed to rearrange data in the order of its values.

For this reason, data has conventionally been rearranged using the following method. First, data for rearranging is sequentially stored in a memory. At this time, the order in which the data is stored in the memory is the order in which the data to be stored is supplied, and the address at which the data is stored is stored in the memory for address storage.

Some data that is supplied sequentially may have the same content as data that has already been stored, so in this case, the data that will be supplied later is stored in the save memory, and the data that is supplied later is stored in the save memory. The address in which the data was stored is also stored in the address storage memory. After all data has been stored, the stored data is read out in a predetermined order according to the contents of the address storage memory.

FIG. 2 is a block diagram showing an example of a data sorting device to which a conventional method is applied. In the same figure, 11~
15.17 to 21 are memories, and 16.22 is a counter. The memory 11 is used as a data memory in which numerical data to be sorted is written, and the memory 12 is used as a name memory in which name data given to the numerical data written in the memory 11 is written. When displaying a figure on a computer, the address on the cathode ray tube corresponds to numerical data, and the color and brightness correspond to name data. Memory 1 as the first memory
Reference numeral 3 is a memory for temporarily storing data names for sorting, and the data names are written to addresses corresponding to data values.Memory 14 as a second memory stores data names in the memory 13. This is a memory that stores information that has been written.

It is possible that the same data value as the one that occurred once will occur later, and in this case, the data value will be used as the address and
The data name generated later is written into the memory 19 as a memory. At this time, the data names written in the memory 19 are read out for each data name corresponding to the same data value, as will be described later. Therefore, the memory 15 stores the address in the memory 19 at which the first name written in the memory 19 among data names corresponding to the same data value is written.

A counter 16 as a first counter generates an address for writing data names into the memory 19, and a counter 22 as a second counter determines the order of data names to be read.

The memory 17 stores that a plurality of data names corresponding to the same data value are written in the memory 19, and the memories 14, 15.1F, 18.1ura, and 21 store the data written in the memory 19. This is a memory that stores which address a name is located at.

A central processing unit 23 serves as a processing unit and performs data transfer processing between each memory and counter.

1 and b are lines for outputting data names and data values.

A device having such a VC configuration is controlled by a central processing unit, and data to be processed is once written to a memory within the device and then sequentially read out.

The operation at the time of writing will be explained using the flowchart of FIG. 3 and the operation explanatory diagram of FIG. 4. In FIG. 4, symbols .about.0 indicate the order in which data in the memories 11 and 12 are read.

Initially, as shown in FIG. 4, the value "2" of the data stored in the memory 11 and the name "A" of the data stored in the memory 12 are written. A first operation is performed in which the data value "2" is read from the memory 11 according to step 100 in FIG. 3, and the data name "i" is read from the memory 12 according to step 1 old. Then, in step 102, a first determination is made as to whether "1" is written in the address portion indicated by the data read from the memory 11 among the stored contents of the memory 14. The value is "2"
Yes, since nothing has been written to address 2 of the memory 14, it is "0", so the determination result is [NOJ], and the flow moves to step 103. In step 103, the name of the data read from memory 12 is written into memory 13. At this time, the address of memory 13 is
The value that matches the value indicated by the data read from is used. Therefore, "i" is written in address 2 of the memory 13, and the flow moves to step 104. Step 10
At step 4, "1" is written to the value indicated by memory 11 among the addresses of memory 14, that is, address 2 at this time, and the flow returns to step 100.

As a second operation, as shown in steps 100 and 101, the data ``1'' is read from the memory 11, and the data name ``口'' is read from the memory 12. Next, a judgment is made in step 102, but since nothing has been written to address 1 in the memo January 4 yet, the judgment result is "NO", and according to steps 103 and 104, the memory 13 The data name "mouth" is written to address 1 of the memory 14, "1" is written to address 1 of the memory 14, and the flow returns to step 100.0 As the third operation, the data value "3" is written from the memory 11. ,
The data name "c" is read out, and step 102 is "NO".
”, the data name “c” is written in address 3 of the memory 13 according to step 103, and step 10
4, "1" is written to address 3 of the memory 14, and the flow returns to step 100.

For the fourth operation, data value "3" and data name "2"
is read out, but at this time address 3 of memory 14 is 3.
Since "1" has already been written in the second operation,
The determination result is YESJ, and the flow moves to step 105, which is the second determination. In step 105, since nothing is written in the memory 17 at this time, the determination result is "NO".As shown in step 106, the value indicated by the counter 16 is stored at address 3 of the memory 15, and at this time, "0" is written. Then, as shown in step 107, "1" is written to address 3 of the memory 17, and as shown in step 108, the value "0" indicated by the counter 16 is written to address 3 of the memory 18. Thereafter, as shown in step 109, the content "2" indicated by the memory 12 is written to the address O of the memory 19, and in step 11
As shown in 0, the counter 16 counts up and becomes ``1''.
"become.

At this time, in step 111, the value of the counter 16 is
A determination is made as to whether or not the count has reached a predetermined count. In this embodiment, as shown in FIG.
Since 11 data names are written, 11 is used as the predetermined count number. Therefore, step 111 is rN
OJ is determined, and the flow returns to step 100.

For the fifth operation, data value "4" and data name "Ho"
is read out, the determination in step 102 is "NO", the data name "ho" is written in address 3 of the memory 13 in accordance with step 103, and the data name "E" is written in address 3 in the memory 13 in accordance with step 104.
4 is written to address 4, and the flow returns to step 100.

As the sixth operation, "1" is transferred from memory 11 to memory 1.
"to" is read from 2. Then, it is determined that step 102 is "YES" and step 105 is rNOJ, and the flow advances to step 106. In step 106, the value "1" of the counter 16 at this time is written to the address 1 of the memory 15, and in the next step 107, "1" is written to the address 1 of the memory 17, and then in step 108, the value "1" of the counter 16 is written to the address 1 of the memory 15.
The value "1" of the counter 16 is written to the address 1 of the counter 8. Then, in step 109, "to" is written in address 1 of memory 19, and in step 110, counter 1 is written.
The value of 6 is counted up from "1" to "2", step 111 is determined as "NOJ", and the flow returns to flow 100.

As the seventh operation, the data value "3" and the data name "G" are read in steps 100 and 101, both of steps 102 and 105 are determined to be rYEsJ, and in step 112 the value "0" of address 3 of the memory 1B is read.
" is read out, and the value "2" indicated by the counter 16 is written to address O of the memory 20 in step 113.

Next, in step 114, "1" is written to address 0 of the memory 21, and in step 115, "1" is written to address 0 of the memory 21.
The data name "g" is written to address 2 of . Then, in step 116, the value "2" indicated by the counter 16 is written to address 3 of the memory 18, and in step 110
At this point, the value of the counter 16 is counted up from "2" to "3". Next, step 111 is determined to be rNOJ, and the flow returns to step 100.

As the eighth operation, the data value "1" and the data name "chi" are read out in steps 100 and 101, both of steps 102 and 105 are determined to be rYESJ, and in step 112 the value "1" of address 1 of the memory 18 is read out.
" is read out, and the value "3" indicated by the counter 16 is written to address 1 of the memory 20 in step 113.

Next, in step 114, "1" is written to address 1 of the memory 21, and in step 115, "1" is written to the address 1 of the memory 21.
The data name "chi" is written to address 3 of . Then, in step 116, the value "3" indicated by the counter 16 is written to address 1 of the memory 18, and in step 110
At this point, the value of the counter 16 is counted up from "3" to "4". Next, step 111 is determined to be rNOJ, and the flow returns to step 100.

As the ninth operation, the data value "3" and the data name "su" are read at step 100.101, and both steps 102 and 1050 are determined to be ryEs J.
In step 112, the value of address 3 in memory 18 is “
2" is read out, and in step 113, the value "4" indicated by the counter 16 is written to address 2 of the memory 20. Next, in step 114, the address 2 of the memory 21 is
``1'' is written to ``1'', and in step 115, the data name ``su'' is written to address 4 of the memory 19. Then, in step 116, the address 3 of the memory 18 is
The value "4" indicated by the counter 16 is written in step 1.
At step 10, the value of the counter 16 is counted up from "4" to "5". Next, step 111 is "NO"
If so, the flow returns to step 100.

As the tenth operation, the data value "3" and the data name "NU" are read out in steps 100 and 101, and both steps 102 and 105 are determined to be rYEsJ, and in step 112, the value "4" at address 3 of the memory 18 is read. is read out, and in step 113 the memory 20
The value "5" indicated by the counter 16 is written to address 4 of . Next, in step 114, "1" is written in address 4 of memory 21, and in step 115, the data name "nu" is written in address 5 of memory 19. Then, in step 116, address 3 of memory 1B
The value "5" indicated by the counter 16 is written in step 1.
At step 10, the value of the counter 16 is counted up from "5" to "6". Next, step 111 is “NO.
” and the flow returns to step 100.

As the 11th operation, data "3" and data name "ru" are read out in steps 100 and 101, and both steps 102 and 1050 are determined to be rYEsJ.
In step 112, the value of address 3 of the memory 18 is “
5" is read out, and in step 113, the value "6" indicated by the counter 16 is written to address 5 of the memory 20. Next, in step 114, the address 5 of the memory 21 is
"1" is written to the memory 1 in step 115.
The data name "RU" is written to address 6 of 9. Then, in step 116, the value "6" indicated by the counter 16 is written to address 3 of the memory 1B, and in step 11
At 0, the value of the counter 16 is counted up from "6" to "7". Next, a determination is made in step 111, and since reading is performed 11 times, 11 is set in advance as the predetermined number of times. The flow shown in the figure is completed, and writing of the data stored in the memory 11 and memory 12 is completed.Next, the read operation will be explained using the operation explanatory diagram in FIG. 4 and the flowchart in FIG. 5.0 First, step At 200, a determination is made whether counter 22 is displaying a predetermined number of times. Here, as will be described later, the counter 22 is a counter that counts up once for each reading cycle, and the predetermined number of times is the number of times that is one value larger than the type of data value written to the memory 11.

In this embodiment, since the type of data value is 4, the predetermined number of times is set to 5. Since the counter 22 is initially "0", the determination in step 200 is "NO", and the flow proceeds to the next step 201.

In step 201, a third determination is made as to whether "1" is written in the address indicated by the counter 22 among the data in the memory 14. Since the counter 22 initially indicates "0", as shown in FIG. 4, the address O of the memory 14 is blank and indicates O, so the determination result is rNOJ.
The flow then proceeds to step 202. Step 202
Then, the counter 22 is incremented by 1 and the count value is set to ``1''.
” and the flow returns to step 200.

In the second read, step 200 is determined to be rNOJ, and since "1" is written in address 1 of the memory 14 as shown in FIG. move on.

In step 203, an operation of writing "0" to the address indicated by the counter 22 of the memory 14 is performed, so rOJ is written to address 1 of the memory 14, and the flow advances to step 204. In step 204, the contents of the address indicated by the counter 22 among the data in the memory 13 and the contents of the address indicated by the counter 22 are stored.
Output the contents of 2. As a result, the data "mouth" at address 1 in the memory 13 and the value "1" indicated by the counter 22
is output, and the flow proceeds to step 205. In step 205, a fourth determination is made to determine whether or not the address "1" indicated by the counter 22 has been written in the data in the memory 17. From FIG. 4, the address 1 in the memory 17 is "1". The determination is rYESJ, and the flow advances to step 206. This is the second readout, and in this readout, the name of the data [town] and the data value "
1" is read out.

The third reading starts from step 206.

In step 206, rOJ is written to the address indicated by the counter 22 in the memory 17. Therefore, "0" is written to address 1 of the memory 17, and the flow returns to step 20.
Proceed to step 7. In step 207, the contents of the address indicated by the counter 22 among the contents of the memory 15 are set in the counter 16. Therefore, "1", which is the data at address 1 of the memory 15, is set in the counter 16, and the flow advances to step 208.

In step 208, the data at the address indicated by the counter 16 is read out of the data in the memories 19-21. Since the counter 16 is set to "1", the memories 19 to 2
Data at address 1 in 1 [toJ, r3J, rlJ
is read and the flow proceeds to step 209. In step 209, the contents of memory 19 and counter 2 are
Since the contents of 2 are output, the contents ``to'' read from the memory 19 and the contents ``1'' of the counter 22 are output, and the flow advances to step 210.

In step 210, counter 1 is selected from among the contents of memory 21.
A fifth determination is made to determine whether the content of the address indicated by 6 is "1", but since the address 1 of the memory 21 is "1", the determination at step 210 is ryEs.
, 1, the flow proceeds to step 211. This is the third readout, and in this readout, the data name "to" and the data value "1" are read out.

The fourth reading is performed from step 211.

In step 211, "0" is written to the address indicated by the counter 16 of the memory 21, so "0" is written to the address 1 of the memory 21, and the flow advances to step 212. In step 212, the content of the address indicated by the counter 16 among the data in the memory 20 is set in the counter 16. At this time, since the counter 16 is "1", the content "3" of address 1 of the memory 20 is set to the counter 16, so the counter 16 indicates "3" and the flow advances to step 213.

In step 213, counter 1 of memories 19 to 21 is
Since the contents of the address indicated by 6 are read, memories 19 to 2
1, data "chi", [OJ, rOJ at address 3 are read out, and the flow advances to step 214. Step 2
At step 14, among the contents of the memory 19, the contents of the address indicated by the counter 16 and the contents of the counter 22 are output. Therefore, the contents of address 3 of memory 19 "chi" and counter 22
The content "1" is output, and the flow returns to step 210. In step 210, the counter 16 of the memory 21 is
It is determined whether "1" is written in the address indicated by , but address 3 of the memory 21 is "0" from FIG.
Therefore, the determination is "NO" and the flow returns to step 202. The reading up to this point is the fourth reading, and the data name "chi" and the data value "1" are read out.

Then, in step 202, the counter 22 is incremented by 1, so the content of the counter 22 changes from 1 to 2, and the flow advances to step 200. At this stage, the counter 22 has not reached the predetermined number of times, so step 20
0 is determined as "No", and the flow proceeds to step 201. Since the address 2 of the memory 14 is "1" from FIG. 4, step 201 is determined to be rYEsJ, and the flow advances to step 203, where the fifth reading is performed.

In the fifth read, in step 203, ``10'' is written to address 2 of the memory 14, and in step 204, the content ``a'' of address 2 in the memory 13 and the content ``2'' of the counter 22 are output.

Then, since address 2 of the memory 17 is "0" from FIG.
” will be counted up. Therefore, in the fifth reading, the data name "A" and the data value "2" are read out.

In the sixth read, the determination in step 200 is "NO", the determination in step 201 is rYEsJ, the operation of writing "0" to address 3 of the memory 14 in step 203, and the content of the address 3 of the memory 13 in step 204 "H". ” and outputs the value “3” of the counter 22.

In the seventh read, step 205 is determined as YES, step 206 writes 10'' to address 3 of memory 17, and step 207 writes ``10'' to memory 17.
Operation of setting "0", which is the content of address 3 of 5, to the counter 16, memories 19 to 21 in step 208
The contents of address O in r2J, r2J, rl
The operation of reading J, the operation of outputting the content "2" read from the memory 19 in step 209 and the value "3" of the counter 22 are performed.

In the eighth read, step 210 is determined to be rYESJ, step 211 writes "0" to address 0 of memory 21, step 212 sets content 2 of address O of memory 20 to counter 16, The operation of reading out the contents "r)J, r4J, rl" of addresses 2 of memories 19 to 21 in step 213;
Then, the operation of outputting the value "3" of the counter 22 is performed.

In the ninth read, the determination in step 210 is YES, the operation of writing "0" to address 2 of the memory 21 in step 211, and the operation of writing "0" to address 2 of the memory 21 in step 212.
The operation of setting the content "4" of address 2 of address 0 to color 16, the operation of reading the content "suJ, r5J, rl" of address 4 of memories 19 to 21 in step 213, and the operation of reading from memory 19 in step 214 The content is “T”
Then, the operation of outputting the value "3" of the counter 22 is performed.

In the 10th read, step 210 is determined to be rYEsJ, and address 4 of the memory 21 is determined in step 211.
the operation of writing "0" to the counter 16, the operation of setting the content "5" of the address 4 of the memory 20 to the counter 16 in step 212, the action of writing "nu" of the address 5 of the memories 19 to 21 in step 213, [6J, rOJ The operation of reading out
The contents read from the memory 19 in step 214 “
An operation is performed to output the content "3" of the counter 22.

In the 11th read, step 210 is determined to be rYEsJ, and address 5 of the memory 21 is determined in step 211.
The operation of writing "0" into the counter 16, the operation of setting the contents "6" of address 5 of the memory 20 to the counter 16 in step 212, and the operation of writing memories 19 to 21 in step 213
The operation of reading out the contents "RU", rOJ, and rOJ of the address 6 of , and the operation of outputting the contents "RU" read from the memory 19 in step 214 and the contents 3 of the counter 22 are performed.

After that, the flow returns to step 210, but since address 6 of the memory 21 is "0" at this time, step 210
is determined to be rNOJ, and in step 202 the counter 22 is incremented by ``3'' to ``4'' K, and the flow proceeds to step 200.

In the 12th read, step 200 is determined to be rNOJ, step 201 is determined to be rYEs J, the operation of writing "0" to address 4 of memory 14 in step 203, and the content of address 4 of memory 13 "H" in step 204. and outputs the content "4" of the counter 22.

The flow then proceeds to step 205, where the memory 17
Since address 4 of is "0", step 205 is "
If the answer is "NO", the counter 22 is counted up from "4" to "5" in step 202, and then the flow proceeds to step 200. Here, in step 200, it is determined that the predetermined number of times has reached "5", rYEsJ, and the read operation ends.

The readout results explained above are summarized in Table 1.

Table 1 In this way, the data in the table at the top of FIG. 4 is rearranged in descending order of data value as shown in Table 1.

The above embodiment is an example in which the data values are rearranged in descending order, but if the counter 22 is counted down from the maximum value, the data values are rearranged in descending order.

However, in this conventional method, when reading data, for example, as shown in step 201 or 210 in FIG. Since the amount of data has to be searched, the processing time of the central processing unit increases as the amount of data increases, making it impossible to process large amounts of data.

Therefore, an object of the present invention is to provide a data sorting method that can increase the amount of data handled without increasing the data processing capacity of a central processing unit.

In order to achieve such an object, the present invention reads the stored contents of a memory indicating that data is temporarily stored in parallel for each of a plurality of data names, and decodes the read contents to temporarily store the data. It is designed to detect addresses that are Hereinafter, the present invention will be described in detail using drawings showing embodiments.

FIG. 6 shows a method according to the present invention for the memory 14 shown in FIG.
This is a circuit diagram illustrating an embodiment when applied to FIG. 2, and the same symbols are used for the same parts and corresponding parts as in FIG. The memory 14 includes memories 141 to 156 with a capacity of 1x256 bits.
, a priority encoder 157, and a decoder 15B. The memories 141 to 156 are for storing addresses at which data names are temporarily stored in the memory 13, such that address zero is stored at address zero of the memory 141, address 1 is stored at address zero of the memory 142,
The 15th address is stored at address 0 of the memory 156, and the 16th address is returned to the memory 141 and stored at address 1 of the memory 141, and storage is performed in the following manner (for writing). circuit not shown).

Then, when an address signal is supplied to the terminal AO-A7, the memory contents corresponding to this address signal are read out, and when a signal is supplied to the terminal WE, it corresponds to the address signal supplied to the terminal AO-A7. rOJ is written to the address. When a "1" level signal is supplied to the terminals Do to D15, the priority encoder 157 outputs a 4-bit signal representing the number 0 to 15 of the terminal to which the "1" level signal is supplied. It looks like this. At this time, if a "1" level signal is supplied to a plurality of terminals, the lowest number among the terminal numbers to which "1" level signals are supplied is output. When the enable signal is supplied to terminal E, the decoder 158 outputs the contents of the input signal represented by a 4-bit signal as a 16-bit signal.0 Operation of the device configured in this way is as follows. The write operation is the same as the conventional one, and the read operation is also the same as the conventional one except for the operation of the memory 14 portion, so only the operation of the memory 140 portion will be described in detail. The address signal sent from the counter 22 is supplied in parallel to terminals AO to A7 of the memories 141 to 156.

As a result, the memories 141 to 156 supply the stored contents of the portion corresponding to the supplied address signal to the priority encoder 157. At this time, memories 141 to 156
If "1" is read out, a signal at the terminal DO~D15KrlJ level of the priority encoder 157 corresponding to the memory from which "1" is read out is supplied. Input the number of the terminal to which the “1” level signal is supplied to 4.
Since it is expressed as a bit signal and output, this signal is supplied to the memory 13, and the memo January 3 combines this signal with the counter 2.
The stored contents of the address represented by both address signals supplied from 2 are read out.

When the operations up to this point are completed, the central processing unit 23 supplies an enable signal to the enable terminal E of the decoder 158, so that the decoder 15B outputs the data represented by the 4-bit input signal as a 16-bit signal. . As a result, one of the outputs of the decoder 158 becomes "1" level, and this signal is transmitted to the memories 141 to 156.
Therefore, the memory to which this "1" level signal is supplied is 0 memory 141-156 where "0" is written in the part corresponding to the address signal supplied to terminals AO-A7. When multiple "1" level signals are output, the priority encoder 157
Since an output corresponding to the signal of the terminal supplied to the terminal with the lowest number among the terminals 141 to 156 is generated, the memory into which "0" is written is the memory with the lowest number among the memories 141 to 156. After that, perform the same operation and store memory 1.
The contents of the memory 13 corresponding to the address of the memory with the smallest number among 41 to 156 are read out, and "0" is written in the memory from which the data has been read out. This operation is performed by the memories 141 to 156.
It can be read until there is no one that sends out a "1" level signal.

When none of the memories 141 to 156 sends out a "1" level signal, the central processing unit 23
Since an address signal different by one address from the address signal previously supplied to addresses 1 to 156 is supplied, the operation described above is performed again at a new address. This operation is repeated until all the stored contents of the memories 141 to 156 are read out, and the memory 1
Necessary data is read from 3.

Note that the embodiment described above is an example in which the present invention is applied to the memory 14 in FIG. 2, but the present invention is not limited thereto. Any method that reads data to address J@ while searching for a stored address can be applied.

As explained above, the present invention reads multiple types of data in parallel according to instructions from the central processing unit, and decodes the address where the data was stored based on the presence or absence of each type of data. The time required to read data is extremely short compared to reading data by type, and the amount of data to be handled can be increased without increasing the data processing capacity of the central processing unit, so high-speed sorting is required in real time. It has the advantage that it can be used in a graphic generator, etc.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a figure displayed on the screen, FIG. 2 is a block diagram showing an example of a device to which the conventional method is applied,
FIG. 3 is a 70-tayat representing a write operation, FIG. 4 is a diagram showing data stored in each memory in the device, FIG. 5 is a flowchart representing a read operation, and FIG. 6 is a diagram showing the method of the present invention. FIG. 2 is a block diagram showing an example of an applied device. 11~21.141~156e...Memory, 16.2
2・@Φ・Counter, 23...Central processing unit, 15
7...Priority encoder, 158Q...
decoder. Patent applicant Hitachi Electronics Co., Ltd. Agent Masaki Yamakawa (F!7> Tame 1 person)

Claims (1)

[Claims] Data is temporarily stored in the memory according to instructions from the processing device, and the address at which the data was stored is stored in the memory that stores the fact that this temporary storage has been performed, and then the data is stored based on these stored contents. In a data sorting method that rearranges the data in a predetermined order,
Read out in parallel multiple types of storage contents of a memory that stores information that data has been temporarily stored;
A data sorting method characterized by decoding the address where data is temporarily stored based on the presence or absence of stored contents of each type of data.