JPS59108336A - 2-gate field effect transistor - Google Patents

2-gate field effect transistor

Info

Publication number
JPS59108336A
JPS59108336A JP58223051A JP22305183A JPS59108336A JP S59108336 A JPS59108336 A JP S59108336A JP 58223051 A JP58223051 A JP 58223051A JP 22305183 A JP22305183 A JP 22305183A JP S59108336 A JPS59108336 A JP S59108336A
Authority
JP
Japan
Prior art keywords
gate
pad
pellet
terminal
support
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58223051A
Other languages
Japanese (ja)
Inventor
フランコ・ニコラ・セチ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of JPS59108336A publication Critical patent/JPS59108336A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H01L29/8124—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12033—Gunn diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 この発明は２ゲート電界効果トランジスタ（ＦＥＴ　）
に関し、特に大電力を発生する２ゲー）　ＰＥＴに関す
る。DETAILED DESCRIPTION OF THE INVENTION This invention relates to a two-gate field effect transistor (FET).
Regarding PET, especially 2 games that generate large amounts of power.

〔発明の背景〕[Background of the invention]

公知の２ゲー）　ＦＦｔＴはＫｕ帯のような高い周波数
で所望特性の高利得を有する上、その利得を第２ゲート
のバイアス電圧を変えることにより変えることができる
が、出力電力が低くて約１０ｍＷシがない欠点を有する
。FFtT has a high gain with desired characteristics at high frequencies such as the Ku band, and the gain can be changed by changing the bias voltage of the second gate, but the output power is low, about 10 mW. It has the disadvantage that it does not have any flaws.

公知の単ゲートＦＩＴ、特に米国特許第３９９３５１５
号記載の「クリップチップ」構成のＦＥＴは数１００ｍ
Ｗの出力を発生することができるが、高い周波数で制御
された高利得を生ずることができない。Known single-gate FITs, in particular U.S. Pat. No. 3,993,515
The “clip chip” configuration FET described in the issue is several hundred meters long.
Although it can generate an output of W, it cannot produce high controlled gain at high frequencies.

〔発明の概要〕[Summary of the invention]

この発明の推奨実施例では、ＦＥＴペレットが少なくと
も１個のドレンパッドとソースパッドおよびその各パッ
ドに接続された複式電極と少なくとも２個のゲートパッ
ドおよびそれに接続された複式ゲート電極と、多くの他
の電極とを有し、トランジスタ支持体が電気絶縁性で熱
伝導性の基板から成り、その上にソース端子、ドレン端
子、第１ゲート端子、第２ゲート端子および付加端子が
取付けられている。支持体とベレットは、ベレットのド
レンパッドが支持体のドレン端子に、ベレットのソース
パッドが支持体のソース端子に、ベレットの上記ゲート
パッドの１つが支持体の第１ゲート端子に、ベレットの
ゲートパッドの他の１つが支持体の第２ゲート端子に、
ベレットの他の電極が支持体の付加端子にそれぞれ電気
的に接続されるように構成されている。In a preferred embodiment of the invention, the FET pellet has at least one drain pad and a source pad, a dual electrode connected to each pad, at least two gate pads and a dual gate electrode connected thereto, and many other The transistor support comprises an electrically insulating and thermally conductive substrate, on which are mounted a source terminal, a drain terminal, a first gate terminal, a second gate terminal and an additional terminal. The support and the bellet are connected such that the drain pad of the pellet is connected to the drain terminal of the support, the source pad of the pellet is connected to the source terminal of the support, one of the gate pads of the bellet is connected to the first gate terminal of the support, and the gate of the bellet is connected to the first gate terminal of the support. the other one of the pads is connected to the second gate terminal of the support;
Other electrodes of the pellet are configured to be electrically connected to respective additional terminals of the support.

〔詳細な説明］ 第１図および第２図は単ゲート電力ＦＥＴの製造に使用
するＰＥＴベレットの平面図および正面図を示す。ベレ
ット１０はガリウム砒素材料の半導体基板１２を有し、
その上に厚さ約０．３μのガリウム砒素材料のｎ型ドー
プ層１４が被着されている。層１４上には後述の電極お
よびパッドのパターンがある。DETAILED DESCRIPTION FIGS. 1 and 2 show top and front views of a PET pellet used in the fabrication of a single gate power FET. The pellet 10 has a semiconductor substrate 12 of gallium arsenide material;
Deposited thereon is an n-type doped layer 14 of gallium arsenide material approximately 0.3 microns thick. On layer 14 is a pattern of electrodes and pads as described below.

パッドおよび電極の物理的配置は従来法の単ゲート型も
この発明の２ゲート型も同じであるが、電極およびパッ
ドの用途が異なる。Although the physical arrangement of pads and electrodes is the same in both the conventional single-gate type and the two-gate type of the present invention, the uses of the electrodes and pads are different.

第１図および第２図において、括弧で囲まれない文字Ｓ
（ソース）、Ｄ（ドレイン）、Ｇ（ゲート）はこの発明
に使用するパッドおよび電極を示し、括弧で囲まれた同
じ文字は従来法に用いる電極およびパッドを示す。全て
の電極Ｓ、Ｄ％Ｇは第１図の線１６−１６と１８−１８
との間の範囲にある。In Figures 1 and 2, the letter S not enclosed in parentheses
(source), D (drain), and G (gate) indicate pads and electrodes used in the present invention, and the same letters enclosed in parentheses indicate electrodes and pads used in the conventional method. All electrodes S, D%G are connected to lines 16-16 and 18-18 in FIG.
in the range between.

第１図には４つのパッド２０．２２．２４．２６が示さ
れている。全ての電極およびパッドは一般に金を基板１
４に被着して作られる。Four pads 20.22.24.26 are shown in FIG. All electrodes and pads are generally gold on the substrate 1.
It is made by attaching it to 4.

従来法においては例えば２つのドレンパッド２０．２２
があり、ＩＤ）パッド２０が２つの（Ｄ）電極２０ａお
よび２０ｔｌに接続されでいる。同様に、従来法では２
つのゲートパッド２４．２６があり、例えば、（Ｇ）パ
ッド２６が４つのＩＧ）電極２６ａ１ｐ、６ｂ、２６Ｑ
　、　２６４に接続されている。第２図を見ると、全部
で５つの従来法ノ（Ｓ）電ｒｊ１３０．３２．３４．３
６．３８　（７）上面が層１４ノ上で４つの（Ｄ）電極
２０ａ　、　　２０ｂ　％２２ａ　、　２２ｂより高く
なっているどとが判る。８つの（Ｇ）電極（寸法カ小さ
いので第１図では引用数字を付して女い）は製造が容易
なように層１４の凹部に押し込まれている。In the conventional method, for example, two drain pads 20.22
There is an ID) pad 20 connected to two (D) electrodes 20a and 20tl. Similarly, in the conventional method, 2
For example, the (G) pad 26 has four IG) electrodes 26a1p, 6b, 26Q.
, 264. Looking at Figure 2, there are a total of five conventional (S) electric rj130.32.34.3
6.38 (7) It can be seen that the upper surface is higher than the four (D) electrodes 20a, 20b, %22a, 22b on the layer 14, etc. Eight (G) electrodes (designated with reference numerals in FIG. 1 due to their small size) are pressed into recesses in layer 14 for ease of manufacture.

５つの（Ｓ）電極はどのソースパッドにも接続されてい
ないが、従来法によれば後述の支持体によシ互いに電気
的に接続されている。第２図には示されていないが、パ
ッド２０．２２．２４．２６の上面は（Ｓ）電極の上面
と同じ高さにある。The five (S) electrodes are not connected to any source pad, but according to the conventional method, they are electrically connected to each other by a support described later. Although not shown in FIG. 2, the top surface of pad 20.22.24.26 is at the same height as the top surface of the (S) electrode.

代表的な従来法のベレットでは、第１図および第２図の
電極およびパッドのパターンから一端の（Ｓ）電極（例
えば３８）を除いたものが繰り返され、即ち、電極３０
と２６ｄを含めてその間にある１組のパッドおよび電極
が電極３０の左側に配置されている。繰り返される各組
の電極はこの発明に必要ないので図示されていない。In a typical conventional pellet, the electrode and pad pattern of FIGS. 1 and 2 is repeated except for the (S) electrode (e.g., 38) at one end, i.e., electrode 30
A set of pads and electrodes including and 26d are located to the left of electrode 30. Repeating sets of electrodes are not necessary for this invention and are not shown.

この発明による各種のパッドおよび電極の用途は従来法
のものと大分具なる。例えば、第１図に示すように、電
極２２ａ　、　　２２ｂけ従来法のようにドレン電極で
はなくソース電極として扱われ、また同様に、電＠；　
２２ａ　、　　２２ｂに接続されたパッド２２はドレン
パッドではなくソースパッドとして扱われる。電極３０
．３２と３４の一部はソース電極ではなくドレン電極と
して扱われる。The uses of the various pads and electrodes according to the present invention are largely different from those of conventional methods. For example, as shown in FIG. 1, the electrodes 22a and 22b are treated as source electrodes rather than drain electrodes as in the conventional method, and similarly, the electrodes 22a and 22b are treated as source electrodes instead of drain electrodes as in the conventional method.
The pad 22 connected to 22a and 22b is treated as a source pad rather than a drain pad. electrode 30
．． A portion of 32 and 34 is treated as a drain electrode rather than a source electrode.

最後に、ゲートパッド２４に接続されたゲート電極はゲ
ート１の電極として扱われ、ゲートパッド２６に接続さ
れたゲート電極は単に単ゲー）　ＦＥＴのゲート電極と
してではなく、２ゲートＦＥＴのゲート２の電極として
も扱われる。Finally, the gate electrode connected to gate pad 24 is treated as the gate 1 electrode, and the gate electrode connected to gate pad 26 is treated as the gate 2 electrode of a two-gate FET, rather than as the gate electrode of a single-gate FET. Also treated as an electrode.

従来法では、ＰＥＴベレット１０は、第３図の平面図お
よび第４図の断面図について以下説明するように、支持
体５０に取付けられたフリップチップである。即ち、第
３図および第４図は機械的に、第５図は電気的に単ゲー
ト大電力’ＦＥＴを示している。Conventionally, the PET pellet 10 is a flip chip attached to a support 50, as described below with respect to the plan view of FIG. 3 and the cross-sectional view of FIG. That is, FIGS. 3 and 4 show the single-gate high-power 'FET mechanically, and FIG. 5 shows the electrically single-gate high-power 'FET.

第３図では支持体の形状が見え易いようにベレット１０
が仮想線で示されている。壕だ第３図および第４図の尺
度は第１図および第２図のそれよりも小さいのでゲート
およびドレンは電極でなくパッドだけが図示され、ソー
ス電極は個々の電極を示さずに１つの長いブロックとし
て示されている。In Figure 3, the shape of the support body is shown in the form of a bellet 10.
is shown by a phantom line. The scale of Figures 3 and 4 is smaller than that of Figures 1 and 2, so gates and drains are shown only as pads rather than electrodes, and source electrodes are shown as a single pad rather than individual electrodes. Shown as long blocks.

文字Ｇ、Ｄ１　Ｓに使用した括弧は第１図および第２図
と同効である。The parentheses used for the letters G, D1 and S have the same effect as in FIGS. 1 and 2.

支持体５０は全ソース電極（Ｓ）に対する熱伝達と電気
接続のため銅製の逆Ｔ字形部材５２（第４図参照）を含
み、良好な放熱特性を得るために、Ｔの垂直部５２ａは
第４図に示すように断面が台形になっている。支持体５
０はまた平行な２つのセラミック突起部５４．５６およ
び側壁部５２ａを有し、各セラミック起立部の上にはそ
れぞれに銅層５８．６０がある。The support 50 includes an inverted T-shaped member 52 (see FIG. 4) made of copper for heat transfer and electrical connection to all source electrodes (S), and in order to obtain good heat dissipation characteristics, the vertical portion 52a of the T is As shown in Figure 4, the cross section is trapezoidal. Support 5
0 also has two parallel ceramic protrusions 54.56 and sidewalls 52a, with a respective copper layer 58.60 above each ceramic raised portion.

この銅層５８は短かい導線６２．６４によりベレットの
ゲートパッド２４．２．６に接続され、同様に銅層６０
は短かい導線６へ６８によりベレットのドレンノくラド
２０、２２に接続されている。即ち、ゲートパッド２４
．２６は銅層５８により、ドレンパッド２０．２２は銅
層６０によりそれぞれ互いに電気的に接続され、ソース
電極はベレット１０のソース電極および他の部品に発生
する熱を放散させるための丁字形領域５２ａにより電気
的に接続されている。層５８は第３図に小文字ｇで示す
トランジスタのゲート接続部であり、層５６は第３図に
小文字ｄで示すそのトランジスタのドレン接続部であり
、丁字形部材５２は第３図に小文字θで示すトランジス
タのソース接続部である０ 第５図は第３図および第４図に機械的に示されたトラン
ジスタの電気回路図である。括弧内の文字は第１図およ
び第２図のベレットと同様に従来法のＤ％Ｇ、Ｓを示す
が、小文字のｄ＊　　ｇｓＢの端子表示は第３図のそれ
に一致している。This copper layer 58 is connected by a short conductive wire 62.64 to the gate pad 24.2.6 of the bullet, and likewise the copper layer 60.
is connected to the drain holes 20, 22 of the pellet by a short conductor 6 68. That is, the gate pad 24
．． 26 are electrically connected to each other by a copper layer 58, drain pads 20.22 are electrically connected to each other by a copper layer 60, and the source electrode is a T-shaped region 52a for dissipating heat generated in the source electrode of the pellet 10 and other components. electrically connected. Layer 58 is the gate connection of the transistor shown in FIG. 3 with a lower case letter g, layer 56 is the drain connection of that transistor shown with a lower case letter d in FIG. 3, and T-shaped member 52 is shown in FIG. 3 with a lower case letter θ. 5 is an electrical circuit diagram of the transistor shown mechanically in FIGS. 3 and 4. FIG. The letters in parentheses indicate D%G, S of the conventional method as well as the bellets in FIGS. 1 and 2, but the terminal designation of the lower case d*gsB corresponds to that in FIG. 3.

第６図、第７図および第８図は本来単ゲート大電力ＦＦ
１Ｔ用に指定された第１図および第２図のベレットを用
いて通常の２ゲー）　ＦＦ１Ｔより電力処理容量の大き
い２ゲートＦＫＴを作る方法を示す。第６図はこの発明
による２ゲー）　ＰＥＴの平面図である。このＦＥＴは
支持体７０と、第３図と同様に仮想線で図示された第１
図および第２図のＦＥＴペレット１０とを具備する。第
３図と同様に、ゲートパッドと（一方がソースとして使
用される）ドレンパッドだけが、一般のソース（ドレン
）領域に示されている。第７図はＦＥＴベレット１０を
そのままにした第６図の線７−７に沿う断面図である。Figures 6, 7, and 8 are originally single-gate high-power FFs.
We will show how to make a 2-gate FKT with a larger power handling capacity than a normal 2-gate FF1T using the pellets shown in FIGS. 1 and 2 specified for 1T. FIG. 6 is a plan view of a 2-game PET according to the present invention. This FET has a support 70 and a first
and the FET pellet 10 shown in FIG. Similar to FIG. 3, only the gate pad and drain pad (one of which is used as a source) are shown in the general source (drain) region. FIG. 7 is a cross-sectional view taken along line 7--7 of FIG. 6 with the FET pellet 10 as it is.

支持体７０は一般に銅および金の導電性パタンを被着し
た酸化ベリリウムＣＢ８０）裏基板７２を有することが
望ましい。Ｂ８０材料は良好な電気絶縁体および良好な
伝熱体として知られている。導電パタンはベレット１０
のドレンパッド２０に整合してこれと電気的に接続され
たドレンパッド７４と、ソースパッド２２（従来法では
ドレンパッド）に整合してこれと電気的に接続されたソ
ースパッドと、ペレツ）１０の０１ゲートパツド２４に
整合してこれと電気的に接続された第１ゲートパツド７
８と、ベレット１０の０２ゲートパツド２６に整合して
これと電気的に接続された第２ゲートパツド８０とを有
し、さらに全ての電極３０．３２．３４．３６．３８に
整合してこれらと電気的に接続されたパッド８２を有す
る。ベレット１０上の種々のパッドおよび電極は支持体
９０上のその関連パッドにハンダ付けされている。The support 70 preferably has a backing substrate 72, typically beryllium oxide CB80) coated with a conductive pattern of copper and gold. B80 material is known to be a good electrical insulator and a good heat conductor. The conductive pattern is Bellet 10.
a drain pad 74 aligned with and electrically connected to the drain pad 20 of the drain pad 74; a source pad aligned with and electrically connected to the source pad 22 (drain pad in the conventional method); A first gate pad 7 aligned with and electrically connected to the 01 gate pad 24 of
8 and a second gate pad 80 aligned with and electrically connected to the 02 gate pad 26 of the pellet 10, and further aligned with and electrically connected to all the electrodes 30, 32, 34, 36, 38. It has a pad 82 that is connected to the pad 82. The various pads and electrodes on pellet 10 are soldered to their associated pads on support 90.

ベレット１０が電力を通しているときこれに発生する熱
は各パッドを介してＢθ０基板７２．に伝達され、さら
に回路の他の部品（図示せず）に伝達されて最終的に外
気に発散する。When the pellet 10 conducts power, the heat generated in it passes through each pad to the Bθ0 substrate 72. It is further transmitted to other parts of the circuit (not shown) and finally vented to the outside air.

パッド７４．７６．７８．８０は２ゲートトランジスタ
端子で、第８図の２ゲー）　ＩＴ回路図と同一の小文字
で示されている。即ち、パッド７４はトランジスタのド
レンパッドｄであり、パッド７６は第８図に示すように
通常接地されたトランジスタのソースパッド日であり、
パッドク８はトランジスタのゲートｇ端子、パッド８０
けトランジスタのゲートｇ２端子である。Pads 74, 76, 78, 80 are 2-gate transistor terminals and are indicated by the same lowercase letters as in the 2-gate IT circuit diagram in FIG. That is, pad 74 is the drain pad of the transistor, pad 76 is the source pad of the transistor which is normally grounded as shown in FIG.
Pad 8 is the gate g terminal of the transistor, pad 80
This is the gate g2 terminal of the transistor.

第６図、第７図および第８図に示すように、ソースＳ２
／Ｄ１ハツト８２から外界への接続は全くないが、用途
によってはこのパッドから他の回路素子（図示せず）へ
の接続が望まれることもあシ、これはパッド８２にＢｅ
Ｏ基板７２−ヒの所要の回路を適当に接続するだけで容
易に達成される。As shown in FIGS. 6, 7 and 8, the source S2
/D1 There is no connection to the outside world from the pad 82, but depending on the application it may be desired to connect this pad to another circuit element (not shown).
This can be easily accomplished by simply connecting the required circuits of the O substrate 72--H.

第１図および第２図並びに第６図、第７図および第８図
を再検討すれば、この発明により通常ソースとして使用
される電極がドレンとして使用され、その例が電極３０
．３２．３４（第１図）であり、通常ドレンとして使用
される電極がソースとじて使用され、その例が電極２２
ａおよび２２１）であり、通常は互いに電気的に接続さ
れている各ゲート電極（第３図参照）が２つのゲートＧ
ｌおよびＧ２に電気的に分割されていることが理解され
る。Reviewing FIGS. 1 and 2 and FIGS. 6, 7, and 8, it will be seen that according to the present invention, an electrode normally used as a source is used as a drain, an example of which is electrode 30.
．． 32.34 (Figure 1), where an electrode normally used as a drain is used as a source, an example of which is electrode 22.
a and 221), and each gate electrode (see Figure 3), which is normally electrically connected to each other, is connected to two gates G
1 and G2.

通常単ゲート大電力ＦＦ、Ｔの製造に使用するＦ’ＥＴ
ペレット１０（第１図）を、第６図および第７図に示す
ように、従来法と異なる態様で各ペレット電極を相互に
接続して異なる外部接続を与えた新規な支持体と組合せ
ることによって、普通の２ゲー）　ＦＥＴの数倍の電力
を処理することができる２ゲ−トＦＥＴを実現し得るこ
とが判る。さらに、ＢθＯ基板７２上に他の回路および
回路素子（図示せず）を設け、これをパッド７４．７６
．７８１．８０に適当に接続することもできる。F'ET usually used for manufacturing single gate high power FF, T
Pellet 10 (FIG. 1) is combined with a novel support, as shown in FIGS. 6 and 7, in which each pellet electrode is interconnected in a manner different from conventional methods to provide different external connections. It can be seen that it is possible to realize a 2-gate FET that can handle several times the power of a normal 2-gate FET. Further, other circuits and circuit elements (not shown) are provided on the BθO substrate 72 and connected to the pads 74 and 76.
．． 781.80 as appropriate.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は単ゲート大電力ＦＥＴの製造に一般に使用され
るＦＥＴペレットの平面図、第２図は第１図のＦＥＴペ
レットの線２−２に沿う断面図、第３図は第１図のＦＥ
Ｔペレットを仮想線で図示した従来法の単ゲート大電力
ＦＥＴの平面図、第４図は従来法（１１） による第１図のペレットおよび第３図の支持体の線４−
４に沿う断面図、第５図は従来法により第３図および第
４図のように構成された単ゲート大電力ＦＫＴの電気回
路図、第６図は第１図のＦＥＴを仮想線で示したこの発
明の推奨実施例の２ゲート大電力ＦＦ１Ｔの平面図、第
７図はこの発明の推奨実施例による第１図のペレットお
よび第６図の支持体の線７−７に沿う断面図、第８図は
この発明の推奨実施例により第６図および第７図のよう
に構成された２ゲート大電力ＦＥＴの電気回路図である
。 １０・・・ＦＥＴペレット、２０・・・ドレンパッド２
０ａ。 ２０ｂ　１２２ａ　、　　２２ｂ−・−電極、２２−・
−ソースパッド、２４．２６・・−ゲートパッド、２４
ａ−６％２６ａ−ｄ・・・ゲート電極、３０　３２　３
４　３６　３８・・・電極、７０・・・支持体、７２・
・・基板、７４・・・ドレン端子、７６・・・ソース端
子、７８・・・第１ゲート端子、８０・・・第２ゲート
端子、８２・・・追加の端子。 特許用、Ｈ人　　　アールシーニー　コーポレーション
化　理　人　　清　水　　　哲　ほか２名（１２） 肴１０ 世 偉２０ ０ ？８０ −１６１−1 is a top view of a FET pellet commonly used in the manufacture of single gate high power FETs; FIG. 2 is a cross-sectional view of the FET pellet of FIG. 1 taken along line 2--2; and FIG. FE
A plan view of a conventional single-gate high-power FET showing the T-pellet as a virtual line, and FIG. 4 shows a line 4- of the pellet in FIG. 1 and the support in FIG. 3 according to the conventional method (11).
4, FIG. 5 is an electrical circuit diagram of a single-gate high-power FKT configured as shown in FIGS. 3 and 4 using the conventional method, and FIG. 6 shows the FET of FIG. 1 with imaginary lines. 7 is a plan view of a two-gate high power FF1T according to a preferred embodiment of the present invention; FIG. 7 is a cross-sectional view taken along line 7-7 of the pellet of FIG. 1 and the support of FIG. 6 according to a preferred embodiment of the present invention; FIG. 8 is an electrical circuit diagram of a two-gate high power FET constructed as shown in FIGS. 6 and 7 in accordance with a preferred embodiment of the present invention. 10...FET pellet, 20...Drain pad 2
0a. 20b 122a, 22b-・-electrode, 22-・
- Source pad, 24.26... - Gate pad, 24
a-6%26a-d...Gate electrode, 30 32 3
4 36 38...electrode, 70...support, 72.
...Substrate, 74...Drain terminal, 76...Source terminal, 78...First gate terminal, 80...Second gate terminal, 82...Additional terminal. For patent purposes, H person R Cini Corporation, person Tetsu Shimizu and 2 others (12) Appetizers 10 Shiwei 20 0 ? 80 -161-

Claims (1)

【特許請求の範囲】[Claims] （１）少なくとも１つのドレンパッド、ソースパッドお
よび上記各パッドに接続された複式電極と、少なくとも
２つのゲートパッドおよびその各ゲートパッドに接続さ
れた複式ゲート電極と、他の複式電極とを有する電界効
果トランジスタペレットと、電気絶縁性かつ熱伝導性基
板を備え、その上にソース端子、ドレン端子第１ゲート
端子、第２ゲート端子および追加の端子が装着された支
持体とを具備し、上記支持体およびペレットが、そのペ
レットの上記ドレンパラ１がその支持体の上記ドレン端
子に電気的に接続され、そのペレットの上記ソースパッ
ドがその支持体の上記ソース端子に電気的に接続され、
そのペレットの上記ゲートパッドの１つ力でその支持体
の上記第１ゲート端子に電気的に接続され、上記ゲート
パッドの他の１つがその支持体の上記第２ゲート端子に
電気的に接続され、上記ペレットの上記他の電極がその
支持体の上記追加の端子に電気的に接続されるよ゛うに
配置されたことを特徴とする２ゲート電界効果トランジ
スタ。(1) An electric field having at least one drain pad, a source pad, and a dual electrode connected to each of the pads, at least two gate pads, a dual gate electrode connected to each gate pad, and another dual electrode. an effect transistor pellet; and a support body comprising an electrically insulating and thermally conductive substrate, on which a source terminal, a drain terminal, a first gate terminal, a second gate terminal, and an additional terminal are mounted; a body and a pellet, wherein the drain pad 1 of the pellet is electrically connected to the drain terminal of the support, and the source pad of the pellet is electrically connected to the source terminal of the support;
One of the gate pads of the pellet is electrically connected to the first gate terminal of the support, and another one of the gate pads is electrically connected to the second gate terminal of the support. A two-gate field effect transistor, characterized in that said further electrode of said pellet is arranged to be electrically connected to said additional terminal of said support.
JP58223051A 1982-11-26 1983-11-25 2-gate field effect transistor Pending JPS59108336A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US44472582A 1982-11-26 1982-11-26
US444725 1999-11-24

Publications (1)

Publication Number Publication Date
JPS59108336A true JPS59108336A (en) 1984-06-22

Family

ID=23766084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58223051A Pending JPS59108336A (en) 1982-11-26 1983-11-25 2-gate field effect transistor

Country Status (5)

Country Link
JP (1) JPS59108336A (en)
CA (1) CA1200326A (en)
DE (1) DE3343030A1 (en)
FR (1) FR2536910A1 (en)
GB (1) GB2131228B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0425031A (en) * 1990-05-16 1992-01-28 Nec Corp High-output monolithic microwave integrated circuit

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2137807B (en) * 1983-04-05 1987-08-12 Plessey Co Plc A semiconductor component and method of manufacture
AU668463B2 (en) * 1992-12-22 1996-05-02 Hughes Aircraft Company Fet chip with heat-extracting bridge
DE4444808B4 (en) * 1993-12-17 2005-12-15 Denso Corp., Kariya Semiconductor device
US7299459B1 (en) 2000-01-19 2007-11-20 Sabio Labs, Inc. Parser for signomial and geometric programs
US6802050B2 (en) * 2002-04-07 2004-10-05 Barcelona Design, Inc. Efficient layout strategy for automated design layout tools
WO2003088102A2 (en) 2002-04-10 2003-10-23 Barcelona Design, Inc. Method and apparatus for efficient semiconductor process evaluation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2302592A1 (en) * 1975-02-26 1976-09-24 Nippon Electric Co DOUBLE DOOR SCHOTTKY BARRIER FIELD EFFECT TRANSISTOR
US3993515A (en) * 1975-03-31 1976-11-23 Rca Corporation Method of forming raised electrical contacts on a semiconductor device
US4104673A (en) * 1977-02-07 1978-08-01 Westinghouse Electric Corp. Field effect pentode transistor
US4161740A (en) * 1977-11-07 1979-07-17 Microwave Semiconductor Corp. High frequency power transistor having reduced interconnection inductance and thermal resistance
FR2455785A1 (en) * 1979-05-02 1980-11-28 Thomson Csf ELECTRICAL INSULATOR SUPPORT, WITH LOW THERMAL RESISTANCE, AND BASE OR HOUSING FOR POWER COMPONENT, INCLUDING SUCH SUPPORT

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0425031A (en) * 1990-05-16 1992-01-28 Nec Corp High-output monolithic microwave integrated circuit

Also Published As

Publication number Publication date
GB8331225D0 (en) 1983-12-29
FR2536910A1 (en) 1984-06-01
DE3343030A1 (en) 1984-05-30
GB2131228A (en) 1984-06-13
CA1200326A (en) 1986-02-04
GB2131228B (en) 1986-06-04

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