JPS59105683A - Display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a display control device, and more specifically, in a raster scan type character display device, the display screen is divided into a plurality of areas and symbols are converted into characters. etc.,
Furthermore, the present invention relates to a display/display control device suitable for controlling scrolling of a screen for each divided area.

[Prior art]

As a raster scan type character display device, Catho
2. Description of the Related Art A CRT (hereinafter simply referred to as a CRT) is well known and widely used as a terminal device in the field of information processing.

When displaying digitized characters, symbols, etc. on this CRT, a refresh memory is usually provided corresponding to the display screen of the CRT. This refresh memory stores display data such as characters as character codes, and this display data is sequentially read out from the refresh memory in synchronization with raster scanning on the display screen. Based on this display data, a character pattern is output from a character generator, and this character pattern is displayed on a display screen along a scanning line.

By the way, recently, such character display devices have been used to create or process sentences, and C
There is a strong need to divide the RT display screen into several parts. To meet such needs, it is necessary to continuously display data divided into a plurality of blocks whose addresses on the memory are not consecutive in the divided areas on one display screen. For this purpose, conventionally, each block in memory with non-consecutive addresses is re-edited into continuous addresses and written to a fresh memory. Therefore, data in each block must be processed in a complicated manner for editing, and moreover, it takes a great deal of time to write one screen's worth of data to the refresh memory after editing. Furthermore, even when scrolling a character pattern or the like displayed over a plurality of lines on a display screen line by line, there is the inconvenience of having to re-edit the display data and write it into the refresh memory each time.

[Purpose of the invention]

Therefore, it is an object of the present invention to provide a display control device in which a display screen is divided into a plurality of areas and characters, symbols, etc. The object of the present invention is to provide a display control device that can continuously display images on divided areas of a display screen.

Another object of the present invention is to provide a display control device that can perform a scrolling operation for each area divided into a plurality of areas without re-editing data in a memory that stores display data each time. be.

[Summary of the invention]

The present invention is realized in a display device that selectively reads character codes from a memory that stores character codes, converts them into character patterns, and displays the character patterns on a display screen of a display device. That is, in order to sequentially read character codes from this memory, a first addressing means is provided. In addition, control information is provided to divide the display screen into a plurality of parts, to divide the memory into a plurality of blocks corresponding to the divided screens, and to set a range for outputting character codes in this block, that is, a display area. The control information is set, and an area is reserved in the memory or another memory to store this control information. A second addressing means is provided for specifying control information within this area.

In a raster scan type display device, control information specified by the second addressing means is output from the memory during a predetermined time period of the raster scan. Further, a comparator is provided for comparing this control information with an address directly or indirectly related to the address indicated by the first addressing means. Based on the comparison result of this comparator, the address given to the memory from the first addressing means is set, and as a result, the character code group to be displayed on a certain split screen, that is, the display area is set. be done. Therefore, if the above operations are performed continuously to support split screens, even if display areas are set at non-consecutive addresses in memory according to respective control information, each split screen can be combined. Furthermore, patterns of characters, symbols, etc. can be displayed in a connected manner on the display screen.

In the configuration of the present invention, a processing device such as a microflow sensor is further connected to the memory via an address bus and a data bus. Thus, the character code and control information can be rewritten by accessing this memory from the processing device.

In a raster scan type display device, this rewriting operation is performed, for example, between vertical blanking lines of the raster.

In particular, control information for setting the display area can be arbitrarily set and rewritten within each block.

When a display screen is composed of a plurality of lines and character patterns are displayed in correspondence with the lines, each split screen is set as a set of several display lines. Therefore, within each block, the display area is set in units of display rows.

The scrolling operation is arbitrarily performed within the divided screen line by line in the display area set by the control information.

This can be easily done by having the processing device rewrite the control information for setting the display area at regular intervals.

[Embodiments of the invention]

FIG. 1 shows a block diagram of a display control device according to an embodiment of the present invention. Note that this embodiment describes an example applied to a CRT, and in order to make the following explanation easier to understand, the display screen of the CRT display 10 has 80 characters per line and 4 characters per 12 lines. It refers to something that displays a character pattern.

Now, in this figure, memory 1 is rewritable and stores characters, symbols, etc. displayed on the display screen of display device 1o as character codes. Parameters characteristic of this embodiment are also stored in this memory 1 in order to control the division into multiple parts. Below memory 1
The memory format will be explained in more detail with reference to Figure 2.

As shown in the memory map of the memory 1 in FIG. 2(a), the address of the memory 1 consists of 16 bits and the data field consists of 8 bits. This memory 1 has an area for storing a large number of character codes and an area B for storing parameters.

Here, the parameters are control information for dividing and controlling the display screen into a plurality of parts. In this example, it is assumed that the display screen is divided into four at most. Therefore, a parameter storage area consisting of 32 words is secured in the memory 1 in order to control each of the four divided screens 0-3. As parameters for controlling the divided screen, RA,
Four types are defined: FA, DA, and SA. Note that each parameter is defined by 16 bits, and the parameter indicated by (L) indicates the lower 8 bits, and the parameter indicated by (H) indicates the upper 8 bits.

In this embodiment, in order to set the logical area of each split screen, a certain area (hereinafter referred to as a block) in the character code storage area A in the memory 1 is defined, and within this block, the A display area is defined to set a storage area for character codes to be displayed on the display screen. Under these assumptions, the parameter FA is the first address of the block, R and A are the addresses next to the last address of the block, and S
A indicates the display start address within the block, and DA indicates the address next to the display final address within the block.

For example, an example will be described in which the display screen is divided into six parts using such parameters.

Regarding this, reference is made to the diagram of the character code storage area shown in FIG. 2(b). It is assumed that parameters for divided screens 0 to 2 set blocks and display areas, respectively, as shown in the figure. For split screen 0, character codes are sequentially output from display start address SAo. 80 per line
The character patterns of are output in sequence, and when the character code for 6 lines is output before the address RAo next to the last address of block O, the next step is to return to the first address FAo of block O and display from this FA, O. At the final address (that is, the address before DAO), character codes are sequentially output.

As a result, 8 lines of character codes with 80 characters per line are output on split screen 0.

Similarly, parameters SA1 to RA for split screen 1
Character codes of 80 per line are output for 6 lines up to the address before l. Then, it is returned to FAI, but since DAl is set here, three lines of character codes are output for split screen 1 in the end.

Similarly, the parameter SA2 for split screen 2. ,darkness,
2. One line of character code is output by 1'A2 and DA2.

In this way, the character codes outputted under the control of the parameters of split screens 0 to 2 correspond as shown in FIG. That is, character codes controlled by the parameters for split screen 0 are output corresponding to the 8 lines with line numbers O to 7, and character codes controlled by the parameters for split screen 1 are output corresponding to the 6 lines with line numbers 8 to 10. The controlled character code is output, and the character code controlled by the parameter for split screen 2 is output corresponding to one line with line number 11.

Now, let's return to Figure 1. As described above, the memory 1 stores character codes and parameters for screen division. An AT1/S register 4 is provided for specifying a character code in the memory 1, and an address line 27 is provided for specifying parameters. The output of address register 4 and address line 27 are connected to multiplexer 8. Further, an address bus 25 is connected to this multiplexer 8 for writing parameters and character codes processed by a processing device 11 such as a microprocessor into the memory 1, and for writing parameters and character codes in the memory 1 to the processing device 11. An address is provided to multiplexer 8 via address bus 25 for transfer to. The multiplexer 8 is supplied with a control signal 29 for selecting an address from the control section 6, and depending on this control signal 29, the output of the address register 4, the address of the address line 277511A, or the address of the address bus 25 is selected. One of the addresses from is selected. That is, as will be described in detail later, the multiplexer 8 selects an address from the address register 4 in order to sequentially read character codes from the memory 1 during the raster scan display period, and selects the address from the address register 4 during the horizontal retrace period according to the control signal 29. An address from the address line 27 is selected to read parameters for a certain split screen, and an address from the address bus 25 is selected during the vertical retrace interval to transfer a take between the memory 1 and the processing unit 11. Select゛.

The format and generation of an address for reading parameters will be explained. As shown in FIG. 3, the parameter address line 27 consists of 16 bits, and the upper 11 pits from 2" to 21" are from the parameter address register 7,
The 2 bits from 3 to 24 are from the divide counter 12.
The lower three bits from 2° to 2' are given from the 22.2j and 125th bits of the character counter 20. This one
Of the 6-bit parameter address, character counter 2 is the actual part for reading the parameter.
The 6 pinpoints from 0 are the type of parameter, i.e. RA, FA.
, D.A.

The two bits from the divide counter 12 specify one of the four divided screens 0-6. In this way, the actual address part of the parameter is the lower 5 bits, and occupies an area of 32 words on the memory 1, as shown in FIG. This 32-word area may be located at any location on the memory 1, and the upper 11 bits of the parameter address, ie, the output of the parameter address register 7, are used to specify this area on the memory 1.

The parameter address set in this parameter address register 27 is transmitted from the data bus 26 to the path receiver 2.
4.

If you want to scroll the display screen, you need to rewrite the parameters in memory 1, and if you want to change the character pattern displayed on the display screen, you need to rewrite the character code in memory 1. There is. In this case, the processing device 11 refers to the parameters and character codes in the memory 1. Take register 2
For this purpose, parameters and character codes read from memory 1 are temporarily stored. This take register 2
The take within is transferred to the processing device 11 via the bus driver 23 and take bus 26.

The data register 3 temporarily senode the character code and parameters read from the menu 1. Among these, is the sentence + code sequential character ratio? sent to. On the other hand, the parameter is sent to the comparator 5 and to the row address register 13 under certain conditions, where it is subjected to characteristic processing.

Character Generator 9, as is well known,
It has a memory structure that stores many character patterns.

When a character code is sent from the data register 3, the corresponding character pattern is output using this as an address. The display 10 is, for example, a CRT display, and sequentially displays character patterns output from the character generator 9 in synchronization with raster scanning.

In this embodiment, in order to control the display screen by dividing it,
Variations are set for each split screen, and these parameters are processed characteristically. At the same time, the address given to the address register 4 for reading the character code from the memory 1 is also characteristically controlled by these parameters. This will be explained below.

The 8-bit character code and parameters output from the take register 3 are sent to the comparator 5. Comparator 5 receives data from data register 3.

The data and the data from multiplexer 14 are compared 8 bits at a time. As will be understood later in the explanation, when the parameter is set in data register B, in other words, the comparison operation of comparator 5 is controlled to be valid only during such a period, so the character code This comparison operation is invalid during a period in which there is a possibility that the data is sent from the data register 3 to the comparator 5. Therefore, it may be considered that the following description deals with the parameters, ie, RAlFA, DA, and SA.

16-bit data is sent from the row address register 13 to the multiplexer 14, and the lower 8 bits and upper 8 bits are selected by the control signal 32 from the control section 6 and sent to the comparator 5.

That is, in the comparator 5, the lower 8 bits of each parameter) (
(indicated by (L)) are compared first, and then the top eight (indicated by (H)) of each parameter are compared. The results of this comparison are temporarily held in flip-flops 15 and 16.

It becomes. That is, as a result of the comparison, the row address register 16
If the lower 8 bits of the parameter match the lower 8 bits of the parameter, the flip-flop 15 is set; then, if the upper 8 bits of the parameter match, the clip-flop 16 is set and , flip-flop 1
5 is also set.

AND gate 17 connects flip-flops 15 and 16 with “
1” side pressure match or not, that is, data register 3
It is checked whether or not the contents of a pair of 8-bit bits sent from the column address register 13 match each other, and if they match, a match signal 36 is output to the control section 6.

When the control section 6 detects this coincidence signal 36, it sets each of the 8 bits from the data register 6 into a pair of non-parallel row address registers 13.

The frame number set in the row address register 16 is provided for reading character codes from the memory 1.
The contents of the row address register 16 are set in the address register 4 by the control signal 60.

Now, various control signals for performing parameter processing as described above will be explained in more detail.

As is well known, a character display device using a CRT has a clock counter 19, a character counter 20, a raster address counter 21, and a line counter 22.

The clock counter 19 is a counter that counts i times based on the basic clock, and defines the timing of each dot of the character pattern displayed on the display screen. For example, if an alphanumeric pattern is displayed with a configuration of 7 dots horizontally and 9 dots vertically, the clock counter 19 will be 7"
Each time a signal is output to the character counter 20, the character counter 20 is initialized. character counter 2
0 is displayed in one line of the display screen based on the output of the clock counter 19. Count the number of characters. This counter 20 has, for example, 7 bits of 2 degrees to 26 degrees.

The three bits 22, 2j and 2M are sent to the timing generator 18, and are also connected to the parameter address line 27 as described above. In the case of this embodiment, 80 characters are displayed per line as shown in FIG.
Even if it exceeds the range of "111", it continues counting and is initialized after counting "111".

That is, the count value between "80" and "111" is the raster horizontal retrace period, and the three bits 2F, 2j, and 2" during this period are valid for reading parameters from memory 1. The reason why we focused on bits G, 28, and G of the character counter 20 can be understood from FIG.
The 6 bits of 22.28.2″ are 0.0.0″,
This value becomes the lower 3 bits of parameter address 2747). As a result, R in parameter area B of memory 1
A-(L) is designated. Next, character counter 20
is updated, and between column numbers 84 to 87, these 6 bits are 0.0.1'', and this value becomes the lower 6 bits of the parameter address, and the parameter RA in memory 1 is
(H) is specified. In this way, while the character counter 20 changes from column number 80 to 111, these three bits change from "000" to "111", and as a result, eight parameters, namely , essentially four 16-bit parameters for controlling one split screen are output.

The output of character counter 20 is also sent to raster counter 21. That is, when the character counter 20 counts 111" in the column number, it is initialized, and each time a signal is output to the raster counter 21. Each time a signal from the character counter 20 is input, the raster counter 21 The count value is updated. The counter value essentially counts the number of rasters and indicates the raster address. Assuming that the number of rasters per line on the display screen is 16, the raster counter 21 is " 0″ to 1
The output of the raster counter 21 is sent to the timing generator 18, the character generator 9, and the row counter 22. The signal 37 sent from the raster counter 2i to the character generator 91 is a known signal. This raster address is used for synchronization when reading character patterns from the character generator 9.

Each time the raster counter 21 counts the 16th raster, the row counter 22 receives the signal and updates its count value, essentially counts the display rows on the display screen, and sends the output to the timing generator 18. send to In the case of this example, the character pattern is displayed over 12 lines on the display screen as shown in FIG. First, the counting operation continues, and when the count reaches "44", the counter is initialized. Therefore - C1 this row counter 22 is 12
The period from ``14'' to ``14'' is a vertical retrace period, and as mentioned above, the address bus 25 can access the memory 1 during this period, and parameters, character codes, etc. are rewritten. .

The timing generator 18 indicates the display period to the character generator 9 and a signal 64 for controlling various timings used by the controller 6 based on the count signals of the character counter 20, raster counter 21, and line counter 22. A control signal 65 is generated. Therefore, this timing generating section 18 specifically uses the counters 20 and 21.
．． A known decoder that decodes the output of 22 is sufficient.

Next, various control signals output from the control section 6 will be explained. In short, wholesale 1. The control signal output from the controller 6 is based on the coincidence signal 36 from the AND gate 17 and the output signal 34 from the timing generator 18.

The control signal 28 is a signal for updating the value of the divide counter 12 every month when the split screen ends. If they match, this control signal 28 is outputted by the match signal 36. For example, when the divide counter 12 indicates an 8-word area in which parameters for the first divided screen O are stored, and the contents of DAo and the row address register 16 match as a result of the comparison, The value of the divide counter 12 is updated by the control signal 28, and then the value of the divide counter 12 is updated.
An 8-word area in which parameters for the th split screen 1 are stored is specified. Divide counter 1 like this
The contents of 2 are updated sequentially by the control signal 28, and up to 4
Parameter storage areas for two split screens are specified.

If the parameters DA5 for the fourth divided screen 6 match as a result of the above comparison, the value of the divide counter 12 is initialized by the control signal 28.

Control signal 29 is used to select the address to be given to memory 1. given to 8. This signal 29 indicates that during the middle of the display period, the character counter 20 is 0.
Saki counting "~"79", address register 4
Select the address within.

Further, as shown in FIG. 5, when the character counter 20 is counting 8D" to "111", that is, during the horizontal retrace period, the raster counter 21 is counting the 16th rask, that is, in each row. When counting the final raster,
A parameter read period is set, and a parameter address from the parameter address line 27 is selected during this period. Furthermore, during the period when the line counter is counting "12" to "14", that is, the vertical retrace period, the address bus is used to write parameters and character codes to the memory 1 or to transfer them to the processing device 1. Addresses from 25 are selected.

The control signal 62 is a signal for selecting the lower 8 bits and upper 8 bits of the 16-bit row address transferred to the row address register 13, and is used to select the lower 8 bits and upper 8 pits of the 16-bit row address transferred to the row address register 13.
0 is the column number and is emitted every time the column number is incremented by 4 while counting from "80" to "111".

The control signal 66 is a signal that substantially enables the comparison operation in the comparator 5, and at the same timing when the control signal 62 is output, the raster counters 21 each output the final raster, for example, the 16th raster. Every time the th raster is counted, a signal is output to the tri-input terminals of the flip-flops 15 and 16.

The control signal LO 1 is when the coincidence signal 66 is input to the control unit 6, and in particular, the character counter 20 is 1 in the column number.
04 to 107" and "108 to 111" are issued to the row address register 13, and enable the loading of parameters from the data l/dystaro to the row address register 13. That is, this causes each split screen to A 16-bit parameter indicating the display start address SA is set in the row address register 16.

The control signal 39 is a signal for updating the contents of the row address register 16, and each time the value of the raster counter 21 counts the last raster of each display row, the value of the register 13 is updated by this signal 39. It is updated by plus "80". That is, the value of this row address register 13 is
This indicates the address in memory 1 of the character code to be displayed at the beginning of the next display line.

The control signal 50 is a signal for transferring the contents of the row address register 16 to the address register 4, and as shown in FIG. is emitted. The control signal 38 is a signal for updating the contents of the address register 4, and when the character counter 20 is '0''
Every time a counting operation is performed up to 79'', the address value is updated.

Therefore, each time the raster reaches the final character position in each display line, the contents of the line address register 13 are transferred to the address register 4. While the character counter 20 is counting characters during the display period, the contents of the address register 4 are sequentially counted up. Moreover, during this period, it is valid that the contents of the address register 4 are given to the memory 1 by the control signal 29. Therefore, while being specified as the address of the address register 4, which is updated sequentially, the contents of the address register 4 are applied to the memory 1 during this display period. Character codes of 80 characters per line are sequentially output to data register B. Furthermore, as the raster scan progresses and moves to the final raster of the display row, the value of the row address register 16 is updated to the display start address SA0 "80" in a certain split screen, and the control signal 60 updates the value of the row address register 16 to "80". The subsequent address is transferred to address register 4. Then, when the raster scan moves to the scan of the first notification of the next display line,
The contents of the address register 4 are changed to the fifth by the control signal 6B.
As shown in the figure, from address (SA+"80") to (SA0"
The character code is sequentially updated from 80")-1 to 80", and each time the character code is outputted from the memory 1 to the data register B according to the address indicated by the address register 4.

Thereafter, in the same manner, during the display period, the address register 4
is specified, and the character codes in memory 1 are sequentially output. Note that the character code output from the memory 1 is sent to the character generator 9, as is well known from now on, from which a character pattern corresponding to this character code is output and sent to the display 10. Next, the overall operation of the character display control device shown in FIG. 1 will be explained with reference to the signal diagram shown in FIG. 6.

First, as an initial setting, the processing device 11 sets how many parts the display screen should be divided into and the configuration for controlling each divided screen.

In this example, a maximum of four screen divisions are set in units of display lines on the display screen. The control signal 29 controls the multiplexer 8 to select an address from the address bus 25 during the vertical retrace period. address bus 2
5 to memory 1, an address for writing the harameter is applied. The parameters are transferred via the data bus 26 and the path receiver 24, and are stored in the parameter storage area B.
is stored at the specified address. Further, in the parameter address register 7, an address for specifying a 32-word area B in which parameters for controlling the four divided screens are stored is set.

Similarly, using this vertical retrace period, many character codes to be displayed are sequentially stored in the character code storage area A of the memory 1 in accordance with the parameters for each split screen. Although not particularly shown, the character code is transferred from the host device via the bus 26.

Next, as pre-processing for displaying a character pattern on the display 10, the divide counter 12 is initialized. This is cleared by the vertical retrace signal issued during the vertical retrace interval.

As a result, the byte counter points to the parameter storage area for the first split screen.

Even during such a case, raster scanning is performed on the display screen of the display device 10. On the other hand, a clock counter 19, a character counter 20, a raster counter 21,
The row counter 22 also repeats counting operations. and,
The row counter 22 counts the last row, that is, the row number "14", and the character counter 20 counts the column numbers "80" to "111".
”, and when the raster counter 21 counts the final raster, readout control of parameters for controlling the first divided screen 0 is performed in the shaded area in the middle cylinder 5. That is, during this period, the control signal 29, the multiplexer 8 selects the address from the parameter address line 27. That is, the lower 6 bits of the parameter address are sequentially updated by the three pits of the character counter 20, 23 and 23, so that the parameters in the memory 1 are Storage area B
Therefore, the parameters RAo(L) and RAO for split screen 0
(H), FAo (L), FAo (H), DAo (L),
DAo(H), 5Ao(,T,), and 5Ao(H) are sequentially output to the data register 3 and sent to the comparator 5 in order. At this point, the contents of the row address register 16 to be compared by the comparator 5 are uncertain. Therefore,
In the control unit 6, the row counter 22 counts the last row, and the character counter 20 counts the column numbers "104" to "107".
and 108" to "111", and the control signal 61 is made valid regardless of whether the comparator 5 matches or does not match. In other words, even if the match signal 36 is not detected, the control signal 61 is made valid. Therefore, display start address 5Ao(L), 5A
o(H) is unconditionally stored in the row address register 13.

This operation of setting the starting address SAo for divided screen 0 in the row address register 13 is performed every frame of the display screen.

Then, the character counter 20 is the column number, "iii
At the same time as counting ", the contents of row address register 1 are set in address register 4 by control signal 30. This means that the display start address for split screen 0 has been set in address register 4. Become.

Now, the character counter 20, the raster counter 21,
The row counter 22 is initialized, and the first row is
When counting starts from the first character position of the first rask, the control signal 29 controls the multiplexer 8 to select an address from the address register 4.

On the other hand, the contents of the address register 4 are sequentially updated from the first address SAo by the control signal 38.

By applying this address to the memory 1 via the multiplexer 8, the 80 character codes displayed on the first line are sequentially output from the memory 1 to the data register. Then, as is well known, the character generator 9 outputs a character pattern corresponding to the character code, and the display 1o is synchronized with the signal 35 indicating the display period.
displayed on the display screen.

From then on, regarding the display of the first line, the raster counter 21
The count value of is only updated sequentially, and the character code reading operation is repeated in the same manner as described above during each raster scan.

Now, in the first line, the raster counter 21 counts the final raster, that is, the 16th raster, and the count value of the character counter 2o moves to column number "79" and onwards. Parameters for split screen 1 to 0) - RAo (L), RA.

(H), =---SAo (L), 5Ao (H) read operation is performed. Then, these parameters are sent to the comparator 5 as described above, and compared with the contents of the row attrition/slash raster 16. At this time, the contents of the row address register 16 are changed to S by the control signal 69.
It has been updated to address AO+"80".

Therefore, as a result of the comparison operation in the comparator 5, a match is found.
The contents of are set in address register 4. Thereafter, the value of the line counter 22 is updated, the raster counter 21 and the character counter 20 are initialized, and a character code for display on the second line is read out. In this case, the same operation as described above is performed except that the character code is read from the memory 1 while the address value of the address register 4 is updated sequentially from SAo+"80".

From then on, as shown in FIG. 5, each time the line number is updated to 2, 3, etc., the value of the address register 4 for reading the character code to be output at the beginning of each line changes to: SAo
+160, SAD+240, etc., and the same operation as above is repeated.

Thereafter, when the line counter 22 indicates line number "5", the comparator 5 compares the parameters for split screen 0 differently. In other words, the contents of the row address register 13 are SAO 0''400'', this contents are compared with each parameter, and as a result, the starting address of the block FAo (
L), comparison with FAo (H).

They match, and a match signal 36 is input to the control unit B.

Therefore, a control signal 61 is outputted from the control section 6 to the row address register 16, and the parameter FAo of 16 pinots is set in the row address register 13 by this signal 31. The contents of the row address register 16 are then transferred to the address register 4 by the control signal 6o.

Thereafter, character codes for lines after line number "6" are read out in the same manner as described above starting from address FAo.

In this way, on the memory 1, as shown in FIG. 2(b), the address before the address DAo next to the last displayed address is accessed, and as a result, the address numbered "7" in FIG. The character code controlled by the paran-p for split screen 0 is output from the memory 1 to a total of 8 lines of display area.

Furthermore, during the horizontal retrace period of row number "7", the row address register 16 in the comparator 5, that is, the multiplexer 14
When comparing the line address from and the parameter for split screen printing, especially if the address DAo next to the final address of the display area matches, reading out the character code for split screen 0 from memory 1 is completed. In addition, a control signal 28 is issued from the control section 6 to the divide counter 12, whereby the contents of the divide counter 12 specify an 8-word area in the parameter area B in which parameters for split screen 1 are stored. However, since the lower 6 bits of the parameter address, that is, the character counter 20 is beginning to indicate column numbers after "104", the parameter address is
Parameters 5A1 (L) and 5A1 (H) for this will be specified.

As a result, the address S indicating the start of display is stored from memory 1.
A1 (L) and 5A1 (H) are sequentially read out to data register B. This display start address 5A1 (L), 5A1
(H) is unconditionally set in the row address register 13 and transferred to the address register 4. Therefore, line number "8"
'', character codes are sequentially output from address SA1 on memory 1 indicated by address register 4.

Then, by repeating the same operation as described above, the character codes corresponding to three lines from the parameter storage area for setting the surface water area to the previous address of DAl are sequentially read out from the memory 1 to the data register 3, and the character codes are sequentially read out from the memory 1 to the data register 3. It is sent to generator 9. In addition, during the parameter reading period for line number "10", the operation of setting the display start address SA2 of the third split screen 2 in the line address register 16 and address register 4 is performed as described above (!: Same? It will be done.

In this way, as shown in Figure 5, the line numbers "0" to "
6 consisting of 8 lines, 3 lines, and 1 line among the 12 lines up to 11"
Character patterns are displayed on each of the two split screens.

Note that during such an operation, the data bus 26 and the bus receiver 2 are
Via 4, note l? Any character code can be written here. Therefore, a character pattern corresponding to any character code ζ can be displayed on the display screen within the range of the split screen format described above.

According to this embodiment, in a split screen, a certain display line unit? This scrolling action can also be performed.

Referring to FIG. 7, the range of blocks is set by a certain split screen control parameter FA1RA1. Within the range of this block, character codes that can be displayed within the split screen are stored. Initially, the parameter S
A,, DA,? Assume that a display range (shaded area) is thus set, character codes in this range are output from the memory 1 through the above-described operation ζ, and a character pattern is displayed on the display screen. When a scroll operation is to be performed, the processing unit 11 specifies the storage address of the parameter 5A1DA in the memory 1 via the address bus 25 and the multiplexer 8 using the vertical retrace period (Fig. 5). address will be given. At the same time, processing device 1
1, the parameters S' and D' are given to the memory 1 via the redata bus 26 and the path receiver 24, and as a result, the old parameters SA and DA are written to the new parameters SA' and DA'. Can be replaced. Therefore, from then on, the display area is set by the parameters SA' and DA', and character codes are sequentially output from the area in the same manner as in the operation described above. In addition, in the case of this scrolling operation, it goes without saying that Go to S' and Go to D' are set so that the same number of lines as specified by 5A1DA can be selected within the range of the corresponding block. . Under this condition.

SA' and DA' can be set arbitrarily, but for example, when scrolling one line at a time, SA', ..., SA+80, DA': DA-1-
It is understood that it is sufficient to set it to 80 (representing 80 characters displayed in one line).

Now, according to another application example of the present invention, scrolling operation in the horizontal direction is also possible. As shown in FIG.
As, character codes of 1 and 2 can be stored per line,
It is assumed that 80 character codes are output in two lines on the display screen.

Therefore, initially, 5AO1DAo (= SA
o 10゛80"), 8A1 (= SAo + "1
52"), DAl(=S A1+"so) and two display areas (shaded areas) are set.

When scrolling in the horizontal X direction, change SAO' to, for example,
If you reset SAO'=SAO+"1", DAo', SA1', and DAl' will also each be plus "1" accordingly.
As a result, the display area is newly set at a position shifted by one character to the right, and character codes are sequentially read from this area. In addition, in this example, SAO'
, DAo', SAI', DAl' are set arbitrarily,
It is understood that the operating range is that scrolling is performed line by line over a maximum of ``52'' characters in the horizontal direction.

FIG. 9 is a partial block diagram for explaining another embodiment of the present invention, specifically, an example in which the parameter storage area B is provided separately from the memory 1 shown in FIG. This is to explain. Note that the same parts as those shown in FIG. 1 are given the same reference numerals. In this example, a group of parameters for controlling the split screen shown in FIG. 2(a), for example, is stored in the memory 100, and
, and parameter addresses 270 consisting of the aforementioned five pits from the divide counter 12 and character counter 20 are applied to this memory 100. Further, a data bus 26 is connected to a data input terminal of this memory 100 via a path receiver 24 in order to write parameters. In this example, memory 100
is inevitably accessed, so the parameter address register 7 is not required to specify the 62-word area of the parameter storage area B, as shown in FIG. memory 10
Parameter reading control from 0 is performed in the same manner as described above. However, in other time periods, that is, during the display period and vertical retrace period in FIG. 5, the processing device 11 can arbitrarily access the memory 1.

Although one embodiment and some application examples of the present invention have been described above, the present invention is not limited to these.
For example, in the embodiments described above, the various numerical conditions are merely examples, and the present invention is not limited thereto. For example, if you want to divide the display screen into more than four, you can increase the number of bits in the divide count 12. In this case, as a matter of course, the parameter storage area increases from 62 words, so it is necessary to increase the number of words in the parameter address register.

Furthermore, in the above embodiment, the data width of the memory 1 was set to 8 bits, but if this were set to 16 bits, 16 bits of data width would be read out from the memory 1 at the same time.
The comparator 5 compares the contents of the row address register 16 with 16 bits at the same time. In this case, the control signal 32 is not needed and the fritsuno flop 15.16
It is understood that AND gate 17 is also unnecessary0

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a display control device according to an embodiment of the present invention, and FIG. 2 is a diagram showing how parameters are set in the memory map and character code storage area of the memory 1 in FIG. 1. 3 is a diagram showing the parameter address format, FIG. 4 is a diagram showing how parameters are addressed to the memory 1, FIG. 5 is a diagram for explaining the operation of the display screen by raster scanning, and FIG. 6 is a signal diagram of each part shown in FIG. 1, FIG. 7 is a diagram for explaining the scrolling operation of the display screen, and FIG. 8 is a diagram for explaining the horizontal scrolling operation of the display screen. , No. 9
This figure is a block diagram of main parts when the display control device shown in FIG. 1 is modified to provide another embodiment. 1...Memory, 4...Address register, 5...Comparator, 6...Control unit,
7...Parameter address register, 8...Multiplexer, 9...Character generator.

Claims (1)

[Scope of Claims] (1) In a display control device that displays a character pattern on a display screen of a display device, (al) a first area staff storing a character' code that can be converted into a character pattern; A second area is set corresponding to each area of the display screen divided into one area, and stores control information that defines at least a range of addresses of character codes to be read from within the first area. (b) a first address setting means for providing an address for reading a character code from the memory; (C) a second address setting means for providing an address for reading certain control information from the memory; (d) controlling the address generated from the first address setting means based on certain control information read from the memory by the second address setting means, and controlling the address generated from the first address setting means to the memory; A display control comprising control means for updating and controlling the second address setting means to read other control information from the memory when the address given to the control information exceeds the address range specified by the control information. (2) The display device is a sister scan type display device, and the address from the second address setting means is given to the memory within the horizontal retrace period of the rask scan. Range The display control device according to item 1. (5) The control information includes a first parameter that defines a range of addresses on the memory of character codes that are currently output from a first area of the memory; a second parameter defining a maximum range within which the parameter of may be set;
The display control according to claim 1, wherein the first parameter is arbitrarily rewritten with a new first parameter within the range defined by the second parameter. Device. (4) In a display control device that displays a character pattern in each area of a display screen of a display device that is divided into a plurality of areas, (al) a first area that stores a character code that can be converted into a character pattern; , first control information that defines a range of addresses of character codes that can be output from the first area, corresponding to each area of the display screen, and a range of addresses specified by the first control information. (b) a first area for setting an address for outputting a character code from the first area of the memory; address setting means; (C) second address setting means for setting an address for outputting a certain pair of control information from a second area of the memory; (dl) for writing at least the control information stored in the memory; (e) transfer means for transferring at least the control information to be written into the memory; (fl) an address from the first, second and third address setting means; (g) specifying control information read from the second area of the memory and an address output from the first address setting means; and (h) extracting a character code from a certain range of the first area of the first control information. Information indicating the first address to be outputted is given to the first address setting means, and on the condition that the information indicating the last address to output the character code from the range matches in the comparator, other A display control device characterized by having a control unit that updates an address output from the second address setting means so as to output the paired control information from the second area. (5) By the sixth address setting means Claim 4, characterized in that the new first control information transferred via the transfer means is rewritten in the second area of the specified memory at a certain period. Display control device.