JPS59103475A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain a solid-state image pickup element with less fixed pattern noise by signal after setting a potential of vertical signal line to a reference potential of a readout CTD provided above and under a photodetecting section comprising an MOS sensor. CONSTITUTION:A prescribed electric charge exists at each stage of a CTD82 at the end of a horizontal scanning period, the entering into horizontal blanking period and a TX2A and a BLGA are brought into a high level, a BLDA is brought into a level lower than the expected minimum potential of a vertical signal line and the BLDA is brought into high level, then a vertical signal line is clamped to a prescribed potential. When the TX1A goes to high level and an H1A goes to low level, an electric charge transmitted from an input section of a CTD82 is transferred to the vertical signal line. When the vertical signal line goes to high, the signal charge is transferred to the vertical signal line, mixed with a bias charge from the CTD and flows to the CTD82 when the transfer pulse H1A goes to high. Since the vertical signal line of the solid-state image pickup element is clamped to a reference level, the element is not susceptible to the variance in the threshold voltage of each gate and unnecessary charge.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a diode array in the light receiving section and uses a charge transfer element (ChargeTransf) as a readout register.
The present invention relates to a two-dimensional solid-state imaging device (hereinafter simply abbreviated as a photosensor) provided with an er Device (hereinafter abbreviated as C'rD).

Two types of photosensors are conventionally known: a MOS type and a CCD type. Compared to the latter, the former has a higher utilization rate for the chip size and higher sensitivity, but each has its own advantages and disadvantages, such as the output signal being small and signal processing difficult, and there are some areas where it lacks practical level performance. .

As a photo sensor to solve this problem, a photo sensor as shown in FIG. 1 has been proposed, which uses a MOS method in the light receiving section and a readout register CCD method.

Figure 1 shows a conventional example of a photosensor that has a diode array in the light receiving section and a CTD in the readout register.
In the figure, l is a photodiode consisting of a p-n junction, 2 is a vertical switch MO8) transistor (abbreviated as vMO8T),
3Lt, m(7) MOS)-7 register clock φ7
4 is a vertical signal line,
5 is MO8) transistor for horizontal switch (hereinafter 8M08)
(abbreviated as T), 6 is CTD for horizontal reading, 7 is CTD6
This is a preamplifier connected to the . The signal charge read out to the vertical signal line 4 via the VMO8T in synchronization with the pulse φ7 from the scanner 3 is 5M08T in synchronization with the pulse φ.
5 to the CTD 6 and sequentially read out from the preamplifier 7.

The photo sensor shown in Figure 1 was expected to have excellent characteristics as a device that combines the advantages of the MO8 method and the CCD method, but in reality, it has achieved extremely inadequate performance for the following reasons. .

Fig. 2 is a circuit diagram explaining the problem of the photo sensor shown in Fig. 1, in which lO is one taken out of VMO8T, II is the corresponding photodiode, and 12 is 5M08T.
13 schematically shows one storage electrode of the CTD, which is a horizontal register.

Photodiode 11 shown in FIG. vertical signal line 14,
Let the capacitance of each storage electrode 13 of CTD be c, , cv
, and Cc, then Cv ” CF -CC-
--(11) CT in the signal charge QvO taken out to the vertical signal line
Since tQc taken into D is, Qc<Qv, and the signal charge is sufficiently
Unable to import to DVD. Furthermore, the potential change ΔV due to the charge Qv taken out to the vertical signal line 14 is very small compared to the potential change ΔvP due to the optical signal in the photodiode section, so the 5M08T12 will not be sufficiently conductive even when the pulse φ8 is turned on. First, the charge transfer time is very long, and sufficient transfer cannot be performed.

FIG. 3 is an equivalent circuit diagram illustrating a conventional example that solves the above problem. 10 and 14 in the figure are the same as in FIG. In FIG. 3, a transfer gate 15, a storage capacitor 16, and a reset transistor 17 are provided between the vertical signal line 14 and the 5M08T12.

FIG. 4 is a diagram showing an example of the timing of drive pulses of a conventional photosensor, and the direction indicated by arrow 30 is in the on state. The operation of the circuit shown in FIG. 3 will be explained below using the timing shown in FIG. 4.

First, before reading out the signal accumulated in the photodiode 11, φ8. φS and φR are turned on sequentially as shown in 22.23.24, and the pseudo signal due to the dark current accumulated during the horizontal readout time tH (29) is reset to the reset transistor 1.
7 and reset the potential under the storage capacitor 16 to vR. Next, φ7゜φ1. φ8. φ, 25, 26, 27
．． As shown at 28, the signals are sequentially turned on and transferred to the CTD storage gate 13. If vR is set so that when φ is turned on, the electric charge flows from below the storage gate 16 to the vertical signal line 14 side as a source, the potential of the vertical signal line 14 can be lowered. The transfer gate becomes fully conductive. Therefore, when φ is turned on and the storage gate 16 (lower side) becomes the drain side, the charge that previously flowed in from the direct signal line 14 side and the signal charge are combined in a short time. It can be moved to the storage gate 16 side. In other words, a certain amount of charge is reset (
By sending it from the 17 side to the vertical signal line 14, making it flow back to the 16 storage capacitors together with the signal charge sent from the diode array 11 side, and further transferring it to the CTD,
It becomes possible to send most of the signal charges to the CTD within a short time.

(The above transfer operation is performed during the horizontal retrace period 1. (Fig. 4 2)
Everything is done in 1). ) Here, it is also conceivable that the reset group (17) is directly connected to the vertical signal line 14, for example.

However, in such a connection, Cv>C,,Cc.

Since it is C1, even a slight change in vR causes a large change in the amount of charge, and the storage capacitance is 16. CTD accumulation game) 1
Since the potential change at 3 is large, strict control of vR is required, and in reality it is difficult to obtain sufficient characteristics.

Therefore, reset 17 to transfer gate 15 and 5M0
It is extremely important to provide between 8T12.

FIG. 5 is a diagram showing a conventional example based on the above principle, 1
7 are the same as shown in FIG. 1, 41 is a transfer gate, 42 is a storage capacitor, and 43 is a reset gate.

However, in this conventional method, variations in the storage capacitance of each column (16, C in FIG. 3, or 42 in FIG. 5) result in variations in signal charge for each column, and the monitor image taken with this solid-state imaging device So-called fixed pattern noise, consisting of thin vertical stripes, can be seen on the screen. Therefore, countermeasures against this noise are required.

By the way, in a single-chip color solid-state image sensor, it is necessary to perform an interlacing operation and read out the color signal of each pixel. There are various methods for signal readout, but MO
At S centimeters, there is a two-line simultaneous reading method that can provide high-resolution images with no afterimages. (N, K
oike et a11979 l5SCCDige
st pp 193. Figure 6 shows this method. 61 is photodiode l and VMO8
One pixel consists of T2, 62 is a 5M08T circuit, and 63 is a horizontal scanning circuit. During the -horizontal scanning period of a certain field (A field), the signals of two lines, for example, the nth line and the (n+1) line, are projected simultaneously using two output lines 4.4/, and the next field (B field) ) The signals of the (n-1) row and the n row are read out during the -horizontal scanning period. However, as can be easily seen from Fig. 6, the planar structure of the element is
Two vertical output lines are equimetrically required for one pixel, and the area occupied by the photodiode of one pixel is reduced. This leads to a decrease in sensitivity and also makes the planar structure relatively complex and dense, resulting in low yield and high cost.

In order to solve the above problems in MOS Senna, the seventh
The inventions shown in the figures have been filed by the same applicant.

This means that n rows and (
When reading the signal of the (n+1) row, the signal of the nth row is transferred to the storage capacitor column 71 (corresponding to the storage capacitor 16 in FIG. 3) in the first half of the horizontal blanking period, and the signal of the (n+1) row is read in the second half of the horizontal blanking period. The row signals are transferred to the storage capacitor row 72, and then the horizontal shift register 73 is operated during the horizontal scanning period to read the two row signals simultaneously.

However, as described above with reference to FIG. 5, in FIG. 7 as well, charges due to variations in the threshold voltages and capacitances of the two storage capacitor columns 71 and 72 are mixed into the signals of each column as noise. MOS cm in Figure 7 and CCD in Figure 5
Good image quality cannot be obtained just by combining senna.

The present invention provides a solid-state image sensor in which a MOS centimeter (a sensor in which pixels each consisting of a photodiode and a VMO8T are arranged in a matrix) is arranged in the light receiving part, and readout CTDs are provided above and below the MOS centimeter. C for reading one line of signals after setting the upper and lower reference voltages.
I will explain from the TD register.

FIG. 8 is a block diagram of an element configuration of an embodiment of the present invention, FIG. 9 is a schematic circuit diagram, and FIG. , FIG. 11 is a cross-sectional structural diagram of a connecting portion between a CTD (BCD is used here) and a vertical output line. In FIG. 11, 110 is an insulating film (SiO□, etc.)
, 111 is a P-type Si substrate, 112 is an n-type layer, 113 is an n+-type layer, 114 is a SiO2 layer, 115 and 116 are gate electrodes, and 117 and 118 are CTD transfer gate electrodes.

In Fig. 8, 81.85 is CTD (CCD).

BCD, etc.) input part, 87.88 is output part, 82°86
is a charge transfer section. 83 is a vertical scanning circuit, and 84 is a buffer circuit. 89 is a MOS centimeter light receiving section consisting of a photodiode and a vertical switch MOS transistor (VMO8T); 100 and 105 are first transfer gates;
104 is the second transfer gate, 102 and 103 are Bremi/
FIG. 9 shows specific circuits of each of the anti-corrosion circuits.

The key point in the operation of this element is to transfer the signal charge on the vertical signal line to the CTD register within the horizontal blanking period, so below we will use the pulse timing diagram in Figure 10 and the cross-sectional view in Figure 11. explain. FIG. 11 (al is a sectional view of the part corresponding to X-X' in the block diagram of FIG. 8. Also, from (bl to (gl is
) to (g). Furthermore, the broken line shows the potential under the BLGA gate.
These are the potentials of BT and DA.

The CTD operates during the horizontal scanning period, and at the same time transfers each signal to the output stage, it sequentially transfers a certain amount of insulating material from the input section, and at the end of the horizontal scanning period, all the signals have been read out. , a certain amount of charge exists in each stage of the CTD. This is shown in FIG. 11(b).

Entering the horizontal blanking period, Tx2A and BLGA are h
When BLDA goes low, charge flows from BLDA into the vertical signal line. (Fig. 11 (C). After that, when BLDAfhtgh is set, charge flows from the vertical signal line to BLDA, and the vertical signal line is clamped to the potential vvcA shown by the following equation, and the flow of charge stops. Figure (mountain) vyCA = vX2A '+ kX2A
``''''''(''Kokote, v, v is T's h1gh level, x2mu tkX2A
This is the effective threshold voltage (including substrate bias effect) of the X2A second transfer gate 101.

Figure 11 (BI and GA are low in el, BLGA and BLDA are not involved in the following operation. Next, Txl
A goes high and HlA, the transport pulse of the CTD,
When set to low, each bias charge sent from the input section of the CTD is transferred to each vertical signal line. It is necessary to set each potential relationship so that when this H1□ becomes low, the charge is not transferred to the electrode adjacent to the CTD. Specifically, the threshold voltage of the CTD channel, the threshold voltage of the first transfer gate 100, and the transfer pulse H2 of the CTD.
□vXIA-vIkXIA"H2AL-vIIA"
“”(” is fine.

At this time, a certain vertical gate line (corresponding to FIG. 90, potential VG
) goes high, the signal charge of the photodiode in a certain row moves to the respective vertical signal line and mixes with the bias charge from the CTD.

Next, when the CTD transfer pulse I-I, □ is set to high (Fig. 11(f)), the bias charges and signal charges in the vertical signal line are transferred to the CTD until the vertical signal line reaches vvcA in equation (4). flows.

When the transfer pulse TxIA is set low, the vertical signal line and CT
D is electrically cut off, but at this time, the CTD now has a signal charge from the photodiode in addition to the original bias charge. (@11 (g)) Above is C of A channel
T D K Although the operation of inputting the n-th row signal has been shown, the same operation of transferring the (n+1)-th row signal to the other B channel CTD is performed in the latter half of the same horizontal blanking period. Then, CT of both channels A and B during the horizontal scanning period.
D operates, and the signals of two rows are read out sequentially from the two output stages.

However, within this element, the threshold voltage of each gate usually varies to some extent (200 mV to 10 mV), and even if the clamp voltage expressed by equation (4) is focused on the same vertical signal line, The channel clamp voltage and the B channel clamp voltage will be different. B in this element
LD and BLG function to eliminate the negative effects of this variation.

In other words, in FIG. 11(b), at the beginning of signal readout, blooming charges and dark current charges are also stored in the vertical signal line, and due to variations in the threshold voltage between the A channel and the B channel, the vertical I have no idea what the potential of the signal line is.

If the low level of BLD is selected to be lower than the expected lowest potential of the vertical signal line, no matter what the recent potential is, the first
In Figure 1 (dl), the vertical signal line is clamped by vvc of equation (4). That is, BLD.

BLG is the A channel reference level vvc if it is the A channel.
If A is B channel, B channel reference level vvcB
It works to clamp the vertical signal line, and at the same time has the effect of sweeping away unnecessary charges caused by blooming and dark current. This BLD and BLG are one of the points of the present invention.

After each vertical signal line is clamped at VVC, bias charges and desired signal charges enter the vertical signal line, and after the signal is transferred to the CTD, it is clamped at VVC again, so each stage and column Even if the threshold voltage or capacitance varies, fixed pattern noise as seen in the conventional example does not occur. In other words, high image quality and high S/N can be obtained.

The charge transfer rate from the vertical signal line to the CTD, ie, the transfer efficiency l, is approximately expressed by the following equation.

Here, tx is the transfer time, which is 2 μs in Figure @10. Moreover, T can be expressed by the following formula.

Here, Cv is the vertical output line capacity, β is the transfer gate 100
and the series cosodoductance of a transistor of 101 (unit: ■
/v2), QsR is the sum of bias charge and signal charge. For example, Cv=3pF, β-value 200 (p I/
V"), Q, B-(1,5T)Ctort, 7'=0.
2X10-' (81), and the transfer efficiency of equation (6) is 90%.

Although 10% of the charge will remain on the vertical signal line, since the vertical signal line is always cleared before reading out the signal, the sensitivity will only decrease by 10% and the resolution will not deteriorate.

Although the simultaneous reading method for two lines has been described above, the present invention is of course not limited to this. There are two points to this invention.

(2) Before reading a signal, charge is once put into the vertical signal line from the BLD to clear the vertical signal line regardless of the initial voltage.

(2) Rather than injecting bias charges from the drain as in a MOS sensor, charges transferred by CTD are used.

If the present invention is a monochrome sensor, a three-chip color sensor, or a single-chip color sensor and one row of signals is to be read out in one period, it is sufficient to perform the above operations for only one channel.

Also, in the explanation, B CD (Bulk Charge
-transfer device) was used as the CTD, but a surface-type CCD or BBD may be used, and the present invention is not limited to the electrode structure, material, etc.

[Brief explanation of drawings]

Figure 1 shows a conventional MOS centimeter in the light receiving section and C in the readout section.
A schematic circuit diagram showing the outline of a photosensor using a CD, Fig. 2 is an equivalent circuit diagram of the photosensor shown in Fig. 1, Fig. 3 is an equivalent circuit diagram of another conventional photosensor, and Fig. 4 is an equivalent circuit diagram of the photosensor shown in Fig. 3. 5 is a schematic circuit diagram of the photosensor shown in FIG. 3, FIG. 6 is a block diagram of another conventional photosensor, and FIG. 7 is a block diagram of yet another conventional photosensor. , FIG. 8 is a block diagram showing an embodiment of the photosensor of the present invention, FIG. 9 is a schematic circuit diagram of the photosensor shown in FIG. 8, FIG. 10 is a pulse timing chart regarding the A channel of FIG. 8, and FIG. is the CTD of the photo shoot in Figure 8.
FIG. 3 is a cross-sectional structural diagram of a connecting portion between the vertical output line and the vertical output line. 82.86. ...CTD, 81.85. ,, input section of CTD, output section of 87.88...CTT), 891MO
8 Fig. 1 Fig. 2 Fig. 3 Fig. 5↑/'L4 I3C completed) Kenza 1" Figure 4 Od Figure S Figure 6 Figure 7 Continuation of Figure 1 page 0 Inventor Masaaki Nakai 1-280 Higashi Koigakubo, Kokubunji City, Hitachi, Ltd. Author: Kenji Takahashi, Hitachi, Ltd. Central Research Laboratory, 1-280 Higashi-Koigakubo, Kokubunji-shi.0 author: Masakazu Aoki, Hitachi, Ltd. Central Research Laboratory, 1-280 Higashi-Koigakubo, Kokubunji City.0 author: Takemoto-Heo Kokubunji. Hitachi, Ltd. Central Research Laboratory, 1-280 Koigakubo, Kokubunji City 0 Inventor: Haruhisa Ando 1-280-461, Koigakubo, Kokubunji City

Claims (1)

[Claims] 1. Photodiode and vertical switch M as light receiving part
MO consisting of O8T pixels arranged in a matrix
In a solid-state imaging device using an S sensor and equipped with two sets of readout CTDs that read out signals from the MOS centimeter divided into two channels, the potential of the vertical signal line is set to the reference voltage of each channel, and then, - A solid-state imaging device characterized in that the signal for a row is transferred to each readout CTD register.