JPS59100616A - System and circuit for controlling delay of code - Google Patents

Abstract

PURPOSE:To control the delay of phase of a code accurately by a required amount only independently of the kind of said code by constituting the circuit with an RAM, an address counter, an up-down counter, an adder and a multiplexer. CONSTITUTION:The address counter D-1 is counted down always by a clock signal and a parallel output 1 of the D-1 is inputted to the adder D-3 and the multiplexer D-4. On the other hand, a clock signal of a common phase as that to the D-1 is applied to an up-down counter D-2, and its parallel output 2 is applied to the D-3. The D-3 outputs a parallel output 3 being an added value of the parallel outputs 1, 2. Parallel outputs 1, 3 are inputted to the D-4, a parallel output 4 in which the parallel outputs 1, 3 appear alternately by a switching signal 7 is outputted from the D-4. A write address and a read address are disignated alternately to the RAM D-5 by the parallel output 4 and the write of a code 5 to be controlled to the designated address and the read of an output code from the designated address are performed alternately.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for delay-controlling the phase of a digital code such as a PN code (pseudorandom code).

Delay control of the phase of a digital code is necessary in various electronic devices, such as when synchronizing ranging signals of a master station and a slave station in an electronic ranging system.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a delay circuit in such an electronic device that can accurately control the phase of a code by a necessary amount regardless of the type (pattern) of the code.

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart of the embodiment.

D-1 is composed of, for example, an N-stage counter, and includes an address counter (ADRCNTR) for specifying an address to be accessed in a random access memory, which will be described later;
is composed of, for example, an N-stage counter, and an up-down counter (U
/DCNTR), D-3 is composed of, for example, a binary adder, and is an adder (
ADD), D-4 is a multiplexer (MPX) that switches and controls the output value of the address counter D-1 and the output value of the adder D-3, and alternately supplies the output value to the random access memory (described later); D-5 is a multiplexer (MPX); The code input to the address specified by the output of the address counter D-1 and the output of the binary adder D-3 supplied via the multiplexer D-4 is stored, or the code is stored from the specified address. This is a random access memory (RAM, hereinafter referred to as memory) that outputs a code.

Address counter D-1 is constantly counting down by a clock signal applied thereto, and the parallel output 1 of address counter D-1 is input to adder D-3 and multiplexer D-4. On the other hand, the up/down counter D-2 is also supplied with a clock signal having the same phase as the address counter D-1, and its parallel output 2 is input to the adder D-3.

The clock signal to this up/down counter D-2 is
Only the amount of delay required to be given to the controlled code is input, and the process stops thereafter.

The adder D-3 outputs a parallel output 3 which is the sum of the parallel output 1 of the address counter D-1 and the parallel output 2 of the up/down counter D-2. Parallel output 1 of the address counter D-1 and parallel output 3 of the adder D-3 are input to the multiplexer D-4, and from the multiplexer D-4, the parallel output 1 and the parallel output 3 of the adder D-3 are inputted. A parallel output 4 in which 3 and 3 appear alternately is output.

The switching signal 7 also controls the writing and reading of the memo IJ D-5, and the memory D-5 has a write address and a read address sequentially and alternately designated by the parallel output 4 from the multiplexer D-4. Writing of the control code 5 to the specified address and reading of the output code 6 from the specified address are performed alternately.

Since the switching control of the multiplexer D-4 and the loading/reading control of the memory D-5 are performed using the same signal 7, the parallel output 4 of the multiplexer D-4 is connected to the parallel output 1 side of the address counter D-1, for example. When the switch is made, the controlled code 5 is written to the memo IJ D-5, and when the parallel output 4 is switched to the parallel output 2 side of the adder D-3, the output code 6 from the memory D-5 is written. When set to read, the code written to the address specified by the parallel output 1 of the address counter D-1 differs by the phase corresponding to the parallel output 2 of the up/down counter D-2. It will be read out at a (delayed) point in time.

Figure 2 shows the above situation as a time chart, and shows the case where the input code is delayed by a phase corresponding to one cycle of the clock signal and output (that is, the parallel output 2 of the up/down counter D-2). The value of 1lljl
) is shown. Incidentally, the missing portion of the output code 6 (portion represented by a dotted line) can be corrected by using a known sampling circuit at the subsequent stage of the code delay control circuit.

In FIG. 2, the parallel output 1 of the address counter D-1 and the parallel output 2 of the up/down counter D-2 are represented by the LSB signal of the counter, and "1# to ##
6'' indicates the value of the counter in decimal notation, and this is a numerical value that specifies the address of the memory D-5.

As explained above, the present invention provides memo IJ1)=5
The output of is an up/down counter D for input code 5.
The output code 6 is obtained which is delayed by the phase corresponding to the value set in -2, and the present invention has extremely large effects such as being able to easily and freely set the delay amount and obtaining an accurate delay amount. have

The present invention provides a long-period P code, such as an M-sequence code, for example.
Although the present invention provides a system and circuit suitable for accurately delaying an N code by a necessary amount, it can also be applied to time series signals other than PN codes.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure is a time chart showing signal waveforms of each part of the embodiment. (Main symbols) D-1...Address counter (first counter) D-
2... Up-down click (second counter) D
-3... Adder D-4... Multiplexer D-5... Random access memory. Fig. 1 12) Fig. 2 H: High level, L-low bell W: 11 Timing included, Rn1t issued timing leg procedural amendment written by Commissioner of the Japan Patent Office Kazuo Wakasugi 1, Indication of the case Showa da ■ year patent Application No. ZO F';'g2-No. 3, Relationship with the case of the person making the amendment Applicant 4, Agent Address: 330fi 7, Shigesu Building, 2-6-2 Marunouchi, Chiyoda-ku, Tokyo, Subject of amendment IllNm4 The details of the amendment in Shelf 8 of the detailed description of the invention are as shown in the appendix.Amendment The following matters in the specification of the present application will be amended. Note 1, page 4, line 8, the word "common" is corrected to "common". 2. In the 5th line from the bottom of page 5, correct the phrase "parallel output 21 rules" to read "parallel output 3 side." 92-

Claims (1)

[Claims] 1. A code string to be delayed is sequentially written to a memory address, and a code string stored in the address is sequentially read from an address different from the writing address of the memory to output a code string. Code delay control method. 2. A random access memory in which input codes are written and stored codes are read in response to input of a clock signal, and a first counter that sequentially specifies addresses to be accessed in the random access memory by input of the clock signal. a second counter that sets a delay phase value of the input code; and an adder that adds the output value of the first counter and the output value of the second counter.
The output value of the first counter and the output value of the adder are switched in synchronization with the clock signal and alternately supplied to the random access memory. A code write address and a code read address of the random access memory A code delay control circuit consisting of a multiplexer that alternately specifies