JPS5910028A - Oscillating circuit - Google Patents

Abstract

PURPOSE:To avoid consumption of the undesired current, by increasing and decreasing the mutual conductance of an inverter which is set to the oscillating frequency of a signal generating circuit in response to the frequency of a clock signal. CONSTITUTION:An inverter 2 is designed to the minimum mutual conductance gm that is driven by a frequency obtained while a signal generating circuit is working. A clocked inverter 6 is designed to a high mutual conductance gm which can work even with a clock pulse of a higher frequency supplied from a joint 5. In the case of a normal operation performed by the signal generating circuit, the inverter 6 is nonconductive due to a control signal 7. Then the inverter 6 conducts with the signal 7 when a clock pulse of a frequency higher than the inner oscillating frequency is applied to the joint 5. Thus both inverters 2 and 6 have operations parallel to each other. This can increase the mutual inductance gm of a waveform shaping inverter and therefore avoid the useless consumption of current.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an oscillation circuit, and more particularly to an oscillation circuit operable in response to an external clock signal.

[Technical background of the invention]

FIG. 1 shows a typical conventional example of configuring an oscillation circuit using semiconductor elements. According to the same figure, inverter /,! , and a feedback resistor 3 and a crystal oscillator ≠ connected in parallel between the input and output terminals of the inverter. The input of the inverter tacho is connected to the output of the inverter /.

In an oscillation circuit having such a configuration, a sine wave with extremely small amplitude is obtained as the output of the inverter depending on the inverter 1, the feedback resistor 3, and the crystal oscillator ≠ that constitute the signal generating circuit.

In this case, if the supply voltage to the inverter is VDD,
The operating point of the output is approximately E-VITD. Inverter, 2
shapes this sine wave into a rectangular wave, but since the input is a sine wave, a large amount of through current flows during operation. Therefore, in semiconductor circuits that aim for low power consumption, especially LET■, etc., in order to minimize the through current of conventional inverter tachos, the mutual conductance g of the transistors that make up the inverter tacho
The design was to make m as small as possible. That is, when an inverter tacho is configured using, for example, a MOS transistor, mutual conductance is reduced by reducing w and A as the gate length and gate width W of the transistor.

[Problems with back moon technology]

However, in the conventional oscillation circuit shown in FIG. 1, the circuit may be operated by inputting a clock pulse having a frequency different from that of the signal generating circuit through the connection point j between the inverter and the inverter tacho. For example, when testing the operation of an oscillation circuit.

In some cases, an external clock pulse with a frequency higher than the internal oscillation frequency is input from the connection point j.For this reason, conventionally, taking this test into consideration, the transconductance gm of the transistors constituting the inverter λ was calculated based on the actual operation. It was designed to be larger than necessary to drive the clock, and was designed to be able to handle even when a clock pulse with a frequency higher than the internal oscillation frequency was input.

Therefore, as described above, during normal operation, wasteful current is consumed due to the through current.

On the other hand, if a clock pulse with a frequency lower than the internal oscillation frequency is input from the connection point j and the device is operated at a lower frequency, it has the disadvantage that more current than necessary is consumed.

[Purpose of the invention]

The present invention has been made in an attempt to eliminate the above-mentioned drawbacks of the prior art, and when testing is performed by inputting a clock pulse of a frequency different from the oscillation frequency from the outside during the operation of the oscillation circuit, It is an object of the present invention to provide an oscillation circuit in which unnecessary current is not consumed by using a waveform shaping inverter that can change mutual conductance gm optimally for each operation.

[Summary of the invention]

To achieve this objective, according to the invention.

A signal generation circuit that generates a sine wave, and a waveform shaping inverter that converts the sine wave output from the generation circuit into a rectangular wave, and a clock signal that is supplied to a connection point between the signal generation circuit and the inverter. In the oscillation circuit that can operate responsively, the mutual conductance of the inverter, which is determined with respect to the oscillation frequency of the signal generation circuit, can be increased or decreased in accordance with the frequency of the clock signal.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. In each figure, the same reference numerals as in FIG. 1 indicate the same objects. FIG. 1 shows an embodiment of the present invention.

Inverter/
, feedback resistance 3. It is also equipped with a crystal oscillator and a waveform shaping inverter. A clocked inverter 6 is connected in parallel to this inverter λ. The clocked inverter 6 is a type of clock gate type CMOS logic, and in this embodiment, the input signal that arrives as a regular U-turn signal is controlled by a control signal, and the inverting operation is performed by an ON command of the control signal. is executed, and the input signal is cut off by the Hajida-off command. In FIG. 2, the control (U is indicated by number 7).

Here, the inverter tacho is designed to have the minimum transconductance gm driven by the operating frequency of the signal generation circuit, and the clocked inverter t can also be operated by a clock pulse of a higher frequency input from the connection point j. Designed with high mutual conductance gm. Now, this circuit uses a signal generation circuit which is an internal oscillator circuit, and in the case of normal operation, the clocked inverter t is made non-conductive by the control signal 7.
Perform the same operation as .

Next, when a clock pulse with a higher frequency than the internal oscillation frequency is applied to the connection point j, the clocked inverter 2 is made conductive by the control signal 7 and the impark! and clocked inverter 6 operate in parallel. If you do this, it looks like an inverter! It is possible to increase the mutual conductance gm of the waveform shaping impark, which is constituted by a parallel circuit of the clocked inverter t and the clocked inverter t.

FIG. 3 shows another embodiment of the present invention, in which a plurality of inverters A/, 4 are connected to the same impark λ as described above.
u, . . . A3 are connected in an appropriate number to mask slices. In this case, inverter AI,
/, 2,..., arbitrarily select A3 and invert! By controlling the connection so as to connect to the connection point j, it is possible to obtain a mutual conductance gr11 that is suitable for any clock pulse applied to the connection point j.

〔Effect of the invention〕

The present invention enables each of the internal oscillation frequency and the external f-lock signal to be changed by arbitrarily changing the mutual conductance of the impark for waveform shaping with respect to the external clock signal from the connection point as described above. It is possible to respond with the optimal mutual conductance for
An oscillation circuit that can avoid consumption can be provided.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a conventional oscillation circuit, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Fig. 3 is another embodiment 1 of the present invention.
] (C1 (schematic diagram. /, 2 Inverter, 3...Return resistance, Hiroshi...Crystal pendant, j-connection point, 6 Clocked inverter, 7
・System ``111 Shinzuki, AI, Ari, 63... Inverter.

Claims (1)

[Claims] / A signal generating circuit, and a waveform shaping inverter that converts the output of the generating circuit into a rectangular wave. In an oscillation circuit operable in response to a clock signal supplied to a connection point between the signal generation circuit and the inverter, the mutual conductance of the inverter determined with respect to the oscillation frequency of the signal generation circuit is equal to the mutual conductance of the clock signal. An oscillation circuit that can be increased or decreased depending on the frequency. In the oscillation circuit according to claim 1, a clocked inverter is connected in parallel to the inverter, and the mutual conductance is increased by making the clocked inverter conductive, and the mutual conductance is increased by making the clocked inverter conductive. An oscillation circuit configured to reduce the mutual conductance by bringing the transconductance into a state. 3. The oscillation circuit according to claim 1, wherein the mutual conductance is increased or decreased by connecting an arbitrary number of other inverters in parallel to the inverter by mask slicing.